CN101540298B - TFT-LCD array substrate and manufacturing method thereof - Google Patents

Abstract

The invention relates to a TFT-LCD array substrate and a manufacturing method thereof. The manufacturing method comprises the following steps: a gate metallic layer is deposited on the substrate to form a gate electrode and a grid line pattern through a first composition process; a gate insulating layer, a semiconductor layer, a doped semiconductor layer and a source drain metal layer are conditionally deposited to form a source electrode, a drain electrode, a data line and a doped semiconductor layer pattern through a second composition process and a TFT groove is formed; a passivation layer is deposited, a passivation layer and a semiconductor layer pattern are formed through a third composition process and a passivation layer through hole is formed; and a transparent conducting layer is deposited, a pixel electrode is formed through a fourth composition process, and the pixel electrode is connected with the drain electrode through the passivation layer through hole. Compared with the fourth composition process of the slit photoetching technology adopted in the prior art, the invention can remarkably reduce various defective pixels caused by the slit photoetching technology and improves the rate of finished products and the product quality of the TFT-LCD array substrate.

Description

TFT-LCD array substrate and manufacturing method thereof

technical field

The invention relates to a thin film transistor liquid crystal display and a manufacturing method thereof, in particular to a TFT-LCD array substrate and a manufacturing method thereof.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD for short) has the characteristics of small size, low power consumption, and no radiation, and occupies a dominant position in the current flat panel display market. For TFT-LCD, the manufacturing process of the array substrate determines its product performance, yield and price.

In order to effectively reduce the price of TFT-LCD and increase the yield, the manufacturing process of the TFT-LCD array substrate structure (active drive TFT array) has been gradually simplified. Four patterning (4mask) process of slit lithography technology. The core of the four-patterning process is to use the slit photolithography process to replace the second patterning (active layer photolithography) and the third patterning (source-drain electrode photolithography) in the traditional five-step patterning process. The specific process is as follows: firstly, gate lines and gate electrodes are formed by patterning for the first time; then gate insulating layer, semiconductor layer, doped semiconductor layer (ohmic contact layer) and source-drain metal are continuously deposited on the gate lines and gate electrodes. layer; followed by the second patterning, through wet etching, multi-step etching (semiconductor layer etching→ashing→dry etching→doped semiconductor layer etching) to form data lines, active layers, source and drain electrode and TFT channel pattern; then deposit a passivation layer, and form a via hole on the passivation layer by the third patterning; finally deposit a transparent conductive layer, and form a pixel electrode by the fourth patterning. Among them, in the second patterning process, a slit photolithography process is required to form the active layer, source and drain electrodes and TFT channel patterns. The principle of the slit lithography process is to set a slit of a specific size on the mask to control the transmittance of light by generating optical diffraction, thereby selectively controlling the thickness of the photoresist, and the thickness of the photoresist will directly Determine the width-to-length ratio of the TFT channel, that is, the electrical characteristics of the TFT.

The actual production shows that there are still some unavoidable defects in the four-step patterning process using the slit photolithography process in the prior art, for example: due to certain limitations in the manufacturing accuracy of the mask with the slit structure, resulting in different regions There is a certain difference in transmittance, and these differences will cause various defects in the channel area, reduce the uniformity of TFT electrical characteristics on the entire substrate, affect the display quality of TFT-LCD, and may even cause various defects in pixels. Occurs, reducing the yield and product quality to a certain extent. As another example, the multi-step etching process is one of the core processes of the slit photolithography process. Its purpose is to form the active layer and source-drain electrode pattern in the second patterning, and at the same time form the TFT channel. The main process Including the etching of the semiconductor layer, the ashing of the photoresist at the channel, the etching of the source and drain electrodes at the channel, and the etching of the doped semiconductor layer, these etching processes are all completed continuously in the same equipment, which is not only complicated , and the process development is difficult, and the requirements for equipment are very high, so that the yield and product quality cannot be effectively guaranteed.

Contents of the invention

The purpose of the present invention is to provide a TFT-LCD array substrate and its manufacturing method, which can effectively solve the technical defects of the existing quadruple patterning process using slit photolithography technology in terms of product quality, production development cycle and production cost.

In order to achieve the above object, the present invention provides a method for manufacturing a TFT-LCD array substrate, comprising:

Step 1, depositing a gate metal layer on the substrate, and forming gate electrodes and gate line patterns through the first patterning process;

Step 2. Continuously deposit gate insulating layer, semiconductor layer, doped semiconductor layer and source-drain metal layer on the substrate that completed step 1, and form source electrode, drain electrode, data line and doped semiconductor layer pattern through the second patterning process , and form a TFT channel;

Step 3, depositing a passivation layer on the substrate completed in step 2, forming a passivation layer and a semiconductor layer pattern through a third patterning process, and forming passivation layer via holes;

Step 4, depositing a transparent conductive layer on the substrate after step 3, forming a pixel electrode through a fourth patterning process, and connecting the pixel electrode to the drain electrode through the passivation layer via hole.

The step 1 specifically includes: depositing a gate metal layer on the substrate by means of sputtering or thermal evaporation, and forming gate electrodes and gate line patterns on the substrate through the first patterning process.

The step 2 is specifically:

Step 21, continuously depositing a gate insulating layer, a doped semiconductor layer and a semiconductor layer on the substrate completed in step 1 by PECVD method;

Step 22, depositing a source-drain metal layer on the substrate completed in step 21 by sputtering or thermal evaporation;

Step 23. Etching the source-drain metal layer through a second patterning process to form patterns of drain electrodes, source electrodes and data lines;

Step 24, retaining the photoresist, and etching the doped semiconductor layer by dry etching to form the pattern of the doped semiconductor layer and the TFT channel.

The step 3 is specifically:

Step 31, depositing a passivation layer on the substrate completed in step 2 by PECVD method;

Step 32: Etching the gate insulating layer, the passivation layer and the semiconductor layer through the third patterning process to form patterns of the passivation layer and the semiconductor layer, and forming passivation layer via holes at the position of the drain electrode.

The step 4 is specifically:

Step 41, depositing a transparent conductive layer on the substrate completed in step 3 by sputtering or thermal evaporation;

Step 42 , forming a pixel electrode through a fourth patterning process, so that the pixel electrode is connected to the drain electrode through the passivation layer via hole.

In order to achieve the above object, the present invention also provides a TFT-LCD array substrate, comprising:

A gate electrode and a gate line are formed on the substrate;

a gate insulating layer formed on the gate electrode and the gate line;

a semiconductor layer formed on the gate insulating layer and located above the gate electrode;

a doped semiconductor layer formed on the semiconductor layer;

A source electrode, a drain electrode and a data line, wherein the source electrode and the drain electrode are formed on the doped semiconductor layer, and a TFT channel exposing the semiconductor layer is formed between the source electrode and the drain electrode;

A passivation layer is formed on the gate electrode, gate line, source electrode, drain electrode, data line and TFT channel, and a passivation layer via hole is formed at the position of the drain electrode;

A pixel electrode is formed on the substrate and connected to the drain electrode through the passivation layer via hole.

The invention provides a TFT-LCD array substrate and a manufacturing method thereof, which is a four-time patterning process for realizing the preparation of the TFT-LCD array substrate without using a slit photolithography process. In the present invention, the first patterning process is used to form gate lines and gate electrode patterns, the second patterning process is used to form source electrodes, drain electrodes, data lines, doped semiconductor layer patterns and TFT channels, and the third patterning process is used to form The passivation layer and the pattern of the semiconductor layer are used to form the pixel electrode through the fourth patterning process. Compared with the five-step patterning process that does not use the slit photolithography process in the prior art, the patterning process is less, the production efficiency is high, and the production cost is low. Compared with the four-time patterning process using the slit photolithography process in the prior art, the technical advantages of the present invention are reflected in:

(1) Since the slit photolithography process is not used, not only the requirements for the precision of the photolithography layout are reduced, the difficulty of the photolithography process is reduced, and the production cost is reduced, but also the manufacturing process of the TFT-LCD array substrate is simplified and Development in the direction of low cost;

(2) Since the slit lithography process is not used, the development difficulty of lithography process and etching process is greatly reduced, and the production and development cycle is significantly shortened;

(3) Since the slit photolithography process is not used, various pixel defects caused by the slit lithography process can be significantly reduced, and the production yield and product quality of the TFT-LCD array substrate are improved.

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

Description of drawings

Fig. 1 is the flowchart of TFT-LCD array substrate manufacturing method of the present invention;

Fig. 2a is the plane view after the gate line and gate electrode are formed in the first patterning process of the present invention;

Figure 2b is a cross-sectional view of A-A in Figure 2a;

Figure 3a is a plan view of drain electrodes, source electrodes, data lines, doped semiconductor layer patterns and TFT channels formed by the second patterning process of the present invention;

Fig. 3b is a B-B cross-sectional view in Fig. 3a;

Fig. 4a is the plane view after the third patterning process of the present invention forms the passivation layer and semiconductor layer pattern;

Fig. 4b is a C-C cross-sectional view in Fig. 4a;

Fig. 5a is a plan view after forming a pixel electrode in the fourth patterning process of the present invention;

Fig. 5b is a cross-sectional view along D-D in Fig. 5a.

Explanation of reference signs:

1-substrate; 2a-gate electrode; 2b-gate line;

3-gate insulating layer; 4a-semiconductor layer; 4b-doped semiconductor layer;

5a-drain electrode; 5b-source electrode; 5c-data line;

6-TFT channel; 7-passivation layer; 7a-passivation layer via;

8-pixel electrode.

Detailed ways

Fig. 1 is the flowchart of the manufacturing method of TFT-LCD array substrate of the present invention, specifically:

Step 1, depositing a gate metal layer on the substrate, and forming gate electrodes and gate line patterns through the first patterning process;

Step 2. Continuously deposit gate insulating layer, semiconductor layer, doped semiconductor layer and source-drain metal layer on the substrate completed in step 1, and form source electrode, drain electrode, data line and doped semiconductor layer pattern through the second patterning process , and form a TFT channel;

Step 3, depositing a passivation layer on the substrate completed in step 2, forming a passivation layer and a semiconductor layer pattern through a third patterning process, and forming passivation layer via holes;

Step 4, depositing a transparent conductive layer on the substrate after step 3, forming a pixel electrode through a fourth patterning process, and connecting the pixel electrode to the drain electrode through the passivation layer via hole.

The present invention proposes a method for manufacturing a TFT-LCD array substrate that does not use the traditional slit photolithography process. On the one hand, it effectively solves the problems in product quality, production cycle and production cost of the existing four-time patterning process using the slit photolithography process. On the other hand, the technical defects existing in aspects such as TFT-LCD array substrates are developed towards simplification and low cost. 2a to 5b are schematic diagrams of the manufacturing method of the TFT-LCD array substrate of the present invention. The technical solution of the present invention is further described below through the manufacturing process of the TFT-LCD array substrate. In the following description, the patterning process referred to in the present invention includes Photoresist coating, masking, exposure, etching and other processes.

～4000

的栅金属层。栅金属层可以使用Cr、W、Ti、Ta、Mo、Al、Cu等金属及其合金，栅金属层也可以由多层金属薄膜组成。通过第一次构图工艺在基板1上形成栅电极2a和栅线2b图形，如图2a、图2b所示。Fig. 2a is a plan view after forming gate lines and gate electrodes in the first patterning process of the present invention, and Fig. 2b is a cross-sectional view along AA in Fig. 2a. Using sputtering or thermal evaporation, deposit a layer with a thickness of 500 on the substrate 1 (such as a glass substrate or a quartz substrate)

~4000

gate metal layer. The gate metal layer can use Cr, W, Ti, Ta, Mo, Al, Cu and other metals and their alloys, and the gate metal layer can also be composed of multi-layer metal films. Patterns of gate electrodes 2a and gate lines 2b are formed on the substrate 1 through the first patterning process, as shown in FIG. 2a and FIG. 2b.

～4000

的栅绝缘层3、厚度为1000～3500

的半导体层4a和掺杂半导体层4b，栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH₄、NH₃、N₂的混合气体或SiH₂Cl₂、NH₃、N₂的混合气体。之后，在掺杂半导体层4b上通过溅射或热蒸发的方法，沉积厚度为500

～2500的源漏金属层，源漏金属层可以选用Cr、W、Ti、Ta、Mo、Al、Cu等金属及其合金。在沉积完源漏金属层后，通过第二次构图工艺对源漏金属层进行刻蚀，形成漏电极5a、源电极5b和数据线5c图形，如图3a所示。接下来保留光刻胶，采用干刻方法刻蚀掺杂半导体层4b，确保漏电极5a和源电极5b之间的掺杂半导体层(欧姆接触层)4b完全被刻蚀掉，形成掺杂半导体层图形和TFT沟道6，如图3b所示。Fig. 3a is a plan view after drain electrodes, source electrodes, data lines, doped semiconductor layer patterns and TFT channels are formed in the second patterning process of the present invention, and Fig. 3b is a BB cross-sectional view in Fig. 3a. On the substrate with the gate electrode and grid lines patterned, a thickness of 1000 μm is continuously deposited by plasma enhanced chemical vapor deposition (PECVD for short).

~4000

The gate insulating layer 3 with a thickness of 1000 ~3500

The semiconductor layer 4a and the doped semiconductor layer 4b, the gate insulating layer 3 can be selected from oxide, nitride or oxynitride compound, and the corresponding reaction gas can be a mixed gas of SiH ₄ , NH ₃ , N ₂ or SiH ₂ Cl ₂ , A mixed gas of NH ₃ and N ₂ . Afterwards, on the doped semiconductor layer 4b, by sputtering or thermal evaporation, the deposition thickness is 500

~2500 The source and drain metal layers of the source and drain metal layers can be selected from Cr, W, Ti, Ta, Mo, Al, Cu and other metals and their alloys. After the source-drain metal layer is deposited, the source-drain metal layer is etched through a second patterning process to form patterns of the drain electrode 5a, the source electrode 5b and the data line 5c, as shown in FIG. 3a. Next, the photoresist is retained, and the doped semiconductor layer 4b is etched by dry etching to ensure that the doped semiconductor layer (ohmic contact layer) 4b between the drain electrode 5a and the source electrode 5b is completely etched away to form a doped semiconductor layer. Layer pattern and TFT channel 6, as shown in Figure 3b.

～2000

的钝化层7，钝化层可采用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH₄、NH₃、N₂的混合气体或SiH₂Cl₂、NH₃、N₂的混合气体。然后通过第三次构图工艺，进行栅绝缘层、钝化层和半导体层刻蚀，刻蚀气体可选用SF₆/Cl₂、SF₆/O₂、Cl₂/O₂或HCl/O₂，形成钝化层和半导体层图形的同时，在漏电极5a位置形成钝化层过孔7a，如图4a、图4b所示。Fig. 4a is a plan view after forming a passivation layer and a semiconductor layer pattern in the third patterning process of the present invention, and Fig. 4b is a CC cross-sectional view in Fig. 4a. After the above process, the PECVD method is used to deposit a thickness of 700

~2000

Passivation layer 7, the passivation layer can be oxide, nitride or oxynitride compound, the corresponding reaction gas can be SiH ₄ , NH ₃ , N ₂ mixed gas or SiH ₂ Cl ₂ , NH ₃ , N ₂ mixed composition. Then through the third patterning process, the gate insulating layer, passivation layer and semiconductor layer are etched, and the etching gas can be selected from SF ₆ /Cl ₂ , SF ₆ /O ₂ , Cl ₂ /O ₂ or HCl/O ₂ , While forming the passivation layer and the pattern of the semiconductor layer, a passivation layer via hole 7a is formed at the position of the drain electrode 5a, as shown in Fig. 4a and Fig. 4b.

～600的透明导电层，透明导电层可以为氧化铟锡(IndiumTin Oxide，简称ITO)，通过第四次构图工艺形成像素电极8，像素电极8通过钝化层过孔7a与漏电极5a连接，如图5a、图5b所示。Fig. 5a is a plan view after forming a pixel electrode in the fourth patterning process of the present invention, and Fig. 5b is a cross-sectional view along DD in Fig. 5a. After forming the passivation layer via hole 7a, by sputtering or thermal evaporation, the deposition thickness is 300

~600 The transparent conductive layer can be indium tin oxide (IndiumTin Oxide, ITO for short), and the pixel electrode 8 is formed through the fourth patterning process, and the pixel electrode 8 is connected to the drain electrode 5a through the passivation layer via hole 7a, as shown in the figure 5a and Figure 5b.

It can be seen from the above-mentioned manufacturing process of the TFT-LCD array substrate of the present invention that although the present invention is still a four-step patterning process, it is different from the four-step patterning process that uses the slit photolithography process in the prior art. The gate line and gate electrode pattern are formed by the second patterning process, the source electrode, drain electrode, data line pattern, doped semiconductor layer and TFT channel are formed by the second patterning process, and the passivation layer and semiconductor layer are formed by the third patterning process pattern, the pixel electrode is formed through the fourth patterning process. It can be seen that, compared with the four-time patterning process using the slit photolithography process in the prior art, the present invention only forms source electrodes, drain electrodes, data lines, doped semiconductor layer patterns, and TFT trenches in the second patterning process. but does not form a semiconductor layer pattern, and the present invention simultaneously forms a semiconductor layer and a passivation layer pattern in the third patterning process, and the second patterning process adopts a traditional photolithography process, avoiding the use of a slit photolithography process, thereby It is conducive to the improvement of yield rate and product quality. Specifically, in the four patterning processes using the slit photolithography process in the prior art, the TFT channel is formed by the slit photolithography process in the second patterning process. The accuracy has certain limitations, resulting in a certain difference in the transmittance of different regions, which affects the uniformity of the photoresist. In the subsequent multi-step etching process (semiconductor layer etching→ashing→dry etching→doping Semiconductor layer etching) will lead to various defects in the channel region caused by the slit photolithography process. For example, if there is no photoresist in the channel region, channel open defect will easily occur, and if the photoresist in the channel region is thicker, channel bridge defect will easily occur. In the technical solution of the present invention, the traditional photolithography process is used to form the TFT channel in the second patterning process instead of the multi-step etching process based on the slit photolithography process. The process is simple and stable, and it is easy to achieve high-precision control. Not only can avoid defects in TFT channels, improve the uniformity of TFT electrical characteristics on the entire substrate, but also ensure the yield and product quality can be effectively guaranteed. The manufacturing method of the TFT-LCD array substrate of the present invention has simple and stable technology, is easy to realize the technology development, reduces equipment configuration requirements, not only shortens the production cycle, but also reduces the production cost.

In addition, in the above manufacturing process, for the pixel area and the peripheral gate line PAD area, the gate insulating layer 3, the doped semiconductor layer 4b, the semiconductor layer 4a and the passivation layer 7 need to be etched away to expose the gate line. The gate line PAD area refers to the lead part of the gate line, which is actually some vias that expose the gate lines. Its function is to load external input signals to each gate line through these vias, thereby controlling each gate On-line TFT off. The PAD area of the grid line is covered by a transparent conductive layer. Since the transparent conductive layer is a conductive layer, it will not affect the loading of external signals, and the transparent conductive layer can also protect the grid line.

The structural diagram of the TFT-LCD array substrate of the present invention is shown in Fig. 5a and Fig. 5b, including a gate electrode 2a, a gate line 2b, a gate insulating layer 3, and a semiconductor layer respectively formed on a substrate 1 (such as a glass substrate or a quartz substrate). 4a, doped semiconductor layer 4b, drain electrode 5a, source electrode 5b, data line 5c, passivation layer 7 and pixel electrode 8, wherein the gate electrode 2a and gate line 2b are connected and formed on the substrate 1, and the gate insulating layer 3 is formed On the gate electrode 2a and the gate line 2b, the semiconductor layer 4a is formed on the gate insulating layer 3 and is located above the gate electrode 2a, the doped semiconductor layer 4b is formed on the semiconductor layer 4a, and the drain electrode 5a and the source electrode 5b are formed on the semiconductor layer 4a. On the layer 4a, a TFT channel 6 exposing the semiconductor layer 4a is formed between the drain electrode 5a and the source electrode 5b, and the data line 5c is formed simultaneously with the drain electrode 5a and the source electrode 5b, connected to the source electrode 5b, and connected to the gate line 2b vertical cross insulation, passivation layer 7 is formed on gate electrode 2a, gate line 2b, drain electrode 5a, source electrode 5b, data line 5c and TFT channel 6, and passivation layer via hole 7a is formed at the position of drain electrode 5a A pixel electrode 8 is formed on the substrate 1 and connected to the drain electrode 5a through the passivation layer via hole 7a.

2a to 5b are schematic diagrams of the manufacturing process of the TFT-LCD array substrate of the present invention. The foregoing description can further clarify the technical solution of the TFT-LCD array substrate of the present invention, which will not be repeated here.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention without limitation, although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent replacements can be made without departing from the spirit and scope of the technical solutions of the present invention.

Claims (6)

1. a TFT-LCD manufacturing method of array base plate is characterized in that, comprising:

Step 1, on substrate deposition grid metal level, through the first time composition technology form gate electrode and grid line figure;

Step 2, metal level is leaked in successive sedimentation gate insulation layer, semiconductor layer, doping semiconductor layer and source on the substrate of completing steps 1, through the second time composition technology form source electrode, drain electrode, data wire and doped semiconductor layer pattern, and form the TFT raceway groove;

Step 3, on the substrate of completing steps 2 deposit passivation layer, form passivation layer and semiconductor layer figure through composition technology for the third time, and the formation passivation layer via hole;

Step 4, on the substrate of completing steps 3 the deposit transparent conductive layer, form pixel electrode through the 4th composition technology, and pixel electrode is connected with said drain electrode through said passivation layer via hole.

2. TFT-LCD manufacturing method of array base plate according to claim 1; It is characterized in that; Said step 1 is specially: adopt the method for sputter or thermal evaporation, deposition one deck grid metal level on substrate, through the first time composition technology on said substrate, form gate electrode and grid line figure.

3. TFT-LCD manufacturing method of array base plate according to claim 1 is characterized in that, said step 2 is specially:

Step 21, on the substrate of completing steps 1 through PECVD method successive sedimentation gate insulation layer, doping semiconductor layer and semiconductor layer;

Step 22, the method sedimentary origin through sputter or thermal evaporation on the substrate of completing steps 21 leak metal level;

Step 23, through the second time composition technology metal level leaked in said source carry out etching, form drain electrode, source electrode and data wire figure;

Step 24, reservation photoresist adopt dry etching method etching doping semiconductor layer, form doped semiconductor layer pattern and TFT raceway groove.

4. TFT-LCD manufacturing method of array base plate according to claim 1 is characterized in that, said step 3 is specially:

Step 31, the PECVD method deposit passivation layer of on the substrate of completing steps 2, passing through;

Step 32, through composition technology for the third time, carry out gate insulation layer, passivation layer and semiconductor layer etching, form passivation layer and semiconductor layer figure, and in said drain electrode position the formation passivation layer via hole.

5. TFT-LCD manufacturing method of array base plate according to claim 1 is characterized in that, said step 4 is specially:

Step 41, method through sputter or thermal evaporation on the substrate of completing steps 3, the deposit transparent conductive layer;

Step 42, form pixel electrode, said pixel electrode is connected with said drain electrode through said passivation layer via hole through the 4th composition technology.

6. a TFT-LCD array base palte of being made by the said TFT-LCD manufacturing method of array base plate of arbitrary claim in the claim 1～5 is characterized in that, comprising:

Gate electrode and grid line are formed on the substrate;

Gate insulation layer is formed on said gate electrode and the grid line;

Semiconductor layer is formed on the said gate insulation layer, and is positioned at said gate electrode top;

Doping semiconductor layer is formed on the said semiconductor layer;

Source electrode, drain electrode and data wire, wherein source electrode and drain electrode are formed on the said doping semiconductor layer, and between source electrode and drain electrode, form the TFT raceway groove that exposes semiconductor layer;

Passivation layer is formed on said gate electrode, grid line, source electrode, drain electrode, data wire and the TFT raceway groove, and forms passivation layer via hole in the drain electrode position;

Pixel electrode is formed on the said substrate, and is connected with said drain electrode through said passivation layer via hole.

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