CN104659108A - Thin film transistor and manufacturing method thereof as well as array substrate, display panel and display device - Google Patents
Thin film transistor and manufacturing method thereof as well as array substrate, display panel and display device Download PDFInfo
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- CN104659108A CN104659108A CN201510122620.7A CN201510122620A CN104659108A CN 104659108 A CN104659108 A CN 104659108A CN 201510122620 A CN201510122620 A CN 201510122620A CN 104659108 A CN104659108 A CN 104659108A
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- underlay substrate
- film transistor
- thin
- active layer
- semiconductor active
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- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 239000010409 thin film Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims description 34
- 239000012212 insulator Substances 0.000 claims description 25
- 238000000059 patterning Methods 0.000 claims description 22
- 239000010408 film Substances 0.000 claims description 18
- 239000004973 liquid crystal related substance Substances 0.000 claims description 9
- 239000012528 membrane Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 210000002858 crystal cell Anatomy 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a thin film transistor and a manufacturing method thereof as well as an array substrate, a display panel and a display device, aiming at increasing the width to length ratio of the thin film transistor and improving the aperture opening ratio. The thin film transistor comprises a substrate, a grid electrode arranged on the substrate, a grid electrode insulation layer, a semiconductor active layer, a source electrode and a drain electrode, wherein the substrate is provided with a bulge, and the position of the bulge corresponds to that of the semiconductor active layer to be manufactured.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin-film transistor and manufacture method, array base palte, display floater, display unit.
Background technology
The manufactured in recent years electric product such as flat-panel monitor or thin-film solar cells is all configured with thin-film transistor on substrate, thin-film transistor (Thin Film Transistor, TFT) be the Primary Component of liquid crystal display, the service behaviour of display device is had a very important role.Each liquid crystal pixel point in liquid crystal display is all driven by the TFT be integrated in thereafter, thus can accomplish high speed, high brightness, high-contrast display screen information.Along with the rise of intelligent machine, transmitance, the resolution of mobile phone are more and more higher, and this just requires, and aperture opening ratio is high, the size of thin-film transistor is little, in order to meet this requirement, need thin-film transistor to have larger breadth length ratio (W/L).
In sum, in order to adapt to the development of WeiLai Technology, need to produce the larger thin-film transistor of breadth length ratio.
Summary of the invention
Embodiments provide a kind of thin-film transistor and manufacture method, array base palte, display floater, display unit, in order to increase the breadth length ratio of thin-film transistor, improve aperture opening ratio.
A kind of thin-film transistor that the embodiment of the present invention provides, comprise underlay substrate, grid, gate insulator, semiconductor active layer and the source electrode be positioned on described underlay substrate, drain electrode, wherein,
Described underlay substrate is the bossed underlay substrate of tool, and the position of described projection is corresponding with needing the position making semiconductor active layer.
The thin-film transistor provided by the embodiment of the present invention, because this thin-film transistor is arranged on the bossed underlay substrate of tool, wherein the position of projection is corresponding with needing the position making semiconductor active layer, namely the embodiment of the present invention has on the protrusion of certain altitude by being arranged on by the semiconductor active layer of thin-film transistor, therefore, it is possible to increase the breadth length ratio of thin-film transistor, improve aperture opening ratio.
Preferably, described underlay substrate is the bossed glass substrate of tool.
Preferably, the height of described projection is 0.5 micron-7 microns.
The embodiment of the present invention additionally provides a kind of array base palte, and described array base palte comprises above-mentioned thin-film transistor.
The embodiment of the present invention additionally provides a kind of display floater, comprises the array base palte and color membrane substrates that are oppositely arranged, and the liquid crystal layer between described array base palte and described color membrane substrates, and wherein, described array base palte is above-mentioned array base palte.
Preferably, described display floater also comprises the organic insulating film be positioned on array base palte, and described organic insulating film is used as chock insulator matter, and described organic insulating film is provided with via hole in predetermined position.
The embodiment of the present invention additionally provides a kind of display unit, and described display unit comprises above-mentioned display floater.
The embodiment of the present invention additionally provides a kind of manufacture method of thin-film transistor, and the method is included on underlay substrate and makes grid, gate insulator, semiconductor active layer and source electrode, drain electrode, and described method also comprises:
Make the bossed underlay substrate of tool by patterning processes, the position of described projection is corresponding with needing the position making semiconductor active layer.
Preferably, described by the bossed underlay substrate of patterning processes making tool, comprising:
Underlay substrate applies photoresist, described photoresist is exposed, developed, only retain the photoresist of the underlay substrate position needing the position of making semiconductor active layer corresponding;
Wet etching is carried out to the underlay substrate completing above-mentioned steps;
Remove residue photoresist, form the bossed underlay substrate of tool.
Preferably, describedly on underlay substrate, make grid, gate insulator, semiconductor active layer and source electrode, drain electrode, comprising:
On described underlay substrate, grid is made by patterning processes;
The underlay substrate completing above-mentioned steps makes gate insulator;
The underlay substrate completing above-mentioned steps makes semiconductor active layer by patterning processes;
The underlay substrate completing above-mentioned steps makes source electrode and drain electrode by patterning processes.
Accompanying drawing explanation
Fig. 1 is the cross section structure schematic diagram that prior art thin-film transistor is cut in the horizontal direction;
Fig. 2 is the cross section structure schematic diagram that prior art thin-film transistor is vertically cut;
Fig. 3 is the planar structure schematic diagram of prior art thin-film transistor;
The cross section structure schematic diagram that Fig. 4 cuts in the horizontal direction for a kind of thin-film transistor that the embodiment of the present invention provides;
The cross section structure schematic diagram that Fig. 5 vertically cuts for a kind of thin-film transistor that the embodiment of the present invention provides;
The cross section structure schematic diagram of a kind of display floater that Fig. 6 provides for the embodiment of the present invention;
The manufacture method flow chart of a kind of thin-film transistor that Fig. 7 provides for the embodiment of the present invention;
The manufacture method flow chart of a kind of underlay substrate that Fig. 8 provides for the embodiment of the present invention;
Cross section structure schematic diagram in a kind of underlay substrate manufacturing process that Fig. 9 provides for the embodiment of the present invention.
Embodiment
As depicted in figs. 1 and 2, the thin-film transistor of prior art comprises the grid 11 be positioned at above underlay substrate 10, be positioned at the gate insulator 12 on grid 11, be positioned at the semiconductor active layer 13 on gate insulator 12, be positioned at the source electrode 14 on semiconductor active layer 13 and drain electrode 15, W in figure represents the width of thin-film transistor, and L represents the length of thin-film transistor.
Fig. 3 is the planar structure schematic diagram of the thin-film transistor of prior art, in Fig. 3 except thin-film transistor is shown, also show the gate line 20 be connected with the grid of thin-film transistor and the data wire 21 be connected with the source electrode of thin-film transistor, W in figure represents the width of thin-film transistor, and L represents the length of thin-film transistor.Prior art to the transmitance of display floater and the requirement of resolution more and more higher, the breadth length ratio (W/L) of prior art thin-film transistor is relatively little, can not meet the needs of technical development.
In view of this, embodiments provide a kind of thin-film transistor and preparation method thereof, array base palte, display floater, display unit, in order to increase the breadth length ratio of thin-film transistor, improve aperture opening ratio.
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Thin-film transistor that the specific embodiment of the invention provides and preparation method thereof is introduced in detail below in conjunction with accompanying drawing.
The thin-film transistor that the specific embodiment of the invention provides can be the thin-film transistor of bottom gate type, also can be the thin-film transistor of top gate type, can also be the thin-film transistor of other type, the specific embodiment of the invention be construed as limiting the particular type of thin-film transistor.Thin-film transistor in the specific embodiment of the invention is specifically introduced for bottom gate thin film transistor.
As shown in Figure 4 and Figure 5, the specific embodiment of the invention provides a kind of thin-film transistor, comprise underlay substrate 30, be positioned at the grid 31 on underlay substrate 30, gate insulator 32, semiconductor active layer 33 and source electrode 34, drain electrode 35, wherein, underlay substrate 30 is for having the underlay substrate of projection 300, and the position of this projection 300 is corresponding with needing the position making semiconductor active layer.Preferably, underlay substrate 30 in the specific embodiment of the invention for having the glass substrate of projection 300, certainly, in actual production process, underlay substrate can also be the substrates such as ceramic substrate, and the specific embodiment of the invention is not construed as limiting the concrete material of underlay substrate.Preferably, in the specific embodiment of the invention, the height of projection 300 is 0.5 micron-7 microns, and in actual production process, the height of projection 300 sets according to the Production requirement of reality, and the specific embodiment of the invention is not construed as limiting the height of projection.
The cross section structure schematic diagram that Fig. 4 cuts in the horizontal direction for the thin-film transistor that the specific embodiment of the invention provides, L in Fig. 4 represents the length of the thin-film transistor that the specific embodiment of the invention provides, the cross section structure schematic diagram that Fig. 5 vertically cuts for the thin-film transistor that the specific embodiment of the invention provides, the W in Fig. 5 represents the width of the thin-film transistor that the specific embodiment of the invention provides.Compare with length L with the width W of the thin-film transistor of prior art, namely compare with Fig. 1 with Fig. 2 of prior art respectively, the channel region of the thin-film transistor provided due to the specific embodiment of the invention is positioned at and has in the projection 300 of certain altitude, therefore, the width W of the thin-film transistor in the specific embodiment of the invention increases, length L is constant, and the breadth length ratio of the thin-film transistor namely in the specific embodiment of the invention increases relative to prior art.
As shown in Figure 6, the specific embodiment of the invention additionally provides a kind of display floater, and display floater comprises the array base palte 50 and color membrane substrates 51 that are oppositely arranged, and the liquid crystal layer (not shown) between array base palte 50 and color membrane substrates 51.Array base palte in the specific embodiment of the invention comprises the thin-film transistor 52 that the specific embodiment of the invention provides, the display floater that the specific embodiment of the invention provides comprises and is positioned at passivation layer 53 on array base palte 50 and organic insulating film 54, organic insulating film 54 is used as chock insulator matter, organic insulating film 54 is provided with via hole in predetermined position, as: organic insulating film 54 needs the position of routing to be provided with via hole (not shown) in array base palte perimeter leads district, the position be connected with the drain electrode 35 of thin-film transistor in the pixel electrode (not shown) of array base palte is provided with via hole 55.
If the height of projection 300 is thick lower than liquid crystal cell in the specific embodiment of the invention, just need the chock insulator matter making low thickness on color membrane substrates 51, chock insulator matter is corresponding with the position of projection 300.If the height of projection 300 is thick higher than liquid crystal cell, projection 300 is after organic insulating film 54 covers, section difference diminishes, and the organic insulating film 54 above projection 300 directly supports liquid crystal cell, does not need to make chock insulator matter, namely in the specific embodiment of the invention organic insulating film 54 except as except flatness layer, can also be used as chock insulator matter, like this, color membrane substrates 51 just no longer needs to make chock insulator matter, can the production time be saved, reduce production cost.Wherein, section difference here refers between the peak of thin-film transistor position and pixel region difference in height.
The specific embodiment of the invention additionally provides a kind of manufacture method of thin-film transistor, the method is included on underlay substrate and makes grid, gate insulator, semiconductor active layer and source electrode, drain electrode successively, before making grid, the manufacture method of the thin-film transistor that the specific embodiment of the invention provides also comprises: make the bossed underlay substrate of tool by patterning processes, the position of this projection is corresponding with needing the position making semiconductor active layer.
The manufacture method of the thin-film transistor that the specific embodiment of the invention provides is introduced in detail below in conjunction with accompanying drawing.
As shown in Figure 7, the concrete grammar of making thin-film transistor that the specific embodiment of the invention provides comprises:
S701, make tool bossed underlay substrate by patterning processes;
S702, on the bossed underlay substrate of tool, make grid by patterning processes;
S703, on the underlay substrate completing above-mentioned steps, make gate insulator;
S704, on the underlay substrate completing above-mentioned steps, make semiconductor active layer by patterning processes;
S705, on the underlay substrate completing above-mentioned steps, make source electrode and drain electrode by patterning processes.
As shown in Figure 8, the specific embodiment of the invention makes the bossed underlay substrate of tool by patterning processes, comprising:
S801, on underlay substrate, apply photoresist, described photoresist is exposed, developed, only retain the photoresist of underlay substrate position corresponding to the position that needs to make semiconductor active layer;
S802, wet etching is carried out to the underlay substrate completing above-mentioned steps;
S803, removal residue photoresist, form the bossed underlay substrate of tool.
Particularly, as shown in Figure 9, first on underlay substrate, photoresist is applied, the photoresist of specific embodiment of the invention coating is described for positive photoresist, certainly, the photoresist that the specific embodiment of the invention applies on underlay substrate also can be negative photoresist, the photoresist of photolithography plate 80 to coating is adopted to expose afterwards, photolithography plate 80 comprises transparent area 801 and shading region 802, again the underlay substrate after exposure is developed afterwards, in developing process, the photoresist of the position be irradiated by light is removed, the photoresist be not irradiated by light with corresponding position, shading region 802 is retained, photoresist needs the position that is retained corresponding with the follow-up position making semiconductor active layer that needs.Preferably, in order to the accurate contraposition of follow-up making rete in the specific embodiment of the invention, also retain in the specific embodiment of the invention and need to make photoresist corresponding to alignment mark regional location place, in figure, the position of the photoresist 811 retained is corresponding follow-up needs the position making semiconductor active layer, the position in the corresponding alignment mark region, position of the photoresist 812 of reservation.Then wet etching is carried out to the underlay substrate after development; in etching process; be not etched away by the underlay substrate in the region of photoresist 811 and 812 protection, the thickness of the underlay substrate etched away sets according to the demand of actual process, and the specific embodiment of the invention is not construed as limiting it.Finally remove photoresist 811 and 812, form the bossed underlay substrate of tool.
Then, the bossed underlay substrate of the tool of above-mentioned making makes grid by patterning processes, the grid that the specific embodiment of the invention makes is positioned at the top of projection, the detailed process when specific embodiment of the invention makes grid comprises the deposition of gate electrode film, the coating of photoresist, exposure, development, the etching of gate electrode and the removal of photoresist, the concrete manufacturing process of gate electrode is same as the prior art, repeats no more here.Then, the underlay substrate being manufactured with grid makes gate insulator, gate insulator in the specific embodiment of the invention can be silica, silicon nitride, silicon oxynitride etc., and the concrete manufacturing process of gate insulator is same as the prior art, repeats no more here.Then, the underlay substrate being manufactured with gate insulator makes semiconductor active layer by patterning processes, here patterning processes is included in deposit on the semiconductor active layer film that obtains and applies photoresist, photoresist is exposed, develops, the etching of semiconductor active layer film and the rear step removing photoresist of etching, the concrete manufacturing process of semiconductor active layer is same as the prior art, repeats no more here.Then, the underlay substrate being manufactured with semiconductor active layer makes source electrode and drain electrode by patterning processes, here patterning processes is included in deposit on the source-drain electrode film that obtains and applies photoresist, photoresist is exposed, develops, the etching of source-drain electrode film and the rear step removing photoresist of etching, the concrete manufacturing process of source electrode and drain electrode is same as the prior art, repeats no more here.
In sum, the specific embodiment of the invention provides a kind of thin-film transistor and preparation method thereof, before making thin-film transistor, first the bossed underlay substrate of tool is made by patterning processes, the position of this projection is corresponding with needing the position making semiconductor active layer, and namely the specific embodiment of the invention has on the protrusion of certain altitude, relative to prior art by being arranged on by the semiconductor active layer of thin-film transistor, the breadth length ratio of thin-film transistor can be increased, improve the object of aperture opening ratio.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. a thin-film transistor, comprise underlay substrate, grid, gate insulator, semiconductor active layer and the source electrode be positioned on described underlay substrate, drain electrode, it is characterized in that,
Described underlay substrate is the bossed underlay substrate of tool, and the position of described projection is corresponding with needing the position making semiconductor active layer.
2. thin-film transistor according to claim 1, is characterized in that, described underlay substrate is the bossed glass substrate of tool.
3. thin-film transistor according to claim 2, is characterized in that, the height of described projection is 0.5 micron-7 microns.
4. an array base palte, is characterized in that, described array base palte comprises the thin-film transistor described in the arbitrary claim of claim 1-3.
5. a display floater, comprises the array base palte and color membrane substrates that are oppositely arranged, and the liquid crystal layer between described array base palte and described color membrane substrates, it is characterized in that, described array base palte is array base palte according to claim 4.
6. display floater according to claim 5, is characterized in that, described display floater also comprises the organic insulating film be positioned on array base palte, and described organic insulating film is used as chock insulator matter, and described organic insulating film is provided with via hole in predetermined position.
7. a display unit, is characterized in that, described display unit comprises the display floater described in the arbitrary claim of claim 5-6.
8. a manufacture method for the thin-film transistor as described in claim as arbitrary in claim 1-3, the method is included on underlay substrate and makes grid, gate insulator, semiconductor active layer and source electrode, drain electrode, it is characterized in that, described method also comprises:
Make the bossed underlay substrate of tool by patterning processes, the position of described projection is corresponding with needing the position making semiconductor active layer.
9. method according to claim 8, is characterized in that, described by the bossed underlay substrate of patterning processes making tool, comprising:
Underlay substrate applies photoresist, described photoresist is exposed, developed, only retain the photoresist of the underlay substrate position needing the position of making semiconductor active layer corresponding;
Wet etching is carried out to the underlay substrate completing above-mentioned steps;
Remove residue photoresist, form the bossed underlay substrate of tool.
10. method according to claim 8, is characterized in that, describedly on underlay substrate, makes grid, gate insulator, semiconductor active layer and source electrode, drain electrode, comprising:
On described underlay substrate, grid is made by patterning processes;
The underlay substrate completing above-mentioned steps makes gate insulator;
The underlay substrate completing above-mentioned steps makes semiconductor active layer by patterning processes;
The underlay substrate completing above-mentioned steps makes source electrode and drain electrode by patterning processes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510122620.7A CN104659108A (en) | 2015-03-19 | 2015-03-19 | Thin film transistor and manufacturing method thereof as well as array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510122620.7A CN104659108A (en) | 2015-03-19 | 2015-03-19 | Thin film transistor and manufacturing method thereof as well as array substrate, display panel and display device |
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| CN104659108A true CN104659108A (en) | 2015-05-27 |
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| CN201510122620.7A Pending CN104659108A (en) | 2015-03-19 | 2015-03-19 | Thin film transistor and manufacturing method thereof as well as array substrate, display panel and display device |
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| CN105810691A (en) * | 2016-02-05 | 2016-07-27 | 友达光电股份有限公司 | Pixel structure and manufacturing method thereof |
| WO2018223494A1 (en) * | 2017-06-05 | 2018-12-13 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and manufacturing method therefor, and liquid crystal display panel |
| US10615194B2 (en) | 2017-06-05 | 2020-04-07 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd | Array substrates, manufacturing methods thereof, and liquid crystal display (LCD) panels |
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Application publication date: 20150527 |