CN102891170B - LDMOS (laterally diffused metal oxide semiconductor) transistor structure and manufacturing method thereof - Google Patents
LDMOS (laterally diffused metal oxide semiconductor) transistor structure and manufacturing method thereof Download PDFInfo
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- CN102891170B CN102891170B CN201110202772.XA CN201110202772A CN102891170B CN 102891170 B CN102891170 B CN 102891170B CN 201110202772 A CN201110202772 A CN 201110202772A CN 102891170 B CN102891170 B CN 102891170B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 238000002955 isolation Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000012856 packing Methods 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
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Abstract
The invention provides an LDMOS (laterally diffused metal oxide semiconductor) transistor structure and a manufacturing method of the LDMOS transistor structure. The LDMOS transistor structure comprises a semiconductor substrate, a grid region, a body region, a drift region, a source region, a base region, a drain region and a first shallow trench isolation region, wherein the drain region and the first shallow trench isolation region are arranged in the drift region; the drain region comprises a drain doped region and a drain eduction region; the drain doped region surrounds the drain eduction region; the drain doped region is partially located in the first shallow trench isolation region; and the drain eduction region is completely or partially located in the first shallow trench isolation region. The drain region and the first shallow trench isolation structure of the LDMOS transistor structure are partially laminated, so that the normal work of the drain region is ensured, and meanwhile the area occupied by the drain region is reduced, and furthermore the size of a device of an LDMOS transistor is reduced, the output of devices on single wafer is increased, and meanwhile the maximum valid power of given packaging can be reduced while the area of a chip is reduced.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to a kind of LDMOS transistor structure and manufacture method thereof.
Background technology
Along with the development of science and technology, the kind of electronic product is increasing, and the degree of integration of the integrated circuit of electronic product is also more and more higher.BCD (Bipolar CMOS DMOS) technique is the important process realizing smart-power IC (Smart Power IC), be characterized in complementary metal oxide transistor (CMOS), ambipolar (Bipolar) transistor and diffused metal-oxide semiconductor (LDMOS) constant power device being integrated simultaneously, so as will to control, simulate and the various function system such as power on the same chip integrated.In field of power electronics, as the power device in BCD technique, ldmos transistor often needs to bear high pressure, even needs the superhigh pressure bearing kilovolt.Wherein, ldmos transistor is commonly used in high-voltage power integrated circuit, in order to realize the requirement of the aspects such as power control, is usually used in radio-frequency power circuit.Ldmos transistor compared with other transistors, in the device property of key, as gain, the linearity, switch performance, heat dispersion and reduce the aspect advantage such as progression clearly.
Fig. 1 is the structural representation of ldmos transistor in prior art, as shown in Figure 1, in prior art, ldmos transistor comprises: Semiconductor substrate 100, be arranged at the tagma 103 in Semiconductor substrate 100 and drift region 101, be arranged at the gate regions 111 in Semiconductor substrate 100, be arranged at the oxide side wall 115 of both sides, gate regions 111, be arranged at the base 105 in tagma 103 and source region 107, be arranged at the drain region 109 in drift region 101, first shallow channel isolation area 113 and the second shallow channel isolation area 114, wherein usually also be formed with gate oxide 121 between gate regions 111 and Semiconductor substrate 100.
Concrete, as shown in Figure 1, the first shallow channel isolation area 113, drain region 109 and the second shallow channel isolation area 114 is set gradually along the direction away from gate regions 111 in drift region 101, base 105, source region 107, drain region 109 and gate regions 111 are all formed and aim at silicide 117 and be formed at the lead-out wire 119 aimed on silicide 117, for drawing each pole, the second shallow channel isolation area 114 right side area then can make other devices.But, when power output is close, the area of the area ratio bipolar transistor of ldmos transistor is large, therefore, ldmos transistor accounts for the larger area of whole chip, reduce the number of device on single wafer, thus manufacturing cost is improved, chip area also reduces more greatly the maximum effective power of given encapsulation simultaneously.
Summary of the invention
The technical problem to be solved in the present invention is, reduces the size of ldmos transistor, and then improves the output of device on single wafer.
For solving the problem, the invention provides a kind of structure of ldmos transistor, comprise: Semiconductor substrate, be arranged at the gate regions of described semiconductor substrate, be arranged at the tagma in the Semiconductor substrate of both sides, described gate regions and drift region, be arranged at the source region in described tagma and base, and the drain region be arranged in described drift region and the first shallow channel isolation area; Wherein, described drain region comprises leaks doped region and leaks draw-out area, and described leakage doped region surrounds described leakage draw-out area, and described leakage doped region part is arranged in the first shallow channel isolation area, and described leakage draw-out area is all or part of is arranged in described first shallow channel isolation area.
Further, in described ldmos transistor, described leakage draw-out area is all arranged in described first shallow channel isolation area, and described leakage draw-out area overlaps with the sidewall of the first shallow channel isolation area away from described gate regions away from the sidewall of described gate regions.
Further, in described ldmos transistor, the material of filling in described leakage draw-out area is polysilicon.
Further, in described ldmos transistor, also comprise the second shallow channel isolation area be formed in described drift region, described second shallow channel isolation area is positioned at the side of described drain region away from described gate regions.
The present invention also provides a kind of manufacture method of ldmos transistor, comprising:
There is provided semi-conductive substrate, in described Semiconductor substrate, doping forms tagma and drift region, forms the first shallow channel isolation area in described drift region;
Deposition forms gate regions dielectric layer on the semiconductor substrate, and etching forms described gate regions;
Carry out ion implantation technology, in described tagma, form base and source region;
Utilize photoetching and etching technics, formed and leak draw-out area groove in described drift region, and packing material forms leakage draw-out area, described leakage draw-out area is all or part of is arranged in described first shallow channel isolation area;
Carry out ion implantation technology, formed in described drift region and leak doped region, described leakage doped region surrounds described leakage draw-out area, and described leakage doped region part is arranged in described first shallow channel isolation area, and described leakage draw-out area forms drain region jointly with leakage doped region.
Further, in the manufacture method of described ldmos transistor, described leakage draw-out area is all arranged in described first shallow channel isolation area, and described leakage draw-out area overlaps with the sidewall of the first shallow channel isolation area away from described gate regions away from the sidewall of described gate regions.
Further, in the manufacture method of described ldmos transistor, the material of filling in described leakage draw-out area is polysilicon.
Further, in the manufacture method of described ldmos transistor, while described first shallow channel isolation area of formation, form the second shallow channel isolation area, described second shallow channel isolation area is positioned at the side of described drain region away from described gate regions.
Compared with prior art, the drain region of ldmos transistor of the present invention overlaps at least partly with the first fleet plough groove isolation structure, the area that drain region takies is reduced while guarantee drain region normally works, thus the device size of the ldmos transistor reduced, and then the area of the one single chip reduced, improve the output of device on single wafer, meanwhile, the chip area reduced can reduce the maximum effective power of given encapsulation.
Accompanying drawing explanation
Fig. 1 is the structural representation of ldmos transistor in prior art.
Fig. 2 is the structural representation of the ldmos transistor of one embodiment of the invention.
Fig. 3 is the schematic flow sheet of the ldmos transistor manufacture method of one embodiment of the invention.
Fig. 4 a ~ Fig. 4 c is the structural representation in the ldmos transistor manufacture process of one embodiment of the invention.
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention's detailed statement that utilized schematic diagram to carry out, when describing example of the present invention in detail, for convenience of explanation, schematic diagram, should in this, as limitation of the invention not according to general ratio partial enlargement.
Fig. 2 is the structural representation of ldmos transistor one embodiment of the present invention.As shown in Figure 2, the ldmos transistor that one embodiment of the invention provides comprises: Semiconductor substrate 200, be arranged at the gate regions 211 in described Semiconductor substrate 200, be arranged at the tagma 203 in the Semiconductor substrate 200 of both sides, described gate regions 211 and drift region 201, be arranged at the source region 207 in described tagma 203 and base 205, and the drain region 209 be arranged in described drift region 201 and the first shallow channel isolation area 213; Wherein, described drain region 209 comprises leaks doped region 209b and leaks draw-out area 209a, described leakage doped region 209b surrounds described leakage draw-out area 209a, described leakage doped region 209b part is arranged in the first shallow channel isolation area 213, and described leakage draw-out area 209a is all or part of is arranged in described first shallow channel isolation area 213.
Compared to prior art, in the present invention, drain region 209 part of ldmos transistor is arranged in the first shallow channel isolation area 213, and all or part of first shallow trench isolation that is arranged in of the leakage draw-out area 209a in drain region 209 is from 213, namely, leakage draw-out area 209a is away from the sidewall of described gate regions 211 and the overlapping margins of the first shallow channel isolation area 213 or be positioned at outside the first border, shallow channel isolation area 213, to ensure that this sidewall leaking draw-out area 209a can contact with drift region 201, thus make drain region 209 complete electrical extraction, reduce the size that drain region 209 takies simultaneously, thus the device size of the ldmos transistor reduced, improve the output of device on single wafer.
Continue with reference to figure 2, in a preferred embodiment, described leakage draw-out area 209a is all arranged in described first shallow channel isolation area 213, and described leakage draw-out area 209a overlaps with the sidewall away from described gate regions 211 of the first shallow channel isolation area away from the sidewall of gate regions 211, farthest reduces the size that drain region 209 takies.In Fig. 2, drain region 209 is arranged in the cross section Breadth Maximum X of the first shallow channel isolation area 213
1it is exactly the size that ldmos transistor reduces.
Wherein, be usually also formed with gate oxide 221 between gate regions 211 and Semiconductor substrate 200, both sides, described gate regions 211 are formed with oxide side wall 215.In addition, described ldmos transistor also comprises aims at silicide 217 and lead-out wire 219, described aligning silicide 217 is formed on base 205, source region 207, drain region 209 and gate regions 211, and described lead-out wire 219 is formed to be aimed on silicide 217, for drawing each pole.
In 0.18um integrated circuit fabrication process, follow minimum process rule, then lead-out wire 219 is preferably dimensioned to be 0.2um ~ 0.24um, and described drain region 209 is positioned at minimum widith (leaking draw-out area 209a to the distance of leaking 209b border, the doped region) X of the part outside described first shallow channel isolation area 213
2be preferably 0.09um ~ 0.11um, following minimum process rule can reduction of device size to greatest extent, the output improving device on single wafer is certain, and above-mentioned numerical value is not intended to limit the present invention, and also can adjust above-mentioned size accordingly according to concrete technological requirement.
Wherein, the material of filling in described leakage draw-out area 209a is preferably polysilicon, and polysilicon is the material that semiconductor fabrication process is relatively commonly used, and has good electric conductivity.
Further, described ldmos transistor also comprises the second shallow channel isolation area 214, and described second shallow channel isolation area 214 is formed in described drift region 201, and is positioned at the side of described drain region 209 away from gate regions 211, for the isolation between other devices.Described second shallow channel isolation area 214 then can make other devices away from the region of side, gate regions 211, does not repeat them here.
The present invention also provides a kind of manufacture method of ldmos transistor, and please refer to Fig. 2, Fig. 3 and Fig. 4 a ~ Fig. 4 c, the manufacture method of described ldmos transistor comprises the following steps:
Step S01: as shown in fig. 4 a, provides semi-conductive substrate 200, and in described Semiconductor substrate 200, doping forms tagma 203 and drift region 201, and forms the first shallow channel isolation area 213 in described drift region 201.
Concrete, step S01 comprises the following steps: first, utilizes photoetching process at Semiconductor substrate 200 surface-coated photoresist, expose the position needing to form tagma, and carry out ion implantation technology formation tagma 203, described tagma 203 is such as the doping of P type, then removes photoresist; Then, again utilize photoetching process at Semiconductor substrate 200 surface-coated photoresist, expose the position needing to form drift region, and carry out ion implantation technology formation drift region 201, described drift region 201 is such as N-type doping, then removes photoresist; Next, photoetching and etching technics is utilized to form the first groove and the second groove in presumptive area, and deposited oxide is filled in described first groove and the second groove, thus form the first shallow channel isolation area 213 and the second shallow channel isolation area 214, described second shallow channel isolation area 214 is positioned at the side of drain region 209 away from gate regions 211, adjacent with described drain region 209, for the isolation between other devices.Certainly, in other specific embodiment of invention, according to concrete requirement on devices, the second shallow channel isolation area 214 can not also be made.
Step S02: as shown in Figure 4 b, described Semiconductor substrate 200 deposits gate oxide film layer and gate regions film (being such as polysilicon membrane), then photoetching and etching technics is utilized, etch described gate regions film and gate oxide film layer, form gate regions 211 and gate oxide 221, then can form oxide side wall 215 at gate regions 211 sidewall.
Step S03: as illustrated in fig. 4 c, carries out ion implantation technology, forms base 205 and source region 207 in described tagma 203, and described base 205 is such as the doping of P type, and described source region 207 is such as P type doping;
Step S04: then, utilizes photoetching and etching technics, is formed and leak draw-out area groove in described drift region 201, and packing material formation is leaked, and draw-out area 209a, described leakage draw-out area 209a are all or part of is arranged in described first shallow channel isolation area 213; Wherein leak the material of filling draw-out area 209 and be preferably polysilicon.In preferred embodiment, described leakage draw-out area 209a is all arranged in described first shallow channel isolation area 213, and a sidewall of described leakage draw-out area 209a overlaps with the sidewall away from described gate regions 211 of the first shallow channel isolation area, the maximum size reducing drain region 209 and take.
For in integrated circuit 0.18um manufacturing process, follow minimum process rule, then lead-out wire 219 is of a size of 0.2um ~ 0.24um, and namely the width of the part that described drain region 209 is positioned at outside described first shallow channel isolation area 213 leaks draw-out area 209a to the distance X leaking 209b border, doped region
2for 0.09um ~ 0.11um, following minimum process rule can reduction of device size to greatest extent, improves the output of device on single wafer.
Step S05: carry out ion implantation technology, formed in described drift region 201 and leak doped region 209b, described leakage doped region 209b surrounds described leakage draw-out area 209a, described leakage doped region 209b part is arranged in described first shallow channel isolation area 213, described leakage draw-out area 209a forms drain region 209 jointly with leakage doped region 209b, the Doped ions injection technology to leaking draw-out area 209a is completed, the final structure formed as shown in Figure 2 while forming leakage doped region 209b.
In sum, drain region and first fleet plough groove isolation structure of ldmos transistor of the present invention partially overlap, the area that drain region takies is reduced while guarantee drain region normally works, and then the device size of the ldmos transistor reduced, improve the output of device on single wafer, the chip area simultaneously reduced is to the limited degree of the maximum effective power of given encapsulation.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (6)
1. a ldmos transistor, is characterized in that, comprising:
Semiconductor substrate;
Be arranged at the gate regions in described Semiconductor substrate;
Be arranged at the tagma in the Semiconductor substrate of both sides, described gate regions and drift region;
Be arranged at the source region in described tagma and base; And
Be arranged at the drain region in described drift region and the first shallow channel isolation area;
Wherein, described drain region comprises leaks doped region and leaks draw-out area, described leakage doped region surrounds described leakage draw-out area, described leakage doped region part is arranged in described first shallow channel isolation area, described leakage draw-out area is all arranged in described first shallow channel isolation area, and described leakage draw-out area overlaps with the sidewall of the first shallow channel isolation area away from described gate regions away from the sidewall of described gate regions.
2. ldmos transistor as claimed in claim 1, it is characterized in that, the material of filling in described leakage draw-out area is polysilicon.
3. ldmos transistor as claimed in claim 1, it is characterized in that, also comprise the second shallow channel isolation area be formed in described drift region, described second shallow channel isolation area is positioned at the side of described drain region away from described gate regions.
4. a manufacture method for ldmos transistor, is characterized in that, comprising:
Semi-conductive substrate is provided, in described Semiconductor substrate, forms tagma and drift region, and form the first shallow channel isolation area in described drift region;
Form gate regions on the semiconductor substrate;
Base and source region is formed in described tagma;
Utilize photoetching and etching technics, formed and leak draw-out area groove in described drift region, and packing material forms leakage draw-out area, described leakage draw-out area is all arranged in described first shallow channel isolation area;
Carry out ion implantation technology, formed in described drift region and leak doped region, described leakage doped region surrounds described leakage draw-out area, described leakage doped region part is arranged in described first shallow channel isolation area, described leakage draw-out area forms drain region jointly with leakage doped region, leak draw-out area and be all arranged in described first shallow channel isolation area, and described leakage draw-out area overlaps with the sidewall of the first shallow channel isolation area away from described gate regions away from the sidewall of described gate regions.
5. the manufacture method of ldmos transistor as claimed in claim 4, it is characterized in that, the material of filling in described leakage draw-out area is polysilicon.
6. the manufacture method of ldmos transistor as claimed in claim 4, is characterized in that, while described first shallow channel isolation area of formation, form the second shallow channel isolation area, described second shallow channel isolation area is positioned at the side of described drain region away from described gate regions.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1225623A2 (en) * | 2001-01-19 | 2002-07-24 | Chartered Semiconductor Manufacturing, Inc. | A method to form a recessed source drain on a trench side wall with a replacement gate technique |
| CN101197369A (en) * | 2006-12-05 | 2008-06-11 | 东部高科股份有限公司 | Lateral MOS transistor and its manufacturing method |
| CN101266930A (en) * | 2008-04-11 | 2008-09-17 | 北京大学 | A kind of preparation method of lateral double diffused field effect transistor |
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| DE10326523A1 (en) * | 2003-06-12 | 2005-01-13 | Infineon Technologies Ag | Field effect transistor, in particular double-diffused field effect transistor, as well as manufacturing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1225623A2 (en) * | 2001-01-19 | 2002-07-24 | Chartered Semiconductor Manufacturing, Inc. | A method to form a recessed source drain on a trench side wall with a replacement gate technique |
| CN101197369A (en) * | 2006-12-05 | 2008-06-11 | 东部高科股份有限公司 | Lateral MOS transistor and its manufacturing method |
| CN101266930A (en) * | 2008-04-11 | 2008-09-17 | 北京大学 | A kind of preparation method of lateral double diffused field effect transistor |
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