CN104701373A - LDMOS (laterally diffused metal oxide semiconductor) transistor and forming method thereof - Google Patents

Abstract

An LDMOS transistor and its forming method. The LDMOS transistor includes: a semiconductor substrate; a body region and a drift region located in the semiconductor substrate; a gate region located on the semiconductor substrate and spanning the body region and the drift region; source region and base region in the region; drain region located in the drift region; The doping type of the flow region is opposite to the doping type of the drift region; the blocking region located in the semiconductor substrate and surrounding the body region, the drift region and the guiding region, the doping of the blocking region The impurity type is opposite to the doping type of the conduction region. The LDMOS transistor can prevent leakage current from entering into the semiconductor substrate and improve the performance of the LDMOS transistor.

Description

LDMOS transistor and method of forming the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to an LDMOS transistor and a forming method thereof.

Background technique

Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors are mainly used in power integrated circuits, such as RF power amplifiers for mobile phone base stations, and can also be used in high frequency (HF), very high frequency (VHF) and ultra-high frequency (UHF) High frequency (UHF) broadcast transmitters and microwave radar and navigation systems, etc. LDMOS transistor technology brings higher power peak-to-average ratio, higher gain and linearity to a new generation of base station amplifiers, while bringing higher data rates for multimedia services.

For semiconductor devices used as power integrated circuits, their on-resistance (Rdson) and breakdown voltage (Breakdown Voltage, BV) are two important indicators to measure the performance of their devices. For LDMOS transistors, it is generally desired to have a larger breakdown voltage and a smaller on-resistance.

Please refer to FIG. 1, the existing LDMOS transistor includes: a semiconductor substrate 100; a body region 110 in the semiconductor substrate 100, a base region 112 and a source region 111 in the body region 110, wherein the base region 112 is used to adjust and control the body region The potential of 110; in order to increase the breakdown voltage of the LDMOS transistor, a drift region 120 is usually provided in the semiconductor substrate 100, the doping type of the drift region 120 is opposite to that of the body region 110, and the drain region 121 is arranged in the drift region 120 In addition, the LDMOS transistor also includes a gate dielectric layer 131 and a gate 132, which are located on the semiconductor substrate 100 between the source region 111 and the drift region 120.

When the above-mentioned existing LDMOS transistor is an LDNMOS transistor, the semiconductor substrate 100 is P-type doped, and the drift region 120 is N-type doped. At this time, a PN junction is formed between the two. When the drain region 121 receives a negative voltage, The PN junction will be opened, and current will flow into the semiconductor substrate 100, affecting the normal operation of the device.

When the above-mentioned existing LDMOS transistor is an LDPMOS transistor, the semiconductor substrate 100 is N-type doped, the drift region 120 is P-type doped, and a PN junction is still formed between them (the direction is opposite to that of the LDNMOS transistor). , at this time, when the drain region 121 receives a positive voltage, the PN junction will be opened, and current will flow into the semiconductor substrate 100, affecting the normal operation of the device.

It can be seen that the performance of the existing LDMOS transistor needs to be improved urgently.

Contents of the invention

The problem to be solved by the present invention is to provide an LDMOS transistor and its forming method, so as to prevent leakage current between the drift region and the semiconductor substrate in the LDMOS transistor and improve the performance of the LDMOS transistor.

In order to solve the above problems, the present invention provides an LDMOS transistor, comprising:

semiconductor substrate;

a body region and a drift region located in the semiconductor substrate;

a gate region located on the semiconductor substrate and spanning the body region and the drift region;

a source region and a base region located in the body region;

a drain region located in the drift region;

It is characterized in that it also includes:

a diversion region located below the body region and the drift region and connected to the body region and the drift region, the doping type of the diversion region being opposite to that of the drift region;

A blocking region located in the semiconductor substrate and surrounding the body region, the drift region and the conduction region, the doping type of the blocking region is opposite to that of the conduction region.

Optionally, the choke area includes a first choke zone located below the flow diversion area and a second choke zone located on the side of the body area, the first choke zone and the second choke zone connected.

Optionally, the second blocking area has an ohmic contact area.

Optionally, when the doping type of the conduction region is N-type, the dopant ions in the conduction region include phosphorus ions or arsenic ions, and the dopant ion concentration in the conduction region is 1E12cm ^-2 ~ 2E14cm ^-2 , the thickness of the diversion region ranges from 0.1 μm to 3 μm; when the doping type of the diversion region is P-type, the dopant ions in the diversion region include boron ions or boron fluoride ions , the doping ion concentration of the diversion region is 1E12cm ⁻² to 2E14cm ⁻² , and the thickness of the diversion region is 0.1 μm to 3 μm.

Optionally, when the doping type of the first blocking region is N type, the doping ions of the first blocking region include phosphorus ions or arsenic ions, and the doping ions of the first blocking region The concentration is 1E12cm ^-2 ~ 2E14cm ^-2 , the thickness range of the first blocking zone is 0.2μm ~ 4μm; when the doping type of the first blocking zone is P type, the first blocking zone The dopant ions include boron ions and boron fluoride ions, the dopant ion concentration of the first blocking zone is 1E12cm ^-2 ~ 2E14cm ^-2 , and the thickness of the first blocking zone is 0.2μm ~ 4μm.

Optionally, when the doping type of the second blocking region is N type, the doping ions of the second blocking region include phosphorus ions or arsenic ions, and the doping ions of the second blocking region The concentration is 1E12cm ^-2 to 2E14cm ^-2 , and the thickness range of the second blocking zone is 0.8 μm to 4 μm; when the doping type of the second blocking zone is P type, the second blocking zone The dopant ions include boron ions or boron fluoride ions, the dopant ion concentration of the second blocking region is 1E12cm ^-2 -2E14cm ^-2 , and the thickness of the second blocking region is 0.8μm-4μm.

Optionally, the drift region further has a first isolation structure, and the first isolation structure is located between the gate region and the drain region.

Optionally, the body region further has a second isolation structure, and the second isolation structure is located between the base region and the source region.

Optionally, the semiconductor substrate further has a third isolation structure, and the third isolation structure is located between the body region and the second blocking region.

In order to solve the above problems, the present invention also provides a method for forming an LDMOS transistor, including:

Provide semiconductor substrates;

forming a first blocking region in the semiconductor substrate;

forming a conduction region in the semiconductor substrate above the first flow blocking region, the doping type of the conduction region being opposite to the doping type of the flow blocking region;

forming a body region and a drift region in the semiconductor substrate above the conduction region, the drift region having a doping type opposite to that of the conduction region;

A second blocking region is formed in the semiconductor substrate, the second blocking region is connected to the first blocking region, and forms a structure with the first blocking region to surround the body region, the drift region and the conductive region. Blocking area in the flow area;

forming a gate region bridging the body region and the drift region on the semiconductor substrate;

Using the gate region as a mask, a source region and a base region are formed in the body region, and a drain region is formed in the drift region.

Optionally, when performing N-type doping to form the diversion region, the doping ions used include phosphorus ions or arsenic ions, the doping ion concentration used is 1E12cm ^-2 ~ 2E14cm ^-2 , and the energy range used is 70KeV～6000KeV; when performing P-type doping to form the diversion region, the doping ions used include boron ions or boron fluoride ions, and the doping ion concentration used is 1E12cm ^-2 -1E14cm ^-2 , and the energy used The range is 20KeV～6000KeV.

Optionally, when N-type doping is performed to form the first blocking region, the doping ions used include phosphorus ions or arsenic ions, the concentration of the doping ions used is 1E12cm ^-2 to 1E14cm ^-2 , and the energy used is The range is from 100KeV to 10000KeV; when P-type doping is performed to form the first blocking region, the doping ions used include boron ions or boron fluoride ions, and the doping ion concentration used is 1E12cm ^-2 to 1E14cm ^-2 , the adopted energy range is 50KeV～10000KeV.

Optionally, when N-type doping is performed to form the second blocking region, the doping ions used include phosphorus ions or arsenic ions, the concentration of the doping ions used is 1E12cm ^-2 to 1E14cm ^-2 , and the energy used is The range is from 5KeV to 10000KeV; when P-type doping is performed to form the second blocking region, the doping ions used include boron ions or boron fluoride ions, and the doping ion concentration used is 1E12cm ^-2 to 1E14cm ^-2 , the adopted energy range is 10KeV～10000KeV.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, a diversion region is provided under the body region and the drift region, and a flow blocking region is further arranged to surround the body region, the drift region and the diversion region. Wherein the diversion region is connected to the body region and the drift region, and the doping type of the diversion region is opposite to that of the drift region, so a PN junction is formed between the diversion region and the drift region. The PN junction can suppress the leakage current when the reverse voltage is applied to the drain region, and when the forward voltage is applied to the drain region, although the PN junction is opened, after the PN junction is opened, due to the blocking region The function of blocking the leakage current from entering the semiconductor substrate, so the leakage current does not flow into the semiconductor substrate, but flows back into the body region through the conduction region, and can flow away through the base region in the body region, thereby ensuring that the LDMOS Transistors work properly, improving the performance of LDMOS transistors.

Further, a first isolation structure is provided in the drift region, the first isolation structure is located between the gate region and the drain region, the first isolation structure has insulating properties, and the dielectric properties of the entire drift region are increased, so the first isolation structure The entire drift region can share more voltage, thereby increasing the breakdown voltage of the entire LDMOS transistor.

Description of drawings

FIG. 1 is a schematic diagram of an existing LDMOS transistor;

2 is a schematic diagram of an LDMOS transistor according to an embodiment of the present invention;

3 is a schematic diagram of an LDMOS transistor according to another embodiment of the present invention;

4 to 7 are schematic diagrams of the method for forming the LDMOS transistor shown in FIG. 3 .

Detailed ways

In the existing LDMOS transistors, the doping types of the semiconductor substrate and the drift region are different, and a PN junction will be formed between the two. Although this PN junction can suppress the leakage current when the reverse voltage is applied to the drain region, However, when a forward voltage is applied to the drain region, the PN junction will be opened, causing a leakage current between the drift region and the semiconductor, and the current flows into the semiconductor substrate, affecting the normal operation of the LDMOS transistor, and the performance of the entire LDMOS transistor is affected. Influence.

To this end, the present invention provides a novel LDMOS transistor, the LDMOS transistor has a conduction region located below the body region and the drift region, and a blocking region surrounding the body region, the drift region and the conduction region. The diversion region is connected to the body region and the drift region, and the doping type of the diversion region is opposite to that of the drift region, so a PN junction is formed between the diversion region and the drift region, and the PN The junction can also play a role in suppressing the leakage current when the reverse voltage is applied to the drain region. More importantly, when the drain region is applied with a forward voltage, although the PN junction is also opened, after the PN junction is opened, Since the blocking region can block the leakage current from conducting semiconductor, the leakage current will not flow into the semiconductor substrate, but will flow back into the body region through the conduction region, and can flow away through the base region in the body region, thus ensuring The LDMOS transistor works normally and improves the performance of the LDMOS transistor.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 2 , the LDMOS transistor provided by this embodiment is shown in FIG. 2 , which includes a semiconductor substrate 200 with a body region 210 and a drift region 220 in the semiconductor substrate 200, and a gate region ( Not marked), the gate region includes a gate dielectric layer 231 and a gate 232 , and the gate region spans the body region 210 and the drift region 220 . The body region 210 has a source region 211 and a base region 212 therein. The drift region 220 has a drain region 221 therein. The portion of the body region 210 and the drift region 220 below the gate region subsequently forms a channel region under the action of the electric field applied by the gate 232 .

In this embodiment, the semiconductor substrate 200 may be a silicon substrate or a germanium substrate, and may also be a silicon-on-insulator (SOI) substrate, which is not limited in the present invention.

In this embodiment, the material of the gate dielectric layer 231 may be silicon dioxide, and the material of the gate 232 may be polysilicon.

In this embodiment, the drift region 220 is a low-concentration ion-doped region and also a high-resistance region capable of withstanding higher voltage. The drain region 221 is a region doped with high concentration ions.

In this embodiment, the body region 210 can be used to adjust the turn-on voltage of the transistor. There is a space between the body region 210 and the drift region 220 , and the doping type of the body region 210 is opposite to that of the drift region 220 . In the actual manufacturing process, the distance between the body region 210 and the drift region 220 can be adjusted as required.

In this embodiment, the source region 211 may be a region doped with moderate concentrations of ions. The base region 212 can also be a medium-concentration ion-doped region for adjusting and controlling the potential of the body region 210 .

Please refer to FIG. 2 , the LDMOS transistor provided in this embodiment further includes a conduction region 240 and a flow blocking region (not labeled), wherein the flow blocking region includes a first flow blocking section 250 and a second flow blocking section 260 .

The diversion region 240 is located below the body region 210 and the drift region 220 and is connected to the body region 210 and the drift region 220 . The doping type of the guide region 240 is opposite to that of the drift region 220 .

The blocking area includes a first blocking area 250 located below the flow guide area 240 and a second blocking area 260 located on the side of the body region 210. The first blocking area 250 and the second blocking area 260 are connected to form a The entire choke region of is surrounded by the body region 210 , the drift region 220 and the flow guide region 240 . The doping type of the blocking region is opposite to that of the guiding region 240 .

In this embodiment, the second blocking region 260 may have an ohmic contact region 261, and the ohmic contact region 261 is electrically connected to a control potential, and the control potential is used to control the potential of the blocking region, thereby further strengthening the blocking region to prevent current from flowing into the semiconductor. capability of the substrate 200.

When the provided LDMOS transistor is an LDNMOS transistor, the doping type in the semiconductor substrate 200 is P-type, and the doping type in the body region 210 is also P-type (the doping type in the source region 211 and the drain region 221 is N-type , but the doping type of the base region 212 is P-type), while the doping type of the drift region 220 is N-type.

When the provided LDMOS transistor is an LDNMOS transistor, the doping type of the conduction region 240 is P-type at this time, and the dopant ions of the conduction region 240 may include phosphorus ions or arsenic ions, and of course other V main groups. element. The dopant ion concentration of the conduction region 240 is 1E12cm ⁻² to 2E14cm ⁻² . By controlling the dopant ion concentration within the above range, the conduction region 240 formed in this embodiment has good electrical conductivity, and can protect subsequent drains. The current plays a good conduction role. The thickness of the diversion region 240 is in the range of 0.1 μm˜3 μm. In this embodiment, the thickness of the diversion region 240 is controlled to ensure that the diversion region 240 fully conducts the leakage current.

When the provided LDMOS transistor is an LDNMOS transistor, the doping type of the first blocking region 250 is P-type, and the doping ions of the first blocking region 250 may include boron ions or boron fluoride ions, and of course other second blocking regions. Elements of the main group III. The dopant ion concentration of the first blocking region 250 is 1E12cm ⁻² ~ 2E14cm ⁻² , and the thickness of the first blocking region 250 is 0.2 μm ~ 4 μm. By controlling the doping ion concentration and thickness range, the first blocking region 250 formed in this embodiment can form a strong PN junction with the conduction region 240, thereby preventing leakage current from passing through the first blocking region 250 and entering the semiconductor substrate.

When the provided LDMOS transistor is an LDNMOS transistor, the doping type of the second blocking region 260 is also P-type, and the doping ions of the second blocking region 260 may include boron ions or boron fluoride ions, or other Elements of Group III. The dopant ion concentration of the second blocking region 260 is 1E12cm ⁻² ~ 1E14cm ⁻² , the thickness of the second blocking region 260 is 0.8 μm ~ 4 μm, and the thickness of the second blocking region 260 is basically from the semiconductor substrate The surface of the bottom 200 begins to extend toward the inside of the semiconductor substrate 200. In this embodiment, the doping ion concentration and thickness range of the second blocking region 260 are selected as above, so as to prevent the leakage current of the semiconductor substrate by using the second blocking region 260. 200 purposes.

Conversely, when the provided LDMOS transistor is an LDPMOS transistor, the doping type in the semiconductor substrate 200 is N-type, and the doping type of the body region 210 is also N-type (the doping type of the source region 211 and the drain region 221 is P-type, but the doping type of the base region 212 is N-type), and the doping type of the drift region 220 is P-type.

When the provided LDMOS transistor is an LDPMOS transistor, the doping type of the conduction region 240 is N type, the dopant ions of the conduction region 240 may include boron ions or boron fluoride ions, and the dopant ion concentration of the conduction region 240 is 1E12cm ⁻² to 2E14cm ⁻² , and the thickness of the diversion region 240 is in the range of 0.1 μm to 3 μm. For the corresponding reasons, please refer to the related content of the LDNMOS transistor.

When the provided LDMOS transistor is an LDPMOS transistor, the doping type of the first blocking region 250 is P type, and the doping ions of the first blocking region 250 may include phosphorus ions and arsenic ions, and the doping ions of the first blocking region 250 The impurity ion concentration ranges from 1E12cm ⁻² to 2E14cm ⁻² , and the thickness of the first blocking region 250 ranges from 0.2 μm to 4 μm. For the corresponding reasons, please refer to the relevant contents of LDNMOS transistors.

When the provided LDMOS transistor is an LDPMOS transistor, the doping type of the second blocking region 260 is also N-type. The doping ions of the second blocking region 260 may include phosphorus ions and arsenic ions. The impurity ion concentration is 1E12cm ⁻² ˜2E14cm ⁻² , and the thickness of the second blocking region 260 is 0.8 μm˜4 μm. For the corresponding reasons, please refer to the relevant contents of LDNMOS transistors.

Since the LDMOS transistor provided by this embodiment has a blocking region located below the body region 210 and the drift region 220 and surrounding the body region 210, the drift region 220 and the conduction region 240 (by the first blocking region 250 and the second blocking region flow region 260), wherein the flow guide region 240 is connected to the body region 210 and the drift region 220, and the doping type of the flow guide region 240 is opposite to the doping type of the drift region 220, so the flow guide region 240 and the drift region 220 A PN junction is formed between them. This PN junction can suppress the leakage current when the drain region 221 is applied with a reverse voltage. More importantly, when the drain region 221 is applied with a forward voltage, although the PN junction is opened, However, after the PN junction is opened, since the blocking region (especially when the blocking region is electrically connected to the control potential through the ohmic contact region 261) can prevent the leakage current from entering the semiconductor substrate 200, the leakage current will not flow to the semiconductor substrate 200, instead, it flows back into the body region 210 through the conduction region 240, and can flow away through the base region 212 in the body region 210, thereby ensuring the normal operation of the LDMOS transistor and improving the performance of the LDMOS transistor.

The LDMOS transistor provided by another embodiment of this embodiment is shown in FIG. 3 .

The LDMOS transistor provided in this embodiment also includes a semiconductor substrate 300 . There is a gate region (not marked) on the semiconductor substrate 300 , and the gate region includes a gate dielectric layer 331 and a gate 332 . The semiconductor substrate 300 on both sides of the gate region has a body region 310 and a drift region 320 . The body region 310 has a source region 311 and a base region 312 therein. The drift region 320 has a drain region 321 therein.

In this embodiment, there is a diversion region 340 below the body region 310 and the drift region 320 , and the diversion region 340 is connected to the body region 310 and the drift region 320 . The doping type of the guide region 340 is opposite to that of the drift region 320 . There is a first flow blocking zone 350 below the flow guide area 340 , and a second flow blocking zone 360 is located on the side of the body region 310 . The first choke zone 350 is connected to the second choke zone 360 to form a choke zone (not labeled), which encloses the body zone 310 , the drift zone 320 and the diversion zone 340 . The doping type of the blocking region is opposite to that of the guiding region 340 .

In this embodiment, the second blocking region 360 has an ohmic contact region 361, and the ohmic contact region 361 is connected to a control potential, and the control potential is used to control the potential of the blocking region, thereby further strengthening the blocking region to prevent current from flowing into the semiconductor substrate 300 capacity.

For the above structure, please refer to the relevant contents of the previous embodiment. The difference from the previous embodiment is that in this embodiment, the drift region 320 also has a first isolation structure 301, and the first isolation structure 301 is located between the gate region and the drain region. between the regions 321; the body region 310 also has a second isolation structure 302, and the second isolation structure 302 is located between the base region 312 and the source region 311; the semiconductor substrate 300 also has a third isolation structure 303 and a fourth isolation structure 304 , the third isolation structure 303 is located between the body region 310 and the second blocking region 360 , and the fourth isolation structure 304 is located on a side of the second blocking region 360 away from the body region 310 . In addition, in this embodiment, two LDMOS transistors share the same drain region 321 .

In this embodiment, disposing the first isolation structure 301 between the gate region and the drain region 321 can make the entire drift region 320 share more voltage, thereby increasing the breakdown voltage of the entire LDMOS transistor. In other embodiments of the present invention, multiple first isolation structures 301 may be disposed in the drift region 320 .

In this embodiment, disposing the second isolation structure 302 between the base region 312 and the source region 311 can make the control of the potential of the body region 310 by the base region 312 more flexible, and is not affected by the potential of the source region 311 .

In this embodiment, setting the third isolation structure 303 between the body region 310 and the second current blocking subregion 360 can strengthen the insulation effect between the body region 310 and the second current blocking region 360, and the third isolation structure 303 can make the second resistance The isolation effect of flow partition 360 from other structures is enhanced.

In this embodiment, the first isolation structure 301, the second isolation structure 302, the third isolation structure 303, and the fourth isolation structure 304 can all be local oxidation isolation structures, or shallow trench isolation structures, and the four isolation structures The structure can be completed simultaneously using the same process, thereby saving process steps. In other embodiments of the present invention, any one, two or three of the four isolation structures may be formed, and the number of each isolation structure is not limited.

The embodiment of the present invention also provides a method for forming the LDMOS transistor shown in FIG. 3 , please refer to FIG. 3 to FIG. 7 in conjunction.

Referring to FIG. 4 , a semiconductor substrate 300 is provided, and a first isolation structure 301 , a second isolation structure 302 , a third isolation structure 303 and a fourth isolation structure 304 are formed in the semiconductor substrate 300 .

In this embodiment, the formation process of each isolation structure may be: depositing a hard mask layer on the semiconductor substrate 300, forming a patterned photoresist on the hard mask layer, dry etching the hard mask layer for patterning The semiconductor substrate 300 is etched with a patterned hard mask layer as a mask to form a shallow trench; the photoresist is removed; a silicon oxide layer is formed by chemical vapor deposition to fill the shallow trench; chemical mechanical polishing is used to planarize The silicon oxide layer until the hard mask layer is exposed, at which point the nitride acts as a polish stop layer; the hard mask layer is removed.

Referring to FIG. 5 , a first blocking region 350 is formed in the semiconductor substrate 300 .

In this embodiment, when N-type doping is performed to form the first blocking region 350, the doping ions used may include phosphorus ions or arsenic ions, and the doping ion concentration used is 1E12cm ^-2 ~ 1E14cm ^-2 . The energy range is 100KeV-10000KeV, so as to ensure that the thickness of the formed first flow-blocking zone 350 ranges from 0.2 μm to 4 μm, thereby ensuring that the first flow-blocking zone 350 has a good flow-blocking effect. Refer to the corresponding content in Embodiment 1.

In this embodiment, when P-type doping is performed to form the first blocking region 350, the doping ions used may include boron ions or boron fluoride ions, and the doping ion concentration used is 1E12cm ⁻² ~1E14cm ⁻² , The energy range used is 50KeV-10000KeV, so as to ensure that the formed first flow-blocking zone 350 has a thickness ranging from 0.2 μm to 4 μm, thereby ensuring that the first flow-blocking zone 350 has a good flow-blocking effect. Refer to the corresponding content of Embodiment 1.

Please continue to refer to FIG. 5 , a conduction region 340 is formed in the semiconductor substrate 300 above the first blocking region 350 , and the doping type of the conduction region 340 is opposite to that of the blocking region.

In this embodiment, when performing N-type doping to form the diversion region 340, the doping ions used include phosphorus ions or arsenic ions, the doping ion concentration used is 1E12cm ^-2 ~ 2E14cm ^-2 , and the energy range used is 70KeV-6000KeV, so as to ensure that the thickness of the diversion region 340 formed is in the range of 0.1 μm-3 μm, thereby ensuring that the diversion region 340 has a good flow blocking effect, and reference may be made to the corresponding content of the first embodiment.

In this embodiment, when performing P-type doping to form the diversion region 340, the doping ions used include boron ions or boron fluoride ions, and the doping ion concentration used is 1E12cm ^-2 ~ 1E14cm ^-2 , and the energy used The range is 20KeV-6000KeV, so as to ensure that the formed diversion region 340 has a thickness ranging from 0.1 μm to 3 μm, thereby ensuring that the diversion region 340 has a good flow-blocking effect. Refer to the corresponding content of the first embodiment.

Referring to FIG. 6 , a body region 310 and a drift region 320 are formed in the semiconductor substrate 300 above the conduction region 340 , and the doping type of the drift region 320 is opposite to that of the conduction region 340 .

In this embodiment, the formation process of the drift region 320 may be: forming a patterned photoresist on the semiconductor substrate 300, using the patterned photoresist as a mask, and performing the first ion implantation, the first ion implantation is Low-concentration ion implantation to remove photoresist.

In this embodiment, the formation process of the body region 310 may be: forming a patterned photoresist on the semiconductor substrate 300, using the patterned photoresist as a mask, performing a second ion implantation, and removing the photoresist.

Please continue to refer to FIG. 6, a second blocking region 360 is formed in the semiconductor substrate 300, the second blocking region 360 is connected to the first blocking region 350, and forms a surrounding body region 310 and a drift region with the first blocking region 350. 320 and the blocking area of the diversion area 340.

In this embodiment, when performing N-type doping to form the second blocking region 360, the doping ions used include phosphorus ions or arsenic ions, and the concentration of the doping ions used is 1E12cm ^-2 ~ 1E14cm ^-2 , and the energy used is The range is 5KeV-10000KeV, so as to ensure that the thickness of the formed second blocking zone 360 ranges from 0.8 μm to 4 μm, thereby ensuring that the second blocking zone 360 has a good flow-blocking effect. Refer to the corresponding content of the first embodiment.

In this embodiment, when performing P-type doping to form the second blocking region 360, the doping ions used include boron ions or boron fluoride ions, and the doping ion concentration used is 1E12cm ^-2 ~ 1E14cm ^-2 . The energy range is from 10KeV to 10000KeV, so as to ensure that the thickness of the formed second blocking zone 360 is in the range of 0.8 μm to 4 μm, thereby ensuring that the second blocking zone 360 has a good flow blocking effect. Refer to the corresponding content of the first embodiment.

In this embodiment, the formation process of the second blocking region 360 may be as follows: forming a patterned photoresist on the semiconductor substrate 300, using the patterned photoresist as a mask, performing a third ion implantation, removing the photoresist glue.

It should be noted that the order of forming the drift region 320, the body region 310 and the second blocking region 360 can be changed arbitrarily. For example, the body region 310 can be formed first, then the second blocking region 360, and finally the drift region 320 can be formed. .

Referring to FIG. 7 , a gate region spanning the body region 310 and the drift region 320 is formed on the semiconductor substrate 300 .

The gate region includes a gate 332 and a gate dielectric layer 331, the formation process of which may be: growing an oxide layer by thermal oxidation on the semiconductor substrate 300, depositing a polysilicon layer on the oxide layer, and forming an anti-reflection coating ( ARC), forming a patterned photoresist on the anti-reflective coating, using the photoresist as a mask, using a dry etching process to etch the polysilicon layer and the oxide layer to form the gate 332 and the gate dielectric layer 331 , remove the photoresist and the underlying anti-reflective coating.

Please refer to FIG. 7 and FIG. 3 in combination. As shown in FIG. 7, the gate region is used as a mask to form a source region 311 and a base region 312 in the body region 310, and after forming a drain region 321 in the drift region 320, the gate region in FIG. 3 is formed. LDMOS transistor shown.

Although not shown in this embodiment, this embodiment may include the step of forming sidewalls on both sides of the gate region, and then perform ion implantation using the gate region with sidewalls as a mask to form a heavily doped The source region 311 and the heavily doped drain region 321 , as well as the base region 312 located in the body region 310 and the ohmic contact region 361 located in the second blocking region 360 , as shown in FIG. 3 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (13)

1. a ldmos transistor, comprising:

Semiconductor substrate;

Be arranged in tagma and the drift region of described Semiconductor substrate;

Be positioned in described Semiconductor substrate and the gate regions of tagma described in cross-over connection and drift region;

Be arranged in source region and the base in described tagma;

Be arranged in the drain region of described drift region;

It is characterized in that, also comprise:

Be positioned at below described tagma and drift region, and the guiding region be connected with described tagma and drift region, the doping type of described guiding region is contrary with the doping type of described drift region;

Be arranged in described Semiconductor substrate, and surround the choked flow district of described tagma, drift region and guiding region, the doping type in described choked flow district is contrary with the doping type of described guiding region.

2. ldmos transistor as claimed in claim 1, is characterized in that, described choked flow district comprises the first choked flow subregion be positioned at below described guiding region and the second choked flow subregion being positioned at side, described tagma, and described first choked flow subregion is connected with the second choked flow subregion.

3. ldmos transistor as claimed in claim 1, it is characterized in that, described second choked flow subregion has ohmic contact regions.

4. ldmos transistor as claimed in claim 1, it is characterized in that, when the doping type of described guiding region is N-type, the Doped ions of described guiding region comprises phosphonium ion and arsenic ion, and the Doped ions concentration of described guiding region is 1E12cm ^-2~ 2E14cm ^-2, the thickness range of described guiding region is 0.1 μm ~ 3 μm; When the doping type of described guiding region is P type, the Doped ions of described guiding region comprises boron ion and boron fluoride ion, and the Doped ions concentration of described guiding region is 1E12cm ^-2~ 2E14cm ^-2, the thickness range of described guiding region is 0.1 μm ~ 3 μm.

5. ldmos transistor as claimed in claim 1, it is characterized in that, when the doping type of described first choked flow subregion is N-type, the Doped ions of described first choked flow subregion comprises phosphonium ion and arsenic ion, and the Doped ions concentration of described first choked flow subregion is 1E12cm ^-2~ 2E14cm ^-2, the thickness range of described first choked flow subregion is 0.2 μm ~ 4 μm; When the doping type of described first choked flow subregion is P type, the Doped ions of described first choked flow subregion comprises boron ion and boron fluoride ion, and the Doped ions concentration of described first choked flow subregion is 1E12cm ^-2~ 2E14cm ^-2, the thickness range of described first choked flow subregion is 0.2 μm ~ 4 μm.

6. ldmos transistor as claimed in claim 1, it is characterized in that, when the doping type of described second choked flow subregion is N-type, the Doped ions of described second choked flow subregion comprises phosphonium ion and arsenic ion, and the Doped ions concentration of described second choked flow subregion is 1E12cm ^-2~ 2E14cm ^-2, the thickness range of described second choked flow subregion is 0.8 μm ~ 4 μm; When the doping type of described second choked flow subregion is P type, the Doped ions of described second choked flow subregion comprises boron ion and boron fluoride ion, and the Doped ions concentration of described second choked flow subregion is 1E12cm ^-2~ 2E14cm ^-2, the thickness range of described second choked flow subregion is 0.8 μm ~ 4 μm.

7. ldmos transistor as claimed in claim 1, it is characterized in that also having the first isolation structure in described drift region, described first isolation structure is between described gate regions and described drain region.

8. ldmos transistor as claimed in claim 1, it is characterized in that also having the second isolation structure in described tagma, described second isolation structure is between described base and described source region.

9. ldmos transistor as claimed in claim 1, it is characterized in that also having the 3rd isolation structure and the 4th isolation structure in described Semiconductor substrate, described 3rd isolation structure and described 4th isolation structure lay respectively at described second choked flow subregion both sides.

10. a formation method for ldmos transistor, is characterized in that, comprising:

Semiconductor substrate is provided;

The first choked flow subregion is formed in described Semiconductor substrate;

Form guiding region in Semiconductor substrate above described first choked flow subregion, the doping type of described guiding region is contrary with the doping type in described choked flow district;

Form tagma and drift region in Semiconductor substrate above described guiding region, the doping type of described drift region is contrary with the doping type of described guiding region;

In described Semiconductor substrate, form the second choked flow subregion, the first choked flow subregion described in described second choked flow piecewise connection, and form with described first choked flow subregion the choked flow district surrounding described tagma, drift region and guiding region;

Form the gate regions of tagma and drift region described in cross-over connection on the semiconductor substrate;

With described gate regions for mask, in described tagma, form source region and base, in described drift region, form drain region.

11. form method as claimed in claim 10, it is characterized in that, when carrying out N-type doping and forming described guiding region, the Doped ions of employing comprises phosphonium ion and arsenic ion, and the Doped ions concentration of employing is 1E12cm ^-2~ 2E14cm ^-2, the energy range of employing is 70KeV ~ 6000KeV; When carrying out the doping of P type and forming described guiding region, the Doped ions of employing comprises boron ion and boron fluoride ion, and the Doped ions concentration of employing is 1E12cm ^-2~ 1E14cm ^-2, the energy range of employing is 20KeV ~ 6000KeV.

12.. form method as claimed in claim 10, it is characterized in that, when carrying out N-type doping and forming described first choked flow subregion, the Doped ions of employing comprises phosphonium ion and arsenic ion, and the Doped ions concentration of employing is 1E12cm ^-2~ 1E14cm ^-2, the energy range of employing is 100KeV ~ 10000KeV; When carrying out the doping of P type and forming described first choked flow subregion, the Doped ions of employing comprises boron ion, boron fluoride ion, and the Doped ions concentration of employing is 1E12cm ^-2~ 1E14cm ^-2, the energy range of employing is 50KeV ~ 10000KeV.

13. form method as claimed in claim 10, it is characterized in that, when carrying out N-type doping and forming described second choked flow subregion, the Doped ions of employing comprises phosphonium ion and arsenic ion, and the Doped ions concentration of employing is 1E12cm ^-2~ 1E14cm ^-2, the energy range of employing is 5KeV ~ 10000KeV; When carrying out the doping of P type and forming described second choked flow subregion, the Doped ions of employing comprises boron ion and boron fluoride ion, and the Doped ions concentration of employing is 1E12cm ^-2~ 1E14cm ^-2, the energy range of employing is 10KeV ~ 10000KeV.