CN102882527B - Time-to-digital converter and time-to-digital conversion method - Google Patents
Time-to-digital converter and time-to-digital conversion method Download PDFInfo
- Publication number
- CN102882527B CN102882527B CN201110192100.5A CN201110192100A CN102882527B CN 102882527 B CN102882527 B CN 102882527B CN 201110192100 A CN201110192100 A CN 201110192100A CN 102882527 B CN102882527 B CN 102882527B
- Authority
- CN
- China
- Prior art keywords
- pulse signal
- meticulous
- unit
- time
- rising edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 11
- 238000005259 measurement Methods 0.000 claims abstract description 28
- 238000012805 post-processing Methods 0.000 claims abstract description 11
- 230000000630 rising effect Effects 0.000 claims description 49
- 238000003860 storage Methods 0.000 claims description 12
- 244000045947 parasite Species 0.000 claims description 11
- 230000001960 triggered effect Effects 0.000 claims description 4
- 239000013256 coordination polymer Substances 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims description 3
- 238000011160 research Methods 0.000 claims description 2
- 238000012360 testing method Methods 0.000 claims description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Landscapes
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The invention discloses a time-to-digital converter, comprising a measurement control circuit unit, a fine counting interface unit, a fine counting unit, a rough counting unit, a calibration unit, an internal register unit and a post-processing unit, wherein the fine counting unit comprises an annular time delaying chain, a double-edge counter, a fine counting latch and a priority encoder; the annular time delaying chain comprises a group of AND logic gates at the uppermost part of the left side of a chip and at least eight groups of NOR logic gates at the other positions; and all the logic gates are placed in a square shape and are connected end to end. The invention further discloses a time-to-digital conversion method; and a technology of combining fine counting based on gate time delaying and fine counting based on a clock is adopted so that a time interval between a starting pulse signal and a stopping pulse signal is accurately measured, the performance requirements of high precision and large measuring range can be met, and the time-to-digital converter has small occupied space and small deviation.
Description
Technical field
The present invention relates to a kind of time accurate measuring technique field, particularly relate to a kind of time-to-digit converter, the invention still further relates to the method for a kind of time figure conversion.
Background technology
In many practical implementations, for speed, the measurement of distance is often converted into the measurement of time, the precision of Measuring Time directly affects the precision of engineering survey, now more and more higher to various measuring instrument required precision, some modern high New measuring techniques are as more and more extensive in Supersonic application, the time difference of ultrasonic wave co-current flow and counter-current flow is very small, make the required precision of Measuring Time more and more higher, therefore high-precision time interval measurement occupies very important status in actual measurement of engineering, time figure conversion is the common circuit of time measurement, time-to-digital conversion circuit TDC conventional is at present analog to digital hybrid circuit mostly, the impact of ambient noise and dynamic temperature is easily subject to when analog circuit is operated under environment under low pressure, cause job insecurity.The actualizing technology of current time-to-digital conversion circuit TDC has: time-reversal mirror technology, counter technique, vernier caliper technology, current integration technology, temporal interpolation technology, simple use any one technology recited above, is all difficult to the performance requirement simultaneously meeting high accuracy, wide range.
Summary of the invention
First technical problem to be solved by this invention is: the deficiency existed for prior art, a kind of time-to-digit converter is provided, this time-to-digit converter can meet the performance requirement of high accuracy, wide range simultaneously, is applicable to some and requires that high device and occasion use to precision, range.
Second technical problem to be solved by this invention is: the deficiency existed for prior art, provides a kind of time figure conversion method that can realize high accuracy, wide range time measurement.
For solving above-mentioned first technical problem, technical scheme of the present invention is:
A kind of time-to-digit converter, comprising:
Circuit of measurement and control unit, for providing control signal to other modular circuit in described time-to-digit converter, realizes State Transferring;
Meticulous counting interface unit, for receiving the pulse signal that described circuit of measurement and control sends, and start the quantity of meticulous counting unit to the gate that the described pulse delay signal in the interval between described pulse signal rising edge and first clock pulse signal rising edge subsequently passes through and count, described pulse signal comprises beginning pulse signal and stop pulse signal, and the time interval between described beginning pulse signal and stop pulse signal is by being surveyed the time interval;
Described meticulous counting unit comprises annular time delay chain, double-edge counter, meticulous Puzzle lock storage and priority encoder; Described annular time delay chain comprises a group of being positioned at the top, the chip left side and gate and at least eight group NOT logic doors being positioned at other position, and these gates described are put by hollow and end to end; Described double-edge counter, exports as the high position of meticulous count value for measuring the circulation number of turns of described pulse signal in described annular time delay chain; Described meticulous Puzzle lock storage, for locking the position that described pulse signal delays to reach in described annular time delay chain; Described priority encoder, for encode to the output signal of described meticulous Puzzle lock storage and low level as meticulous count value exports;
Thick counting unit, surveys the quantity of the rising edge clock in the time interval for the First Astronautic Research Institute for Measurement and Test and exports as thick count value;
Alignment unit, for calibrating described meticulous counting unit, obtains the calibration data of an internal reference reference clock;
Internal register unit, for storing the count results data of described thick counting unit and meticulous counting unit, calibrating the operation result data of initial data and post-processing unit;
Described post-processing unit, for carrying out computing by the data in described internal register unit according to following formula: T=T
clk(Nc+ (Nf1-Nf2)/Nj), and by the result of described computing stored in described internal register unit, wherein
T is surveyed the time interval, T by described
clkfor the clock cycle, Nc is the thick count value between described beginning pulse signal and stop pulse signal, Nf1 is the meticulous count value between described beginning pulse signal rising edge to first rising edge clock arrived subsequently, Nf2 is the meticulous count value between described stop pulse signal rising edge to first rising edge clock arrived subsequently, and Nj is the calibration data of a described internal reference reference clock.
As a preferred implementation, described meticulous counting interface comprise one or, NAND gate, one with door, T trigger, the first d type flip flop, the second d type flip flop and a 3d flip-flop; Described first d type flip flop, the second d type flip flop and 3d flip-flop have a CP end, D end, a Q output, an Enable Pin and a CLR end respectively; Described T trigger has an input, an input end of clock, an output; The Q output of described first d type flip flop is connected with an input that is described or door; The Q output of described second d type flip flop is connected with another input that is described or door; The D end of described 3d flip-flop is connected with output that is described or door, and the Q output of described 3d flip-flop is connected with an input of described NAND gate; Described or the output of door is connected with another input of described NAND gate; The output of described NAND gate is connected with an input of door with described; Described end with the CLR of described first d type flip flop, the second d type flip flop and 3d flip-flop respectively with the output of door is connected, and the input of described T trigger is connected with output that is described or door.
Improve as one, the output of described meticulous counting unit be provided with series connection the first Parasites Fauna triggered for the trailing edge latched and for isolating the second Parasites Fauna that metastable rising edge triggers.
For solving above-mentioned second technical problem, technical scheme of the present invention is:
A kind of time figure conversion method, comprises the following steps:
(1) pulse signal and stop pulse signal by described circuit of measurement and control unit sends;
(2) when described meticulous counting interface unit receives described beginning pulse signal, the quantity of described meticulous counting unit to the gate that described beginning pulse delay signal in described beginning pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through counts, and obtains meticulous count results Nf1 and deposits in internal register unit;
(3) when described meticulous counting interface unit receives stop pulse signal, the quantity of described meticulous counting unit to the gate that described stop pulse signal in described stop pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through counts, and obtains meticulous count results Nf2 stored in internal register unit;
(4) described thick counting unit counts the rising edge clock between described beginning pulse signal and described stop pulse signal, obtains count results Nc stored in internal register;
(5) described alignment unit is calibrated inner reference clock, obtains count results Nj stored in internal register unit;
(6), after having calibrated, described post-processing unit starts according to formula T=T
clk(Nc+ (Nf1-Nf2)/Nj) carries out computing, and acquired results is exactly the time interval between described beginning pulse signal and stop pulse signal.
After have employed technique scheme, the invention has the beneficial effects as follows:
1, because this time-to-digit converter have employed the technology that the meticulous counting unit based on gate delay combines with the thick counting unit based on clock, wherein, the thick counting unit based on clock have employed straight binary counting method, and consume resource few, range ability is large; Meticulous counting unit based on gate delay utilizes the transmission delay of not gate to come quantization time interval, and this precision is accurate to the delay of single not gate, can realize the measurement of PS level; Thus, this time-to-digit converter can realize high accuracy, the measurement in the wide range time interval.
2, because this time-to-digit converter is provided with meticulous counting interface, because beginning pulse signal, stop pulse signal may be most advanced and sophisticated pulses, meticulous counting interface can make signal pulse extend to rising edge clock arrive when, prevent start pulse signal, stop pulse signal sampling less than.
3, when designing annular time delay chain with FPGA editing machine, one group, the top, chip left side gate realizes and logic, residue gate composition at least eight NOT logic, combinatorial logic unit is put according to hollow, annular time delay chain end to end, owing to have employed this structure, the wire length often organized is substantially identical, and it is shorter, ensure that between logical block, the time delay of interconnection line is roughly equal, reduce line time delay on whole logical block impact, reduce by the incomplete same deviation caused of line, can ensure that each combinational logic time delay is less simultaneously, improve certainty of measurement, the employing of annular time delay chain can reduce the quantity of gate circuit in addition, and then reduces the time discrete that brings of gate delay, economizes on resources, saving chip area.
4, the Parasites Fauna triggered by inserting trailing edge to the output of meticulous counting unit latches, then the Parasites Fauna that rising edge triggers is sent into, this two-stage Parasites Fauna inserted, except the data of catching dynamic latch, also plays the metastable effect of isolation.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is the structured flowchart of time-to-digit converter in the embodiment of the present invention;
Fig. 2 is meticulous counting interface unit circuit in Fig. 1;
Fig. 3 is the structure chart of meticulous counting unit in Fig. 1;
Fig. 4 is the layout of the annular time delay chain of time-to-digit converter in the embodiment of the present invention;
Fig. 5 is the measurement sequential chart of time-to-digit converter in the embodiment of the present invention;
Fig. 6 is the state diagram of circuit of measurement and control unit in Fig. 1;
Wherein, 201. first d type flip flops; 202. second d type flip flops; 203. second d type flip flops; 204. or door; 205. and door; 206. NAND gate; 207.T trigger; 301. with gate group; 302. NOT logic door groups; 303. smart Puzzle lock storages; 304. double-edge counter; 305. thick Puzzle lock storages; 306. priority encoder; 307. first Parasites Fauna; 308. second Parasites Fauna; 309. annular time delay chains.
Embodiment
By reference to the accompanying drawings, the present invention is set forth further below.
As shown in Figure 1, a kind of time-to-digit converter, it comprises circuit of measurement and control unit, meticulous counting interface unit, thick counting unit, meticulous counting unit, alignment unit, internal register unit and post-processing unit.
As shown in Figure 2, meticulous counting interface unit comprises one or 204, one NAND gate 206, and door 205, T trigger 207, first d type flip flop 201, second d type flip flop 202 and a 3d flip-flop 203.
Described first d type flip flop 201, second d type flip flop 202 and 3d flip-flop 203 have a CP end, D end, a Q output, an Enable Pin and a CLR end respectively; Described T trigger 207 has an input, an input end of clock, an output; The Q output of described first d type flip flop 201 is connected with an input that is described or door; The Q output of described second d type flip flop 202 is connected with another input that is described or door; The D end of described 3d flip-flop 203 is connected with output that is described or door, and the Q output of described 3d flip-flop 203 is connected with an input of described NAND gate; Output that is described or door 204 is connected with another input of described NAND gate 206; The output of described NAND gate 206 is connected with an input of door 205 with described; The described output with door 205 is held with the CLR of described first d type flip flop 201, second d type flip flop 202 and 3d flip-flop 203 respectively and is connected, and the input of described T trigger 207 is connected with output that is described or door.
In Fig. 2, the implication of each signal is as follows:
Start: the beginning pulse signal that circuit of measurement and control sends, rising edge is effective;
Start-En: the enable commencing signal pulse that circuit of measurement and control sends, high level is effective;
Stop: the stop pulse signal that measuring circuit sends, rising edge is effective;
Clk: reference clock signal;
Start_u: connect meticulous counting unit, start meticulous counting unit counts, high level is effective;
Stop_u: connect meticulous counting unit, latches meticulous counting unit counts, Low level effective;
Reset_n_c: the double-edge counter resetted in meticulous counting unit completes initialization, Low level effective;
Reset_n: the reset signal that circuit of measurement and control sends;
Start_dff and stop_dff is the pulse signal can caught by clk clock that both start and stop produce respectively, and pulse duration is no more than a clock cycle; When reset_n signal is 0, the output of three registers is 0, and now start_u is 0, and meticulous counting unit is closed; When reset_n signal is 1, when EN signal is 1, the rising edge of register response start and stop and clk signal, when the rising edge of start or stop arrives, export start_u and become 1, start_u=1, start meticulous counting unit, and be continued until the rising edge of clk, now clk is that start_u reads in by the trigger of clock, output becomes 1, become 0 with reset_n_c after start_u NOT-AND operation, make three register CLR, then start_u becomes 0, start_u=0, for new once counting is ready; As long as start or stop is without effective edge, then clk be clock register export be always 0; Stop_u and clk is directly connected, and when counting down to the rising edge of clk, stop_u=1, latches meticulous count results.Because start_u signal is at clk rising edge by CLR, so it always meets settling time, start_dff pulse is made to maintain 1 clock cycle; When start or stop puts 1, exported start_u signal before clk rising edge arrives is high level always, exports stop_u signal and clock signal synchronization.
As shown in Figure 3, meticulous counting unit comprises annular time delay chain 309, double-edge counter 304 and thick Puzzle lock storage 305, meticulous Puzzle lock storage 303 and priority encoder 306; Described annular time delay chain comprises a group of being positioned at the top, the chip left side and gate group 301 and the 15 groups of NOT logic door groups 302 being positioned at other position, and these gates described are put by hollow and end to end; Described double-edge counter 304, exports as the high position of meticulous count value for measuring the circulation number of turns of described pulse signal in described annular time delay chain; Described meticulous Puzzle lock storage 303, for locking the position that described pulse signal delays to reach in described annular time delay chain; Described priority encoder 306, for to encode to the output signal of described meticulous Puzzle lock storage 303 and low level as meticulous count value exports, the output of meticulous counting unit be provided with series connection the first Parasites Fauna 307 triggered for the trailing edge latched and for isolating the second Parasites Fauna 308 that metastable rising edge triggers.
As shown in Figure 4, annular time delay chain FPGA editing machine puts manual arrangement to logical block, one group of gate of the top, the chip left side realizes and logic, remain 15 groups of gates and form 15 NOT logic, 16 combinational logics are put by hollow, the ending of time delay chain connects, and annular time delay chain is used for the meticulous counting of counting unit; Double-edge counter, for measuring the number of turns starting pulse signal circulating propagation in annular time delay chain, the high position as counter exports; Latch and XOR unit, for the position that lock-in detection inhibit signal arrives; Priority encoder, is used for encoding to the output signal of XOR gate, and determine by the coding exported the position that the tested time arrives, the low level as tale exports.Certainly, as required, alogical quantity can do corresponding change, such as, can be more than eight or eight.
As shown in Figure 5, when starting pulse signal or stop pulse signal rising edge is effective, starting meticulous counting unit, starting meticulous counting; When rising edge clock is effective, latch data, and require the meticulous counting unit of initialization after after a while, make it to respond and start pulse signal and stop pulse next time, or other start the signal of meticulous counting unit, between twice meticulous counting, thick counting unit writes down the periodicity of clock, alignment unit is calibrated inner reference clock, post-processing unit, for the data in described internal register unit are carried out computing according to following formula: T=T
clk(Nc+ (Nf1-Nf2)/Nj), and by the result of described computing stored in described internal register unit, wherein
T is surveyed the time interval, T by described
clkfor the clock cycle, Nc is the thick count value between described beginning pulse signal and stop pulse signal, Nf1 is the meticulous count value between described beginning pulse signal rising edge to first rising edge clock arrived subsequently, Nf2 is the meticulous count value between described stop pulse signal rising edge to first rising edge clock arrived subsequently, and Nj is the calibration data of a described internal reference reference clock.
As shown in Figure 6, circuit of measurement and control unit comprises the programmable logic cells based on FPGA; Circuit of measurement and control is used for providing control signal for other modules circuit, control the work of whole circuit, when initialization signal Init is effective, system enters init state, when controller receives the signal of start_dff=1, controller is started working by init state; Meticulous counting unit is by its input of meticulous counting Interface Controller, output; When Init is effective, NextState is still S_idle; When Init is invalid, and when controller input start_dff is effective, the number of times cnt being used for calculating start_dff arrival adds 1 automatically, state enters S_1_0 state by S_idle, now, start thick counting unit and start counting, write enable signal is effective, by the output of meticulous counting unit stored in register, come interim at next clock, enter S_1_1 state, it is enable invalid to write, register address adds 1, then judges whether cnt equals controller input set point; If unequal, enter S_2_0 state, repeat above operation.If equal, enter S_j_0 state and calibrate, coarse counter stops counting, controller is put and is exported s_c=1, starts meticulous counting unit and starts reference clock counting, on next clock edge, enter S_j_1 state, put equally and export s_c=1, meticulous counting unit is still at counting; On next clock edge, enter S_j_2 state, now, meticulous counting unit stops counting, write effectively enable, by a reference clock cycle count value recording by meticulous counting unit stored in register, come at next clock interim, enter S_j_3 state, register address adds 1, write effectively enable, by two clock cycle count values recording continuously by meticulous counting unit stored in register, start post-processing unit and start to calculate the data of depositing in internal register; Then enter S_idle state, wait for and being again initialised.
In fact, the above embodiment of the present invention further discloses a kind of time figure conversion method, and this method can be generalized into following steps:
(1) pulse signal and stop pulse signal by described circuit of measurement and control unit sends;
(2) when described meticulous counting interface unit receives described beginning pulse signal, the quantity of described meticulous counting unit to the gate that described beginning pulse delay signal in described beginning pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through counts, and obtains meticulous count results Nf1 and deposits in internal register unit;
(3) when described meticulous counting interface unit receives stop pulse signal, the quantity of described meticulous counting unit to the gate that described stop pulse signal in described stop pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through counts, and obtains meticulous count results Nf2 stored in internal register unit;
(4) described thick counting unit counts the rising edge clock between described beginning pulse signal and described stop pulse signal, obtains count results Nc stored in internal register unit;
(5) described alignment unit is calibrated inner reference clock, obtains count results Nj stored in internal register unit;
(6), after having calibrated, described post-processing unit starts according to formula T=T
clk(Nc+ (Nf1-Nf2)/Nj) carries out computing, and acquired results is exactly the time interval between described beginning pulse signal and stop pulse signal.
The present invention is not limited to above-mentioned embodiment, and all are based on technical conceive of the present invention, and done technical improvement, all falls among protection scope of the present invention.
Claims (7)
1. a time-to-digit converter, is characterized in that, comprising:
Circuit of measurement and control unit, for providing control signal to other modular circuit in described time-to-digit converter, realizes State Transferring;
Meticulous counting interface unit, for receiving the pulse signal that described circuit of measurement and control sends, and start the quantity of meticulous counting unit to the gate that described pulse delay signal in described pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through and count, described pulse signal comprises beginning pulse signal and stop pulse signal, and the time interval between described beginning pulse signal and stop pulse signal is by being surveyed the time interval;
Described meticulous counting unit comprises annular time delay chain, double-edge counter, meticulous Puzzle lock storage and priority encoder; Described annular time delay chain comprises a group of being positioned at the top, the chip left side and gate and at least eight group NOT logic doors being positioned at other position, and these gates described are put by hollow and end to end; Described double-edge counter, exports as the high position of meticulous count value for measuring the circulation number of turns of described pulse signal in described annular time delay chain; Described meticulous Puzzle lock storage, for locking the position that described pulse signal delays to reach in described annular time delay chain; Described priority encoder, for encode to the output signal of described meticulous Puzzle lock storage and low level as meticulous count value exports;
Thick counting unit, surveys the quantity of the rising edge clock in the time interval for the First Astronautic Research Institute for Measurement and Test and exports as thick count value;
Alignment unit, for calibrating described meticulous counting unit, obtains the calibration data of an internal reference reference clock;
Internal register unit, for storing the count results data of described thick counting unit and meticulous counting unit, calibrating the operation result data of initial data and post-processing unit;
Described post-processing unit, for carrying out computing by the data in described internal register unit according to following formula: T=T
clk(Nc+ (Nf1-Nf2)/Nj), and by the result of described computing stored in described internal register unit, wherein
T is surveyed the time interval, T by described
clkfor the clock cycle, Nc is the thick count value between described beginning pulse signal and stop pulse signal, Nf1 is the meticulous count value between described beginning pulse signal rising edge to first rising edge clock arrived subsequently, Nf2 is the meticulous count value between described stop pulse signal rising edge to first rising edge clock arrived subsequently, and Nj is the calibration data of a described internal reference reference clock.
2. time-to-digit converter as claimed in claim 1, is characterized in that: described NOT logic Men Weishi five groups.
3. time-to-digit converter as claimed in claim 1, is characterized in that: described meticulous counting interface comprise one or, NAND gate, one with door, T trigger, the first d type flip flop, the second d type flip flop and a 3d flip-flop;
Described first d type flip flop, the second d type flip flop and 3d flip-flop have a CP end, D end, a Q output, an Enable Pin and a CLR end respectively; Described T trigger has an input, an input end of clock, an output; The Q output of described first d type flip flop is connected with an input that is described or door; The Q output of described second d type flip flop is connected with another input that is described or door; The D end of described 3d flip-flop is connected with output that is described or door, and the Q output of described 3d flip-flop is connected with an input of described NAND gate;
Described or the output of door is connected with another input of described NAND gate;
The output of described NAND gate is connected with an input of door with described;
Described end with the CLR of described first d type flip flop, the second d type flip flop and 3d flip-flop respectively with the output of door is connected;
The input of described T trigger is connected with output that is described or door.
4. time-to-digit converter as claimed in claim 1, it is characterized in that, described circuit of measurement and control unit comprises the programmable logic cells based on FPGA.
5. time-to-digit converter as claimed in claim 1, is characterized in that: the output of described meticulous counting unit be provided with series connection the first Parasites Fauna triggered for the trailing edge latched and for isolating the second Parasites Fauna that metastable rising edge triggers.
6. time-to-digit converter as claimed in claim 1, it is characterized in that: the even number counter that described double-edge counter comprises odd number counter that rising edge triggers, trailing edge triggers and with the data selector of clock as gate control signal, described odd number counter and the parallel connection of even number counter, the output of described odd number counter and even number counter is connected to described data selector.
7. realize a method for time figure conversion with time-to-digit converter according to claim 1, it is characterized in that, comprise the following steps:
(1) pulse signal and stop pulse signal by described circuit of measurement and control unit sends;
(2) when described meticulous counting interface unit receives described beginning pulse signal, the quantity of described meticulous counting unit to the gate that described beginning pulse delay signal in described beginning pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through counts, and obtains meticulous count results Nf1 and deposits in internal register unit;
(3) when described meticulous counting interface unit receives stop pulse signal, the quantity of described meticulous counting unit to the gate that described stop pulse signal in described stop pulse signal rising edge and the interval subsequently between first rising edge clock signal passes through counts, and obtains meticulous count results Nf2 stored in internal register unit;
(4) described thick counting unit counts the rising edge clock between described beginning pulse signal and described stop pulse signal, obtains count results Nc stored in internal register unit;
(5) described alignment unit is calibrated inner reference clock, obtains count results Nj stored in internal register unit;
(6), after having calibrated, described post-processing unit starts according to formula T=T
clk(Nc+ (Nf1-Nf2)/Nj) carries out computing, and acquired results is exactly the time interval between described beginning pulse signal and stop pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110192100.5A CN102882527B (en) | 2011-07-11 | 2011-07-11 | Time-to-digital converter and time-to-digital conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110192100.5A CN102882527B (en) | 2011-07-11 | 2011-07-11 | Time-to-digital converter and time-to-digital conversion method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102882527A CN102882527A (en) | 2013-01-16 |
| CN102882527B true CN102882527B (en) | 2015-04-22 |
Family
ID=47483712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110192100.5A Active CN102882527B (en) | 2011-07-11 | 2011-07-11 | Time-to-digital converter and time-to-digital conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102882527B (en) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103116163B (en) * | 2013-01-29 | 2015-02-04 | 东南大学 | Laser sense-and-response distance measuring device and control method |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
| CN103297054B (en) | 2013-04-27 | 2016-10-12 | 江西三川水表股份有限公司 | Annular time-to-digit converter and method thereof |
| CN103634010B (en) * | 2013-05-14 | 2016-09-21 | 中国科学院电子学研究所 | A kind of High-precision large-range time-to-digital converter based on difference charging |
| CN103401557B (en) * | 2013-08-12 | 2016-12-07 | 龙芯中科技术有限公司 | Time-to-digit converter and time interval measurement method |
| US9891593B2 (en) | 2014-05-18 | 2018-02-13 | B.G. Negev Technologies And Applications Ltd., At Ben-Gurion University | Fully-digital fully-synthesizable delay-line analog to digital converter |
| CN104539856A (en) * | 2014-12-23 | 2015-04-22 | 天津大学 | TDC-based high-speed column level ADC for imaging sensor |
| CN104614976B (en) * | 2015-02-12 | 2017-03-29 | 中国科学技术大学 | A kind of time-digital converter based on FPGA |
| CN105353600B (en) * | 2015-10-14 | 2017-06-09 | 东南大学 | A kind of high-precision low-power consumption three-stage TDC circuits for being applied to array system |
| US9746832B1 (en) * | 2016-09-09 | 2017-08-29 | Samsung Electronics Co., Ltd | System and method for time-to-digital converter fine-conversion using analog-to-digital converter (ADC) |
| CN106527099B (en) * | 2016-12-09 | 2019-07-26 | 深圳市锐能微科技股份有限公司 | A kind of time-to-digit converter and its time measuring circuit and method |
| CN106886146B (en) * | 2017-01-06 | 2019-08-30 | 南京理工大学 | A TOA Estimation Circuit Based on Digital Delay Circuit |
| CN107037721B (en) * | 2017-06-16 | 2019-06-21 | 中国科学技术大学 | A self-correcting time-to-digital converter |
| JP6903849B2 (en) * | 2017-06-30 | 2021-07-14 | エスゼット ディージェイアイ テクノロジー カンパニー リミテッドＳｚ Ｄｊｉ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．，Ｌｔｄ | Time measurement circuit, time measurement chip, laser detection / ranging system, automation device, and time measurement method |
| JP6891375B2 (en) * | 2017-07-20 | 2021-06-18 | エスゼット ディージェイアイ テクノロジー カンパニー リミテッドＳｚ Ｄｊｉ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．，Ｌｔｄ | Systems and methods for measuring optical distance |
| CN108549006B (en) * | 2018-03-30 | 2021-01-29 | 上海集成电路研发中心有限公司 | Self-error-detecting time-to-digital conversion circuit |
| CN110824889B (en) * | 2019-11-08 | 2021-05-28 | 中山大学 | A Time-to-Digital Converter Based on a Novel Time Amplifier |
| CN111061145B (en) * | 2019-12-30 | 2022-07-05 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| CN111313902B (en) * | 2020-02-04 | 2023-05-05 | 深圳市纽瑞芯科技有限公司 | Successive approximation two-dimensional vernier time-to-digital converter circuit and implementation method |
| CN114614817A (en) * | 2020-12-09 | 2022-06-10 | 上海禾赛科技有限公司 | Circuit for time-to-digital converter, lidar, and method of measuring time |
| CN112506029B (en) * | 2020-12-11 | 2022-04-22 | 重庆邮电大学 | TDC circuit system adopting multiple annular delay chains |
| EP4254793A4 (en) * | 2020-12-25 | 2024-02-21 | Huawei Technologies Co., Ltd. | Multi-phase clock generation circuit |
| CN113325429B (en) * | 2021-05-17 | 2024-05-17 | 武汉光迹融微科技有限公司 | Time-to-digital converter with photon time correlation detection function |
| CN114460830A (en) * | 2021-09-27 | 2022-05-10 | 桂林电子科技大学 | A Novel Time-to-Digital Conversion Integrated Circuit |
| CN113835333B (en) * | 2021-09-29 | 2022-08-12 | 武汉市聚芯微电子有限责任公司 | Time-to-digital conversion device and time-to-digital conversion method |
| CN114114885A (en) * | 2021-11-01 | 2022-03-01 | 西北工业大学 | A high-precision time measurement front-end readout circuit based on TOT mode |
| CN116844620B (en) * | 2022-03-23 | 2024-05-03 | 长鑫存储技术有限公司 | Signal sampling circuit and semiconductor memory |
| CN116087628B (en) * | 2023-04-10 | 2023-07-04 | 国仪量子(合肥)技术有限公司 | Measurement method, device and storage medium |
| CN118300578B (en) * | 2024-05-16 | 2024-08-30 | 浙江大学舟山海洋研究中心 | Control system and method for precise delay and pulse width regulation of phased array ultrasonic emission |
| CN118826706B (en) * | 2024-09-19 | 2025-01-07 | 武汉纺织大学 | Time-to-digital converter based on interpolation difference annular delay chain |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277104A (en) * | 2007-03-26 | 2008-10-01 | 英飞凌科技股份公司 | Improved delay circuit and time-to-digital converter |
| CN101895280A (en) * | 2010-07-30 | 2010-11-24 | 徐和根 | Digital-analog mixed CMOS programmable clock delay controller with extra high accuracy |
| CN202121568U (en) * | 2011-07-11 | 2012-01-18 | 山东欧龙电子科技有限公司 | Time-digital converter |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8502801B2 (en) * | 2008-08-28 | 2013-08-06 | Stmicroelectronics Asia Pacific Pte Ltd. | Capacitive touch sensor system |
| US7893861B2 (en) * | 2009-06-30 | 2011-02-22 | International Business Machines Corporation | Time-to-digital based analog-to-digital converter architecture |
-
2011
- 2011-07-11 CN CN201110192100.5A patent/CN102882527B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101277104A (en) * | 2007-03-26 | 2008-10-01 | 英飞凌科技股份公司 | Improved delay circuit and time-to-digital converter |
| CN101895280A (en) * | 2010-07-30 | 2010-11-24 | 徐和根 | Digital-analog mixed CMOS programmable clock delay controller with extra high accuracy |
| CN202121568U (en) * | 2011-07-11 | 2012-01-18 | 山东欧龙电子科技有限公司 | Time-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102882527A (en) | 2013-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102882527B (en) | Time-to-digital converter and time-to-digital conversion method | |
| CN202121568U (en) | Time-digital converter | |
| CN106019923A (en) | FPGA-based time-to-digital converter | |
| CN101174833B (en) | Method for accurate time measurement and its measuring circuit | |
| CN108170018B (en) | A gated loop time-to-digital converter and time-to-digital conversion method | |
| CN101183244A (en) | Accurate trigger signal generation method and generation circuit | |
| CN109766233B (en) | Detection circuit and method for sensing NBTI effect delay of processor | |
| CN105068405B (en) | Single channel signal pulsewidth high-precision measuring method and device that FPGA is realized | |
| CN106443202B (en) | A kind of on piece is from triggering single event transient pulse method for measuring width and system | |
| CN114397561B (en) | Timing error detection circuit, method and electronic equipment | |
| CN110083492B (en) | Circuit key register triple modular redundancy reinforcing method and device | |
| CN102067456A (en) | Apparatus and method for estimating data relating to a time difference and apparatus and method for calibrating a delay line | |
| CN102736511A (en) | Time measurement system and time measurement method | |
| CN104535918B (en) | A kind of cross clock domain lock unit internal constant test circuit and method | |
| CN102353891B (en) | Digital integrated circuit fundamental tester | |
| CN106227026A (en) | A kind of time-interval counter of pair of delay interpolation method | |
| KR101503732B1 (en) | Time to digital converter | |
| KR950015184B1 (en) | Synchronous binary counter | |
| CN103744094B (en) | Based on the navigational system difference of injection time measurement module of CPLD combination | |
| CN109274376A (en) | A vernier ring type time-to-digital converter capable of compressing maximum conversion time | |
| US9638752B2 (en) | Measurement circuitry and method for measuring a clock node to output node delay of a flip-flop | |
| CN106443420A (en) | Spacecraft information processing unit radiation degradation measuring device and method | |
| CN117116311A (en) | Multichannel trigger readout circuit with time interval measurement function | |
| CN202189123U (en) | FPGA LUT test structure based on SRAM | |
| JP6382057B2 (en) | Delay amount measuring circuit and delay amount measuring method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C53 | Correction of patent of invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Shi Chengjiang Inventor after: Yu Huiqing Inventor after: Zhang Qingguo Inventor after: Li Huijun Inventor after: Xu Yonggui Inventor after: Niu Tingju Inventor after: Li Baohua Inventor after: Tan Lili Inventor before: Shi Chengjiang Inventor before: Yan Jun Inventor before: Zhang Qingguo Inventor before: Li Huijun Inventor before: Xu Yonggui Inventor before: Niu Tingju Inventor before: Li Baohua Inventor before: Tan Lili |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: SHI CHENGJIANG YAN JUN ZHANG QINGGUO LI HUIJUN XU YONGGUI NIU TINGJU LI BAOHUA TAN LILI TO: SHI CHENGJIANG YU HUIQING ZHANG QINGGUO LI HUIJUN XU YONGGUI NIU TINGJU LI BAOHUA TAN LILI |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Time to digital converter and time to digital conversion method Effective date of registration: 20210311 Granted publication date: 20150422 Pledgee: Weifang rural commercial bank Limited by Share Ltd. hi tech sub branch Pledgor: SHANDONG ORION ELECTRONICS Co.,Ltd. Registration number: Y2021980001577 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20220421 Granted publication date: 20150422 Pledgee: Weifang rural commercial bank Limited by Share Ltd. hi tech sub branch Pledgor: SHANDONG ORION ELECTRONICS CO.,LTD. Registration number: Y2021980001577 |