CN110824889B - A Time-to-Digital Converter Based on a Novel Time Amplifier - Google Patents
A Time-to-Digital Converter Based on a Novel Time Amplifier Download PDFInfo
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- CN110824889B CN110824889B CN201911089115.1A CN201911089115A CN110824889B CN 110824889 B CN110824889 B CN 110824889B CN 201911089115 A CN201911089115 A CN 201911089115A CN 110824889 B CN110824889 B CN 110824889B
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- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention provides a time-to-digital converter based on a novel time amplifier, which comprises: the novel time amplifier circuit is used for amplifying the time difference between the rising edge of the asynchronous signal and the rising edge of the synchronous signal; a coarse counter for counting the number of clock cycles between the START and STOP signals after synchronization by the synchronizer; the fine counter is used for counting the time allowance amplified by the novel time allowance amplifying circuit; the calculation module is used for adding the metering result of the coarse counter and the metering result of the fine counter to obtain a final measuring result; and the crystal oscillator is used for providing a clock signal. The invention can achieve the aim of giving consideration to both the amplification precision and the amplification dynamic range of the time amplifier in a limited area, and can achieve higher measurement precision and measurement range under the condition of reducing the required clock frequency.
Description
Technical Field
The invention relates to the field of time-to-digital converters, in particular to a time-to-digital converter based on a novel time amplifier.
Background
The function to be performed by a TDC (time to digital converter) is to quantify with a certain precision the time interval between the rising edges of the two input signals. The TDC has a variety of application scenarios, such as laser radar, all-digital phase-locked loop, face recognition, nuclear reaction imaging, and the like.
The TDC has various structures, such as an analog TDC, a delay line TDC, a ring oscillation TDC, and the like. The analog TDC charges a capacitor by using a constant current source under the control of an input signal, and then samples the voltage of the capacitor by using an ADC (analog to digital converter) so as to obtain the charging time. As shown in fig. 1, the delay line type TDC uses a delay line formed by a buffer chain as a transmission line of a start signal, an output node of each buffer serves as an input of a flip-flop, a stop signal serves as a CLK signal, a rising edge of the stop signal triggers the flip-flop, and a state of the delay line is latched to output a hot code. The time difference to be measured can be obtained by multiplying the single-stage delay of the buffer by the number of '1's in the thermal code. As shown in fig. 2, the ring-oscillation TDC includes a ring oscillator, a counter, and two state latches, where the start state latch records the phase state of the ring oscillator at that time, the counter starts recording the number of oscillation turns of the ring oscillator, and the stop state latch records the phase state of the ring oscillator at that time when the stop signal comes. The time interval between the start signal and the stop signal is known from the value of the counter and the difference between the two phase states. For the latter two TDCs, the measurement accuracy depends on single-stage gate delay, the measurement accuracy of the delay line type TDC is opposite to the measurement range, a larger measurement range requires more stages of inverters, which results in a larger chip layout area, and the power of the ring oscillator in the ring oscillation type TDC is larger.
In addition, a hierarchical TDC is also arranged, the TDC carries out two-stage coarse and fine quantization on the time interval, the coarse quantization can expand the measurement range, and the fine quantization can improve the measurement precision. The traditional hierarchical TDC adopts a time amplifier to amplify time intervals which cannot be quantized by a coarse quantization clock, and then quantizes the time intervals by the clock, and the time is cycled for many times to obtain accurate fine time. As shown in fig. 3, in such a TDC, since the dynamic range of TA (time amplifier) depends on the number of stages of inverters and the accuracy depends on the single-stage delay of the inverters, there is a problem that the dynamic range and the accuracy cannot be compatible with each other. The dynamic range is too small and the time to perform the fine quantization (i.e., the difference between the input signal rising edge and the clock rising edge) cannot be too large, thus requiring a higher clock frequency. The dynamic range is sufficient to cause a large area of TA or a reduction in the amplification accuracy of TA, which leads to a reduction in the quantization accuracy of the entire TDC.
One time amplifier proposed in the literature, as shown in fig. 3, requires a small single-stage inverter delay if high-precision time amplification is to be achieved. Therefore, more inverter stages and larger chip layout area are needed to achieve the same amplification range. If a larger amplification range is to be achieved in a smaller area, a larger single-stage inverter delay is required, which results in a larger single-stage delay of the inverter chain and a lower accuracy of the time amplification.
Disclosure of Invention
The invention aims to: aiming at the problems in the prior art, a time-to-digital converter based on a novel time amplifier is provided.
The invention aims to be realized by the following technical scheme:
a time-to-digital converter based on a novel time amplifier, the converter comprising:
the novel time amplifier circuit is used for amplifying the time difference between the rising edge of the asynchronous signal and the rising edge of the synchronous signal;
a coarse counter for counting the number of clock cycles between the START and STOP signals after synchronization by the synchronizer;
the fine counter is used for counting the time allowance amplified by the novel time amplifier circuit;
the calculation module is used for adding the metering result of the coarse counter and the metering result of the fine counter to obtain a final measuring result;
and the crystal oscillator is used for providing a clock signal.
Furthermore, the novel time amplifier circuit is formed by cascading a coarse time amplifier and a fine time amplifier.
Further, the coarse time amplifier comprises an inverter I1, an inverter I2, an inverter I3, an inverter I4, an inverter I5, an inverter I6, an inverter I11, an inverter I10, an inverter I9, an inverter I8 and an inverter I7 which are cascaded in sequence, an output end of the inverter I7 is connected between the inverter I1 and the inverter I2, an output end of the inverter I8 and the inverter I7 is connected between the inverter I2 and the inverter I3, an output end of the inverter I3 and the inverter I4 is connected between the inverter I9 and the inverter I8, an output end of the inverter I4 and the inverter I5 is connected between the inverter I10 and the inverter I9, an output end of the inverter I9 is connected between the inverter I9 and the inverter I9, two ends of the inverter I9 are connected to a D end of a first D flip-flop through a gate a 9, two ends of the I9 are connected to a second D flip-or a gate 9, two ends of the inverter I4 are connected to the D end of the third D flip-flop after passing through the AND gate A2, the inverter I3 and the inverter I4 are connected with the AND gate A3 through a first transmission gate, the inverter I4 and the inverter I5 are connected with the AND gate A3 through a second transmission gate, and the inverter I5 and the inverter I6 are connected with the AND gate A3 through a third transmission gate.
Further, after the input signal IN is changed into the input signal IN' through the delay of the two stages of inverters, the enable of the coarse time amplifier is turned on.
Further, the fine time amplifier comprises an inverter H, an inverter H and an inverter H which are sequentially cascaded, wherein the output end of the inverter H is connected between the inverter H and the inverter H, and the output end of the inverter H is connected with a NOR gate.
Further, the single stage delay τ 2 of the fine time amplifier is at least 10 times less than the single stage delay τ 1 of the coarse time amplifier.
Further, the input signal IN' is transmitted to the inverter I2, and the falling edge of the input signal IN comes to turn off the inverter I4; the input signal IN' passes to inverter I3, and the falling edge of the input signal IN comes, turning off inverter I5.
Compared with the prior art, the invention uses two stages of time amplifiers, the first stage of time amplifier has large single-stage delay and large amplification range but low precision and is used for carrying out time coarse amplification, and the time margin which cannot be amplified is sent to the second stage of time amplifier by the time margin extraction circuit. The second-stage amplifier has small single-stage delay and small amplification range, but has high precision and is used for amplifying the fine time which cannot be amplified by the first-stage amplifier. Therefore, the invention has the following advantages:
(1) the clock frequency required by the system is reduced, and the power of the system is reduced by changing the phase.
(2) The amplification range and the amplification precision of the time amplifier are considered under a smaller area.
(3) The whole time-to-digital converter can still have a large dynamic range under the condition of high measurement precision.
Drawings
Fig. 1 is a schematic structural diagram of a conventional delay line type TDC;
FIG. 2 is a schematic structural diagram of a conventional ring-oscillation TDC;
FIG. 3 is a schematic diagram of a time amplifier proposed in the literature;
FIG. 4 is a novel time amplifier circuit;
FIG. 5 is a block diagram of a TDC system in the present invention;
FIG. 6 is a schematic diagram of a first stage of the time amplifier of the present invention;
fig. 7 is a schematic diagram of a second stage of the time amplifier of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments.
Examples
The invention provides a time-to-digital converter based on a novel time amplifier, and the circuit of the whole digital converter is shown in figure 5 and comprises a time margin amplifying circuit, a coarse counter, a fine counter, a calculating module and a crystal oscillator. The time margin amplifying circuit amplifies the time difference between the rising edge of the asynchronous signal and the rising edge of the synchronous signal by using a time amplifier, and then counts the time margin by a fine counter. The coarse counter counts the number of clock cycles between the START and STOP signals after synchronization by the synchronizer. And the calculation module adds the metering result of the coarse counter and the metering result of the fine counter to obtain a final measuring result. And the crystal oscillator is used for providing a clock signal.
The invention also provides a novel time amplifier circuit, as shown in fig. 4, 6 and 7, the amplification precision and the dynamic range of the time amplifier are improved in a limited area by adopting a mode of cascading a coarse time amplifier and a fine time amplifier. Therefore, the TDC chip can achieve the measurement performance with high precision and high dynamic range under lower clock frequency.
The coarse time amplifier is shown in fig. 6, and comprises an inverter I1, an inverter I2, an inverter I3, an inverter I4, an inverter I5, an inverter I6, an inverter I11, an inverter I10, an inverter I9, an inverter I8 and an inverter I7 which are cascaded in sequence, wherein the output end of the inverter I7 is connected between the inverter I1 and the inverter I2, the output end of the inverter I8 and the inverter I7 is connected between the inverter I2 and the inverter I3, the output end of the inverter I3 and the inverter I4 is connected between the inverter I9 and the inverter I8, the output end of the inverter I4 and the inverter I5 is connected between the inverter I10 and the inverter I9, the inverter I9 and the inverter I9 are connected between the inverter I9 and the inverter I9, the output end of the inverter I9 is connected between the inverter I9 and the inverter I9, the two ends of the first D flip-flop are connected to the D end of the second D flip-flop through a 9, two ends of the inverter I4 are connected to the D end of the third D flip-flop after passing through the AND gate A2, the inverter I3 and the inverter I4 are connected with the AND gate A3 through a first transmission gate, the inverter I4 and the inverter I5 are connected with the AND gate A3 through a second transmission gate, and the inverter I5 and the inverter I6 are connected with the AND gate A3 through a third transmission gate.
The fine time amplifier comprises an inverter H, an inverter H and an inverter H which are sequentially cascaded, wherein the output end of the inverter H is connected between the inverter H and the inverter H, and the output end of the inverter H is connected with a NOR gate.
When the time amplifier works, the input signal is delayed by the two stages of inverters (IN') and then the enable of the coarse time amplifier is turned on, and then the signal I1 → I2 → I3 is carried out until the falling edge of the IN signal arrives. When the falling edge of the IN signal comes, the D flip-flops at the output terminals of A1, O1 and A2 are triggered. The D flip-flop will only output a1 if the signals at both ends of the inverter are the same. Assuming that the falling edge of IN arrives when both ends of I2 are 1, indicating that the IN' signal is passing to I2, it can be seen that the signal will stop when it passes to I4 and there will be no output from I4. Thus part of the time that is propagated inside I4 is lost. Therefore, I4 is turned off in advance, and the signal at the input end of I3 is transmitted to the second stage fine time amplifier for amplification. When the falling edge of IN comes, the D flip-flop at the output end of A1 is set to 1, I4 is closed, and the first transmission gate is opened. I3 outputs a ToSTA signal after passing through the transmission gate and the IN' phase, which is the control signal of the fine time amplifier. Similarly, if the falling edge of IN arrives when the IN 'signal passes to I3, I5 is turned off, and the output signal of I4 is summed with the IN' signal before outputting the control signal of the fine time amplifier.
The single-stage delay tau 2 of the fine time amplifier is much smaller than the single-stage delay tau 1 of the coarse time amplifier: for example at least 10 times. Since the time input into the fine time amplifier is the time margin that the coarse time amplifier cannot amplify, it is known that this time is less than τ 1, so the number of stages of the fine time amplifier depends on the single-stage delay τ 1 of the coarse time amplifier.
After the fine time amplifier amplifies the time margin, the output signal and the NOR signal of the IN signal are used as the enabling signal of the inverter chain returned by the coarse time amplifier. Finally, a pulse signal with twice input pulse width is output at the output end of the coarse time amplifier.
The two-stage time amplifier is used, the first stage amplifier has large single-stage delay and large amplification range but low precision and is used for carrying out time coarse amplification, and the time margin which cannot be amplified is sent to the second stage time amplifier through the time margin extraction circuit. The second-stage amplifier has small single-stage delay and small amplification range, but has high precision and is used for amplifying the fine time which cannot be amplified by the first-stage amplifier. Therefore, the purpose of giving consideration to both the amplification precision and the amplification dynamic range of the time amplifier can be achieved in a limited area. Higher measurement accuracy and measurement range can be achieved with a reduced required clock frequency.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, it should be noted that any modifications, equivalents and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A time-to-digital converter based on a novel time amplifier, the converter comprising:
the novel time amplifier circuit is used for amplifying the time difference between the rising edge of the asynchronous signal and the rising edge of the synchronous signal; the novel time amplifier circuit is formed by cascading a coarse time amplifier and a fine time amplifier; the coarse time amplifier comprises an inverter I, an inverter I and an inverter I which are sequentially cascaded, wherein the output end of the inverter I is connected between the inverter I and the inverter I, the inverter I and the inverter I are connected between the inverter I and the inverter I, the output end of the inverter I is connected between the inverter I and the inverter I, two ends of the inverter I are connected to the D end of a first D trigger after passing through an AND gate A, two ends of the inverter I are connected to the D end of a second D trigger after passing through an NOR gate O, two ends of the inverter I4 are connected to the D end of the third D flip-flop after passing through an AND gate A2, the inverter I3 and the inverter I4 are connected with the AND gate A3 through a first transmission gate, the inverter I4 and the inverter I5 are connected with the AND gate A3 through a second transmission gate, and the inverter I5 and the inverter I6 are connected with the AND gate A3 through a third transmission gate; the fine time amplifier comprises an inverter H, an output end of the inverter H, a space between the inverter H and the inverter H, an output end of the inverter H connected between the inverter H and the inverter H, and an output end of the inverter H connected with a NOR gate;
a coarse counter for counting the number of clock cycles between the START and STOP signals after synchronization by the synchronizer;
the fine counter is used for counting the time allowance amplified by the novel time amplifier circuit;
the calculation module is used for adding the metering result of the coarse counter and the metering result of the fine counter to obtain a final measuring result;
and the crystal oscillator is used for providing a clock signal.
2. The time-to-digital converter based on the novel time amplifier as claimed IN claim 1, wherein the enable of the coarse time amplifier is turned on after the input signal IN is changed into the input signal IN' through the delay of the two-stage inverter.
3. A time-to-digital converter based on a novel time amplifier according to claim 1, characterized in that the single-stage delay τ 2 of the fine time amplifier is at least 10 times smaller than the single-stage delay τ 1 of the coarse time amplifier.
4. The time-to-digital converter based on the novel time amplifier as claimed IN claim 2, wherein the input signal IN' is transmitted to the inverter I2, the falling edge of the input signal IN comes, and the inverter I4 is turned off; the input signal IN' passes to inverter I3, and the falling edge of the input signal IN comes, turning off inverter I5.
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| CN114675525B (en) * | 2021-09-30 | 2022-09-02 | 绍兴圆方半导体有限公司 | Time-to-digital converter and clock synchronization system |
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Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: Xi'an Tuoer Microelectronics Co.,Ltd. Address after: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee after: Xi'an Tuoer Microelectronics Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Patentee before: XI'AN TUOER MICROELECTRONICS Co.,Ltd. |
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