CN105068405B - Single channel signal pulsewidth high-precision measuring method and device that FPGA is realized - Google Patents

Abstract

The invention discloses the single channel signal pulsewidth high-precision measuring method and device that a kind of FPGA is realized, pass through at least one carry line resource composition delay chain in FPGA, each carry line resource has multiple taps, status information of the rising edge of part tap output measurement signal on the delay chain, part tap output is status information of the trailing edge of measurement signal on the delay chain；Select the status information of the rising edge and the status information of trailing edge respectively using MUX, be allowed to input decoding unit respectively and enter row decoding.The present invention has the advantages that measurement accuracy is high, the utilization of resources is few, highly versatile.

Description

Single-channel signal pulse width high-precision measurement method and device realized by FPGA

technical field

The invention belongs to the technical fields of data acquisition, high-precision time measurement, etc., and specifically relates to a single-channel signal pulse width high-precision measurement method and device realized by FPGA, which can be applied to particle physics experiments, nuclear physics experiments, and the like.

Background technique

Time measurement is widely used in scientific research, industrial applications, communications, military and other fields. For example, the lifetime of an excited state of an atom is represented by the time interval between two consecutive signals; the energy of a neutron is represented by the flight time required for a neutron to fly a certain distance Time; the spatial position of the incident particle can be expressed as the time information of the output signal of the position sensitive detector; the time and position of the incident particle are often processed by the time of the signal; in addition, there are communication, timing, military and other fields that require accurate time measurement methods and techniques.

The basic principle of time interval measurement is to use a pulse signal called "start" as the reference point for time measurement, and then measure the time difference between the next pulse signal called "stop" and the "start" signal. The technology that can accurately determine the incident time of particles is called timing (such as leading edge timing, zero-crossing timing, constant ratio timing, etc.), using this technology can accurately determine the physical moment when the signal appears, thus making accurate time measurement possible. Generally speaking, using cutting-edge timing technology, we can quickly and accurately locate the moment of the pulse signal, and the time difference between the "start" and "stop" signals is the pulse interval. However, in many occasions, we need to measure the pulse width of the signal. For example, in order to correct the influence of the "time walk" effect on the leading edge timing, the measurement result can be compensated according to the charge of the signal, and the signal's The amount of charge is proportional to the width of the signal pulse (the time interval between the leading edge and the trailing edge), so it is necessary to measure the pulse width, and when the pulse width becomes narrower, the measurement difficulty will increase sharply. In addition, in fields such as laser ranging, measurement, and instrumentation, there is a wide demand for accurate measurement of signal pulse width.

There are many techniques for time measurement (TDC), such as vernier caliper method, two-stage delay chain, clock phase separation method, time interpolation method, etc., which can be realized by using ASIC or FPGA in specific implementation. Usually, when performing time measurement, a time 0 point is set, and the interval between the leading edge of the measured signal and the time zero point is the time measurement value. The object of traditional time interval measurement is the time difference between two signals to be measured, so it is only necessary to measure the relative time difference between the leading edges of the two signals to be measured. When it is necessary to measure the pulse width of a single signal, especially a narrow pulse signal, in addition to the leading edge of the signal, it is also necessary to measure the time value of the trailing edge of the signal, and the difference between the two represents the pulse width value. Therefore, frontier measurement is the basis of time measurement. For the trailing edge, the simplest and most direct method is to reversely process the signal to be measured through an inverter, then the trailing edge of the signal will be transformed into a leading edge, which can be obtained by using the same technology and circuit as the leading edge measurement. trailing edge information. However, this method needs twice the resource consumption to obtain the signal pulse width information. In applications where only the leading edge of the signal is measured, the other half of the electronics channel for trailing edge measurements is completely wasted. In situations where the number of time measurement channels is high, this obviously reduces the integration level of time measurement and increases the implementation cost.

Contents of the invention

The present invention aims at proposing a new method to realize the simultaneous measurement of the leading and trailing edges of the signal on only one electronic channel, that is, a method for high-precision measurement of the pulse width of the single-channel signal on the FPGA.

In order to solve the above technical problems, the present invention proposes a high-precision measurement method and device for signal pulse width realized by FPGA. The method of the present invention comprises the steps of: forming a delay chain through at least one carry connection resource in the FPGA, each carry connection resource has a plurality of taps, and some taps output the state information of the rising edge of the measurement signal on the delay chain, Part of the tap output is the state information of the falling edge of the measurement signal on the delay chain; use a multiplexer to select the state information of the rising edge and the state information of the falling edge respectively, so that they are respectively input to the decoding unit for decoding .

According to a specific embodiment of the present invention, before the multiplexer selects the state information of the rising edge and the state information of the falling edge, it identifies the state information from the delay chain to determine that it is the state information of the rising edge It is also the status information of the falling edge.

According to a specific embodiment of the present invention, the FPGA is a Xilinx FPGA, and the carry connection resource is CARRY4, and each CARRY4 has three taps to output CO0, O2 and CO3, wherein the output of CO0 and CO3 is the state of rising edge on the delay chain Information; the output of O2 is the state information of the falling edge on the delay chain.

According to a specific implementation manner of the present invention, the multiplexer is a 2:1 multiplexer.

The present invention also proposes a single-channel signal pulse width high-precision measurement device implemented by FPGA, including a coarse counting unit, a fine time measurement unit and a decoding unit, and the fine time measurement unit includes a delay chain, a D flip-flop and a multiplexer A device, wherein the delay chain has a plurality of taps, some of the taps output the state information of the rising edge of the measurement signal on the delay chain, and some of the taps output the state information of the falling edge of the measurement signal on the delay chain; The D flip-flop is used to latch the status information; the multiplexer selects the status information of the rising edge and the status information of the falling edge respectively, so that they are respectively input into the decoding unit.

According to a specific embodiment of the present invention, the fine time measurement unit further includes a detection circuit connected to the selection control terminal of the multiplexer for identifying the state information of the rising edge and the state information of the falling edge, to control the output of the multiplexer.

According to a specific embodiment of the present invention, the detection circuit includes an inverter, a D flip-flop and a two-input AND gate, wherein one input end of the AND gate is connected to the output end of the D flip-flop, and the other end connected to an input signal; one input end of the D flip-flop is connected to the output end of the inverter, and the other input end is connected to a clock signal; the input end of the inverter is the input signal.

The invention has the advantages of simple structure, low cost, high precision, etc., and can simultaneously realize high-precision measurement of the leading and trailing edge times of a signal on a single electronic channel, so as to obtain the signal pulse width. Its advantages include:

1. It makes it possible to measure signal pulse width on a single channel, which greatly improves the number of channels and integration of system time measurement.

2. The automatic identification and measurement of the leading and trailing edges of the signal can be realized, which greatly reduces the complexity and cost of the application and realization of the method.

3. The present invention is implemented based on FPGA, has universality and ease of use, can be applied to various application fields of high-precision measurement of signal pulse width, and can be better integrated with data readout, and has a wide range of application prospects .

Description of drawings

Figure 1 is a specific structure diagram of the bottom layer of Slice resources in Xilinx FPGA;

Fig. 2 is a schematic diagram of the signal front and rear edge measurement of the present invention;

Fig. 3 is the implementation schematic diagram of single channel bottom layer delay chain of the present invention;

Fig. 4 is the single-channel pulse width measurement structure diagram based on "thickness" structure TDC of the present invention;

Fig. 5 is a signal edge change detection circuit of the present invention.

detailed description

The invention proposes a method for measuring the pulse width of a single-channel high-precision signal in an FPGA, and its basic idea is to simultaneously measure the time of the leading edge and the trailing edge of the signal on a single electronic channel. In modern FPGA-based time measurement technology, in order to improve the accuracy, time interpolation method is often used. Due to the characteristics of FPGA internal resources, the carry chain at the bottom of the chip is used as the basic unit of the interpolation delay chain. Therefore, in order to perform high-precision measurement of signal pulse width on a single channel, the first thing to solve is the construction method of the delay chain.

Figure 1 shows the internal specific structure of Slice resources in Xilinx Virtex-5 and later series FPGAs. The dotted line box is the CARRY4 primitive module including the carry chain. It is divided into 4 bits (CO0~CO3, O0~O3), each bit contains a multiplexer (MUX) and an exclusive OR gate (XOR), the output of MUX corresponds to the CO terminal, and the output of XOR corresponds to O terminal; it has 9 ports in total, which are Cout, CO0~CO3, and O0~O3. There is a D flip-flop corresponding to the CO and O output terminals, which can be used to latch the data output by CO or O, but at the same time Only one input (CO or O) can be latched by a D flip-flop, which can be selected by a multiplexer; and Cout can be input to the Cin terminal of CARRY4 in the next adjacent Slice unit in the same column, thus forming a delay chain.

Figure 2 shows the principle of measuring the front and back edges of the signal. When the rising edge of the signal arrives, each CO output jumps from '0' to '1'; and in order to form a delay connection, the selection port of the MUX must be set to ' 1', turn on the Cin channel, so that one fixed input of the XOR gate is '1', and the other input terminal is connected to Cin. When the falling edge of the signal arrives, each O output terminal will also jump from '0' to '1'. Based on this, the CO output can be used to detect the rising edge of the signal and measure its time, and the O output can be used to detect the falling edge of the signal and measure the time of the trailing edge. And because the state transitions of the delay chains of the front and back edges are consistent, the decoding part of the two can be shared, so that one TDC channel can be used to realize the time measurement of the front edge and the time of the back edge.

In order to ensure the measurement accuracy of the rising edge time, the carry line resources in CARRY4 are still divided into two parts on average to form delay units with smaller delay times, that is, use Cin to CO0 as a delay unit, and use CO0 to CO3 as a delay unit. The delay unit constitutes the delay chain required for the "fine" measurement of the rising edge time; since the remaining two bits (O1 and O2) cannot divide CARRY4 into two halves, Cin to O2 is used as a delay unit, and O2 to O2 The O2 of the next adjacent Slice acts as a delay unit, thus forming the delay chain required for the "fine" measurement of the falling edge time. In this way, the delay unit of the trailing edge uses the entire CARRY4 as a delay unit, and the delay time of each delay unit is twice the delay time of the rising edge delay unit, and the time measurement accuracy will be slightly worse than that of the rising edge time measurement. Fig. 3 is an implementation structure diagram of a single-channel bottom layer delay chain.

According to the basic method proposed in the patent of the present invention, it is easy to improve the delay chain based on the time interpolation technology TDC, so that it can meet the high-precision measurement capability of single-channel signal pulse width. Figure 4 is a single-channel pulse width measurement structure based on the "thick and thin" structure TDC, which is mainly composed of a coarse counting unit, a fine time measuring unit and a decoding unit. The circuit realization of each part is introduced in detail below. The coarse counting unit is composed of a high-frequency (250MHz) binary counter to ensure a large dynamic range of time measurement, and the front and rear edges are shared to ensure that the starting point of time measurement is consistent; the fine time measurement unit is composed of delay chains and D flip-flops Time interpolation is implemented to ensure precise measurement of time.

The delay chain is composed of carry connection resources CARRY4 in Xilinx FPGA, as shown in Figure 3. Each CARRY4 has three tap outputs (CO0, O2 and CO3) and sent to the D flip-flop for latching, where the output of CO0 and CO3 is the state information on the rising edge in the delay chain; the output of O2 is the falling edge in the delay chain status information on . These two kinds of state information are sent to the subsequent decoding unit for decoding, and the "fine" time data of each edge are obtained. Since the decoding unit can only process one state code at a time, the two need to be selected by a 2:1 selector to determine which state information code should be sent to the decoding unit.

In order to be able to accurately select the state information code of the rising edge or falling edge, so as to send it to the decoding unit for decoding, it is necessary to add a detection circuit that can identify the rising edge and falling edge in the circuit, such as the LD in Figure 4 (Rising edge detection) and TD (falling edge detection) unit, its specific structure and timing are shown in Figure 5, the detection circuit is mainly composed of an inverter, a D flip-flop and a two-input AND gate. One input end of the AND gate is connected to the output end of the D flip-flop, the other end is connected to the input signal, one input end of the D flip-flop is connected to the output end of the inverter, and the other input end is connected to the clock signal, and the inverting tor input for the input signal. When the input signal changes from low to high, the detection circuit will generate a pulse signal with a width of one clock cycle. However, when the signal to be measured is sent into the delay chain, the output of the first D flip-flop in the rising edge and falling edge will produce a transition from low to high, so that both detection units will output a pulse signal, Moreover, the time when both output pulse signals is related to the time relationship before and after the rising edge and falling edge of the input signal to be tested. In this way, the two detection output signals can be used as the selection control terminals of the 2:1 multiplexer to accurately control the output signal of the selector. At the same time, another same 2:1 multiplexer circuit is used to select two detection enable signals, and after a delay of a D flip-flop, a latch signal is obtained for latching the corresponding decoding result , and then store it in the FIFO.

The application of the present invention utilizes the FPGA of Xilinx series to realize the high-precision measurement of signal pulse width on a single channel, and has the following advantages:

(1) High measurement accuracy

The method proposed in the patent of the present invention is based on the time interpolation technology, while using the carry chain of the Slice resource inside the Xilinx FPGA to form a "fine" time measurement, the signal is realized through MUX (multiplexer) and XOR (exclusive OR gate) respectively. The measurement of the rising edge and the falling edge has high measurement accuracy. The measurement accuracy of the rising edge is about 14ps, and the measurement accuracy of the pulse width is better than 60ps (the pulse width range is 7-100ns).

(2) Less resource utilization

The second significant advantage of the method proposed in the patent of the present invention is that the resource utilization rate is low, and the time measurement of the leading and trailing edges of the signal can be truly realized on a single electronic channel, that is, pulse width measurement, and has extremely high measurement accuracy, which is The practical application integration degree of the method is greatly improved, and the application cost is reduced.

(3) Strong versatility

The third advantage of the method proposed in the patent of the present invention is its strong versatility. The method is to improve the delay chain required by the conventional time interpolation technology, so that it can support the time measurement of the trailing edge of the signal. Therefore, the method is applicable to all time measurement applications using delay chain time interpolation technology, and can be easily integrated with logic resources of other parts of the system, and has strong versatility.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (9)

1. A single-channel signal pulse width high-precision measurement method implemented by FPGA, comprising the steps: A delay chain is formed by at least one carry connection resource in the FPGA. Each carry connection resource has multiple taps. Some taps output the state information of the rising edge of the measurement signal on the delay chain, and some taps output the falling edge of the measurement signal. state information along said delay chain; Use the carry connection resource CARRY4 to output the rising edge of the signal to be tested through multiplexer delay compensation, and turn the falling edge of the signal to be tested into a rising edge output through the XOR gate, and then connect the two to the D flip-flop group for rising Capture and latch of edge state; Use the detection circuit to control the multiplexer, respectively select the state information of the rising edge and the state information of the falling edge, so that they are respectively input into the decoding unit for decoding, wherein the detection circuit is used to identify the state information of the rising edge status information and status information on the falling edge. 2. single-channel signal pulse width high-precision measuring method as claimed in claim 1, is characterized in that, before described multiplexer selects the state information of described rising edge and the state information of falling edge, to trigger from D Identify the state information latched by the device group to determine whether it is the state information of the rising edge or the state information of the falling edge. 3. single-channel signal pulse width high-precision measuring method as claimed in claim 1, is characterized in that, described FPGA is Xilinx FPGA, and carry connection resource is CARRY4, and each CARRY4 has three taps to output CO0, O2 and CO3, Among them, the output of CO0 and CO3 is the state information of the rising edge on the delay chain; the output of O2 is the state information of the falling edge of the delay chain; both are output to the D flip-flop group latch in the form of signal rising edge. 4. The method for measuring the pulse width of a single-channel signal with high precision according to any one of claims 1 to 3, wherein the multiplexer is a 2:1 multiplexer. 5. A single-channel signal pulse width high-precision measuring device realized by an FPGA, comprising a coarse counting unit, a fine time measuring unit and a decoding unit, and the fine time measuring unit includes a delay chain, a D flip-flop group and a multiplexer ,in, The delay chain has a plurality of taps, some taps output the state information of the rising edge of the measurement signal on the delay chain, and some taps output the state information of the falling edge of the measurement signal on the delay chain, using the carry connection Resource CARRY4, the rising edge of the signal to be tested is output through the delay compensation of the multiplexer, and the falling edge of the signal to be tested is turned into a rising edge output through the XOR gate, and the two are connected to the D flip-flop group to capture the state of the rising edge and latches; The D flip-flop group is used to latch the state information; The multiplexer selects the state information of the rising edge and the state information of the falling edge respectively, so that they are respectively input to the decoding unit. 6. the single-channel signal pulse width high-precision measurement device that FPGA as claimed in claim 5 realizes, is characterized in that, described fine time measurement unit also comprises detection circuit, and it is connected to the selection control end of described multiplexer , used to identify the state information of the rising edge and the state information of the falling edge, so as to control the output of the multiplexer. 7. the single-channel signal pulse width high-precision measuring device that FPGA as claimed in claim 6 realizes, is characterized in that, described detection circuit comprises an inverter, a D flip-flop and a two-input AND gate, wherein, One input end of the AND gate is connected to the output end of the D flip-flop, and the other end is connected to the input signal; One input end of the D flip-flop is connected to the output end of the inverter, and the other input end is connected to a clock signal; The input terminal of the inverter is the input signal. 8. The single-channel signal pulse width high-precision measuring device according to any one of claims 5 to 7, wherein said FPGA is a Xilinx FPGA, and the carry connection resource is CARRY4, and each CARRY4 has three tap outputs CO0, O2 and CO3, where the output of CO0 and CO3 is the state information of the rising edge on the delay chain; the output of O2 is the state information of the falling edge on the delay chain. 9. The single-channel signal pulse width high-precision measuring device realized by FPGA as claimed in claim 8, wherein said multiplexer is a 2: 1 multiplexer.