CN104502684B - A kind of totally digitilized peak value due in discrimination method - Google Patents

Abstract

The present invention relates to a method for discriminating the time of arrival of a fully digitalized peak value, comprising the following steps: using a high-speed comparator equal in number to the signal to be tested, and comparing with a certain preset threshold signal, when the signal is greater than the preset threshold, the output is "1", otherwise output "0", the signal to be tested is converted into a digital pulse signal; the signal to be tested is one or more analog pulse signals with a certain symmetry with rising and falling edges; measured by FPGA chip After the rising edge time and falling edge time of the digital pulse signal; according to the rising edge time and falling edge time, calculate the peak arrival time of the signal to be measured. This method has a simple hardware circuit, is easy to implement, and is easy to expand multi-channels. At the same time, compared with the existing technologies such as constant ratio timing and peak detection, the hardware circuit is greatly simplified, and the timing accuracy is similar. It has stronger advantages in the field of multi-channel signal processing. practicality and feasibility.

Description

An all-digital peak arrival time identification method

technical field

The invention relates to the field of identification of the arrival time of pulse signals, in particular to a method for identifying the arrival time of an all-digital peak value.

Background technique

In the fields of laser ranging and high-energy physics, applications such as high-resolution ranging and particle discrimination require accurate measurement of the arrival time of pulse signals. At present, the common arrival time discrimination methods include edge detection, peak detection, constant ratio timing detection and so on. The edge detection method is easy to implement and low in cost, but it is greatly affected by the signal echo strength. With the change of the signal amplitude, the arrival time will wander in a large range, and the range of change is approximately proportional to the width of the rising edge of the pulse signal. . Peak detection obtains high-resolution signal waveforms through high-speed sampling, and determines the peak position through subsequent processing. It requires high-speed hardware sampling circuits, which are costly and consume high power. The constant-ratio timing detection determines the arrival time by detecting the ratio of the signal amplitude to the peak amplitude, which can greatly reduce the random walk caused by the change of the echo signal strength, but its circuit implementation is complicated, and hardware circuits such as delay and proportional sampling are required. Due to the increase in the complexity of hardware circuits, the cost of multi-channel signal processing has increased significantly, and factors such as system size and power consumption are also difficult to control within a reasonable range. It is not suitable for the current multi-channel parallel signal processing environment that is increasing day by day.

Contents of the invention

In order to solve the problems of insufficient detection accuracy or complex circuit structure and difficult expansion in the prior art, the present invention provides an all-digital peak arrival time identification method.

In order to solve the problems of the technologies described above, the technical solution of the present invention is specifically as follows:

A fully digital peak arrival time identification method, comprising the following steps:

Using a high-speed comparator equal to the number of signals to be tested, by comparing with a preset threshold signal, when the signal is greater than the preset threshold, the output is "1", otherwise the output is "0", and the signal to be tested is converted into a digital Pulse signal; the signal to be tested is one or more analog pulse signals with certain symmetry and rising and falling edges;

Use the FPGA chip to measure the rising edge time and falling edge time of the digital pulse signal;

Calculate the peak arrival time of the signal to be measured according to the rising edge time and falling edge time.

In the above technical solution, the FPGA chip has more input interfaces than the number of signals to be tested.

In the above technical solution, the measurement of the rising edge time and the falling edge time of the pulse signal based on the tapped delay line are adopted.

In the above technical solution, the FPGA chip can be reprogrammed to expand the number of signals to be tested.

In the above technical solution, after calculating the peak arrival time of the signal to be measured, it communicates with the subsequent processing unit through a digital protocol to output a high-resolution, low-wander value pulse peak arrival time value.

In the above technical solution, the specific steps of measuring the rising edge moment and falling edge moment of the digital pulse signal with the FPGA chip include:

For each digital pulse signal, when the signal amplitude is from less than the threshold to greater than the threshold, the rising edge moment of the signal is obtained; when the signal amplitude is from greater than the threshold to less than the threshold, the falling edge moment of the signal is obtained.

In the above technical solution, after obtaining the rising edge time and falling edge time, the peak arrival time is calculated according to the following formula:

Among them, t ₊ is the rising edge time, t _- is the falling edge time, η is the proportional coefficient of the falling edge to the rising edge, and t _peak is the peak arrival time.

The present invention has following beneficial effect:

The hardware circuit structure of this technical solution is simple, and it adopts all-digital processing, which is beneficial to the expansion of the measurement channel, and can greatly reduce the random walk at the arrival time of the signal caused by the change of the signal amplitude, and has great advantages in the field of multi-channel high-precision signal timing application potential.

Description of drawings

Figure 1 is a schematic diagram of the hardware system composition of the all-digital peak arrival time identification.

Fig. 2 is a schematic diagram of the principle of fully digitalized peak arrival time measurement.

Fig. 3 is a schematic diagram of the timing and edge detection principle of the tapped delay line.

Figure 4 is a schematic diagram of the structure of the FPGA timing and edge detection system.

Fig. 5 is a schematic structural diagram of a multi-channel all-digital peak arrival time identification system.

detailed description

Invention idea of the present invention is:

Using all-digital technology, by measuring the arrival time of the rising edge and falling edge of the signal, and according to the symmetry characteristics of the pulse signal itself, the peak arrival time is calculated, and the accurate identification of the peak arrival time of the pulse signal with a certain symmetry is realized. It can be used in the fields of laser or radar signal ranging, detection of arrival time of high-energy physical particles, etc., to overcome the random walk of arrival time caused by signal strength, and realize high-precision detection of pulse signal arrival time

Aiming at signals with certain symmetry on the rising edge and falling edge, the present invention uses a high-speed comparator and FPGA to realize a scalable single-channel or multi-channel pulse signal peak arrival time identification system, including:

A high-speed comparator corresponding to the number of signal channels to be tested is used to convert the analog pulse signal to be tested into a digital pulse signal;

An FPGA processing chip with a number of inputs corresponding to the number of signal channels to be tested, the chip includes:

A high-resolution time-to-digital converter corresponding to the number of signal channels to be tested is used to record the moment when the digital pulse signal level changes and the signal transition direction, and determine the rising edge moment and falling edge moment of the signal;

The peak time identification method combines the rising edge time and falling edge time to calculate the peak arrival time of the signal;

The data communication module is used to communicate the measured peak value with the subsequent processing system through a certain protocol.

The present invention will be described in detail below in conjunction with the accompanying drawings.

The hardware composition of the single-channel signal measurement system is shown in Figure 1.

The signal to be tested is a voltage or current signal, and the voltage/current of the signal changes with time, which can be expressed as V=Af(t) or I=Af(t) where A is the peak amplitude and f(t) is the normalized waveform . The signal to be tested has a certain symmetry with respect to the peak time, and the peak time is taken as t _peak , which should be:

f(t _peak -δ)=f(t _peak +ηδ) (1)

Among them, δ is the time away from the peak moment, η is the proportional coefficient of the falling edge to the rising edge, and for the symmetrical signal before and after, η=1.

By comparing the input signal with a threshold, the analog signal is converted into a digital pulse signal. When the input signal is greater than the threshold, the digital signal is "1", otherwise it is "0". The FPGA has high-resolution time-to-digital conversion circuits inside, and its time is gradually increased over time. FPGA monitors this digital signal, and when its state changes, it records the time when it occurs. For each pulse signal, when the signal amplitude is from less than the threshold to greater than the threshold, the signal rising edge time t ₊ can be obtained; when the signal amplitude is from greater than the threshold to less than the threshold, the signal falling edge time t _- can be obtained. After obtaining the rising edge time and falling edge time, calculate the peak arrival time according to the following formula:

Its measurement principle is shown in Figure 2.

The picture shows the front and rear symmetry, that is, the signal to be measured with η=1. In the figure, a and b are two signals to be measured with the same arrival time but with different signal strengths, and the signal amplitude a>b. A _th is the signal threshold. t _a and t _b are digitized signals of a signal and b signal respectively. t _a+ and t _a- correspond to the rising edge time and falling edge time of signal a respectively. t _b+ and t _b - correspond to the rising edge time and falling edge time of b signal respectively. t _ca /t _cb correspond to the peak arrival time of signal a and signal b respectively after digitization. For the single-threshold detection circuit, due to the change of the signal peak intensity, the two signals with the same peak arrival time, the leading edge arrival time of the threshold are t _a+ and t _b+ respectively, which has a large time discrimination error. However, after using the peak arrival time identification method, the time identification error caused by the peak intensity change will be greatly reduced.

For each signal threshold A _th smaller than the peak value of the echo signal, there are two moments, corresponding to the rising edge and the falling edge of the pulse signal respectively.

Since the signal has proportional symmetry with respect to the peak time, it can be obtained from formula (1)

f(t _peak -δ ₊ )＝f(t _peak +ηδ ₊ ) (4)

Therefore available

δ _- ＝ηδ ₊ (5)

Combining Equation (4) and Equation (5), Equation (2) can be obtained. The arrival time obtained at this time has nothing to do with the peak amplitude of the echo signal, thus improving the measurement accuracy of the signal arrival time and reducing the influence caused by the change of the peak amplitude of the signal. Arrival time random walk.

The rising edge time detection and falling edge time detection of the signal are realized by FPGA, and the high-resolution time-to-digital conversion (Time to Digital Convertor-TDC) of the signal is realized by using a tapped delay line. The implementation principle is shown in Figure 3.

The signal is the input signal, and the element marked τ is the delay unit. The input signal is delayed by multiple stages. When the signal propagates between the delay units at all levels, the input of the Q1-Q8 registers changes sequentially with time. After the signal changes from "0" to "1", after time τ, the Q1 input first becomes "0", after 2τ, the Q2 input becomes "0", and so on. When the register clock comes, the registers save their respective input states, and the total time that the signal passes before the clock time can be determined by the number of "1" in it. When Q1 is "1", the signal is a rising edge, and when Q1 is "0", the signal is a falling edge. After recording the time signal, use formula (2) to calculate the peak arrival time.

In order to realize the high precision and long time range of timing at the same time, it can be realized by the common timing method of tapped delay line composed of coarse clock counting and high precision delay unit. FPGA internal timing and edge detection system structure shown in Figure 4.

The delay of a single delay unit of the tapped delay line is τ, the number of delay units is M, and the clock period is T. It is required that M×τ≥T to ensure that the signal cannot completely pass through the tapped delay line within the clock interval. The encoder monitors the output of the tapped delay line. When the output is not all "0" or all "1", the output result of the tapped delay line and the current value of the counter are recorded, and the encoder inputs the result into the memory for storage.

The processor reads the time stamp stored in the memory. If the m registers before the delay line are "1" and the M-m registers after the delay are "0", the calculation method for the rising edge and rising edge of the corresponding signal is:

t=n×T-m×τ (6)

If the value of the first m registers of the delay line is "0" and the value of the last M-m registers is "1", the calculation method of the falling edge time is the same as that of the rising edge from the falling edge of the corresponding signal.

After obtaining the rising edge time and falling edge time of the signal, the processor calculates the peak arrival time according to formula (2), and finally outputs the calculation result to the subsequent processing unit.

When multiple signals need to be measured in parallel, in order to further improve the scalability and flexibility of the system, the structure shown in Figure 5 is adopted.

A, B, and N are high-speed comparators corresponding to signals A, B, and N to be tested, respectively. For different signals to be tested, an independent threshold or the same threshold can be used. After the output digital signal of the comparator is connected to the FPGA, the rising edge time measurement and the falling edge time measurement are performed, and the peak arrival time is calculated, and then through the output interface, according to the application requirements, select The corresponding communication protocol is output for subsequent processing.

Apparently, the above-mentioned embodiments are only examples for clear description, rather than limiting the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. And the obvious changes or changes derived therefrom are still within the scope of protection of the present invention.

Claims (5)

1. a kind of totally digitilized peak value due in discrimination method, it is characterised in that comprise the following steps：

Using with the equal numbers of high-speed comparator of measured signal, by being compared with a certain predetermined threshold value signal, work as signal During more than predetermined threshold value, it is output as " 1 ", on the contrary output " 0 ", measured signal is changed into digital pulse signal；The letter to be measured Number for all the way or multichannel has the analog pulse signal with rising edge and trailing edge of certain symmetry；

Rising edge time and the trailing edge moment by digital pulse signal are measured with fpga chip；According to rising edge time with Drop calculates the peak value due in of measured signal along the moment；It is comprised the following steps that：

For each digital pulse signal, signal amplitude less than threshold value by, to more than threshold value, obtaining signal rising edge time；Signal When amplitude is by more than threshold value to less than threshold value, the signal trailing edge moment is obtained；Obtain after rising edge time and trailing edge moment, root Peak value due in is calculated according to following formula：

$t_{peak}=\frac{{\mathrm{\ηt}}_{+}+t_{-}}{1+\mathrm{\η}}$

Wherein, t₊For rising edge time, t_-For the trailing edge moment, η is trailing edge to the proportionality coefficient of rising edge, t_peakFor peak value Due in.

2. totally digitilized peak value due in discrimination method according to claim 1, it is characterised in that the fpga chip Input interface with higher than measured signal number.

3. totally digitilized peak value due in discrimination method according to claim 1, it is characterised in that using based on tap The measurement of pulse signal rising edge time and the measurement of trailing edge moment of delay line.

4. totally digitilized peak value due in discrimination method according to claim 1, it is characterised in that the fpga chip Extension measured signal number can be reprogramed.

5. totally digitilized peak value due in discrimination method according to claim 1, it is characterised in that calculate measured signal Peak value due in after, pass through digital protocol and subsequent processing units and communicate, output high-resolution, the pulse peak of low migration value It is worth due in value.