CN102833939A - Capacitor performance optimization method and circuit board designed by applying same - Google Patents
Capacitor performance optimization method and circuit board designed by applying same Download PDFInfo
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- CN102833939A CN102833939A CN2011101572837A CN201110157283A CN102833939A CN 102833939 A CN102833939 A CN 102833939A CN 2011101572837 A CN2011101572837 A CN 2011101572837A CN 201110157283 A CN201110157283 A CN 201110157283A CN 102833939 A CN102833939 A CN 102833939A
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Abstract
The invention provides a capacitor performance optimization method and a circuit board designed by applying the same. The capacitor performance optimization method comprises the following steps: providing a circuit board, wherein a capacitor welding pad group is arranged on the circuit board; and arranging a plurality of through holes in one side of a bonding pad (close to the current inflow direction) of the capacitor bonding pad group, wherein the circle centers of the through holes are located in a same semi-circular arc, and the circle center of the semi-circular arc is the center of the bonding pad. The circuit board designed by using the method can be used for effectively optimizing the filtering performance of a capacitor, and thus voltage ripples generated by a power supply can be filtered out so as to supply a stable voltage to a load.
Description
Technical field
The present invention relates to a kind of capacitive property optimization and use this capacitive property optimization designed circuit plate.
Background technology
In the design of power circuit; Because the change of the electric current of load possibly cause the fluctuation of output voltage; And then produce voltage ripple (voltage ripple), add capacitor filtering so the designer is everlasting between voltage source and the load and think that load provides stable voltage.Yet, capacitor easily with circuit board on the via hole offered produce the overall impedance increase on the inductive effect causes current path, influence the filtering performance of capacitor.
Summary of the invention
In view of above situation, be necessary to provide a kind of capacitive property optimization that improves the capacitor filtering performance.
In addition, also be necessary to provide the above-mentioned capacitive property optimization of a kind of application designed circuit plate.
A kind of capacitive property optimization, it may further comprise the steps: a circuit board is provided, electric capacity pad group is set on this circuit board; Near a side of a pad of electric current inflow direction a plurality of via holes are set in electric capacity pad group, the center of circle of said via hole is positioned on the same semi arch, and this semi arch is the center of circle with the center of said pad.
A kind of circuit board is offered electric capacity pad group and a plurality of via hole on it, said a plurality of via holes are located at the side of electric capacity pad group near a pad of electric current inflow direction, and said a plurality of via holes are that the center of circle is located on the same semi arch with this pad.
Capacitive property optimization of the present invention is provided with a plurality of via holes through the side at a pad of electric capacity pad group, and to make a plurality of via holes be that the center of circle is located on the same semi arch with this pad, reduces the overall impedance on the current path by this.The filtering performance of electric capacity that utilized this method designed circuit plate effective optimization, but and then the voltage ripple that produces of filter out power think that load provides stable voltage.
Description of drawings
Fig. 1 is the floor map of the circuit board of the present invention's first preferred embodiments;
Fig. 2 is the floor map of the circuit board of the present invention's second preferred embodiments;
Fig. 3 is the impedance curve analogous diagram of the capacitor of circuit board installation of the present invention.
The main element symbol description
| |
100、200 |
| |
10 |
| The |
30 |
| Electric |
50 |
| Pad | P |
| Via |
70 |
| |
1、2、3、4、5 |
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
See also Fig. 1, first preferred embodiment of the present invention provides a kind of capacitive property optimization and uses this capacitive property optimization designed circuit plate 100.Power pad 10, load pad 30, electric capacity pad group 50 and a plurality of via hole 70 are set on this circuit board 100.
These power pad 10 usefulness are pegged graft for a power supply (like the 12V power supply), and the electric current of this power supply output is through being connected in the electrical traces output of this power pad 10.
These load pad 30 usefulness are pegged graft for a load (like controller), so that the electric current of power supply output is obtained in load through this load pad 30.
In the present embodiment, the quantity of electric capacity pad group 50 is 2, and each electric capacity pad group 50 comprises two pad P.This electric capacity pad group 50 is electrically connected between power pad 10 and the load pad 30 through electrical traces, so that the electric current of power supply output flows to load pad 30 through this electric capacity pad group 50.These electric capacity pad group 50 usefulness are pegged graft for a capacitor, and then think that through the voltage ripple that this capacitor filter out power produces load provides stable voltage.For reducing voltage ripple effectively, this electric capacity pad group 50 is provided with near load pad 30 relatively.
Via hole 70 is used for electrically connecting the electrical traces of circuit board different electric gas-bearing formation, and the concrete structure of each via hole 70 is identical with known techniques, in repeat no more here.In the present embodiment, the quantity of via hole 70 is 6, and wherein per 3 is one group.3 via holes 70 and one group of electric capacity pad group 50 adjacent setting of every group.Concrete; 3 via holes 70 of every group are located at the side of electric capacity pad group 50 near a pad P of electric current inflow direction; These three via holes 70 are that the center of circle is located on the same semi arch with this pad P; Promptly the center of circle of these three via holes 70 is positioned on the same semi arch, and this semi arch is the center of circle with the center of this pad P.These 3 via hole 70 spaced sets, wherein two via holes 70 are arranged at the two ends of semi arch respectively, and the 3rd via hole 70 is located at the mid point of this semi arch.
See also Fig. 2; Second preferred embodiment of the present invention provides a kind of capacitive property optimization and uses this capacitive property optimization designed circuit plate 200; This circuit board 200 only is with the difference of the circuit board 100 of above-mentioned first execution mode: the quantity of this via hole 70 is 8; Wherein per 4 via holes 70 are one group; 4 via holes 70 of every group are that the center of circle is located on the same semi arch with this pad P, and promptly the center of circle of these 4 via holes 70 is positioned on the same semi arch, and this semi arch is the center of circle with the center of this pad P.These 4 via hole 70 spaced sets, wherein two via holes 70 are arranged at the two ends of semi arch respectively.
Be appreciated that; The group number of the via hole 70 of the quantity of the electric capacity pad group 50 in foregoing circuit plate 100 and the circuit board 200, correspondence and the concrete quantity of every group of via hole 70 can increase and decrease according to real needs, as long as every group of via hole 70 still arranged according to the mode described in foregoing circuit plate 100 or the circuit board 200 with respect to the electric capacity pad group 50 of its correspondence.
Please combine to consult Fig. 3; When wherein not offering via hole 70 near the curve 1 expression electric capacity pad group 50; Be plugged in resonance frequency and the curve chart of impedance of the capacitor of electric capacity pad group 50, if the corresponding impedance of resonance frequency is low more, then expression can suppress the voltage ripple of this frequency more.When curve 2 expression via holes 70 are arranged near other position (between two groups of electric capacity pad groups 50) the electric capacity pad group 50, be plugged in resonance frequency and the curve chart of impedance of the capacitor of electric capacity pad group 50.Curve 3,4,5 representes electric capacity pad group 50 near the side of a pad P of electric current inflow direction 3,4,5 via holes 70 to be set respectively respectively, and (center of circle of said via hole 70 is positioned at same semi arch; And this semi arch is the center of circle with the center of this pad P) time, be plugged in resonance frequency and the curve chart of impedance of the capacitor of electric capacity pad group 50.Can be drawn by Fig. 3, when via hole 70 not being set, the impedance of the resonance frequency of capacitor correspondence is higher; When via hole 70 is located at other position, the resonance frequency of capacitor corresponding impedance decrease, but can't effectively promote the performance of capacitor; When via hole 70 is located at the side of electric capacity pad group 50 near a pad P of electric current inflow direction; And when the center of circle is positioned at same semi arch; The impedance of the resonance frequency correspondence of capacitor is minimum, and the impedance between via hole 70 and the capacitor simultaneously also reduces, and promptly the overall impedance on the current path decreases; Improve the filtering performance of capacitor effectively with this, and then the voltage ripple that filter out power produces thinks that load provides stable voltage.
Capacitive property optimization of the present invention is provided with a plurality of via holes 70 through the side at a pad P of electric capacity pad group 50; And to make a plurality of via holes 70 be that the center of circle is located on the same semi arch with this pad P; Reduce the overall impedance on the current path by this; The filtering performance of electric capacity that utilized these method designed circuit plate 100 effective optimization, but and then the voltage ripple that produces of filter out power think that load provides stable voltage.
Claims (10)
1. capacitive property optimization, it is characterized in that: this capacitive property optimization may further comprise the steps:
One circuit board is provided, electric capacity pad group is set on this circuit board;
Near a side of a pad of electric current inflow direction a plurality of via holes are set in electric capacity pad group, the center of circle of said via hole is positioned on the same semi arch, and this semi arch is the center of circle with the center of said pad.
2. capacitive property optimization as claimed in claim 1 is characterized in that: the mode of said electric capacity pad group system through electrical traces is electrically connected between one group of power pad and the one group of load pad.
3. capacitive property optimization as claimed in claim 2 is characterized in that: said electric current is by the power supply output that is plugged in power pad, and flows to the load that is plugged in the load pad through electric capacity pad group.
4. capacitive property optimization as claimed in claim 3 is characterized in that: said electric capacity pad group and capacitor are pegged graft, the voltage ripple that produces through this capacitor filter out power and then voltage is provided for load.
5. a circuit board is offered electric capacity pad group and a plurality of via hole on it, it is characterized in that: said a plurality of via holes are located at the side of electric capacity pad group near a pad of electric current inflow direction, and said a plurality of via holes are that the center of circle is located on the same semi arch with this pad.
6. circuit board as claimed in claim 5 is characterized in that: power pad and load pad also are set on the said circuit board, and this power pad is used for an electric power connecting, and this load pad is used for a load and pegged graft.
7. circuit board as claimed in claim 6 is characterized in that: said electric capacity pad group is electrically connected between power pad and the load pad through electrical traces.
8. circuit board as claimed in claim 7 is characterized in that: said electric current is exported by the power supply that is plugged in power pad, and flows to the load that is plugged in the load pad through electric capacity pad group.
9. circuit board as claimed in claim 7 is characterized in that: the said electric capacity pad group container that is used to supply power is pegged graft, with the voltage ripple that produces through this capacitor filter out power and then be that load provides voltage.
10. circuit board as claimed in claim 5 is characterized in that: said a plurality of via hole spaced sets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101572837A CN102833939A (en) | 2011-06-13 | 2011-06-13 | Capacitor performance optimization method and circuit board designed by applying same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101572837A CN102833939A (en) | 2011-06-13 | 2011-06-13 | Capacitor performance optimization method and circuit board designed by applying same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102833939A true CN102833939A (en) | 2012-12-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101572837A Pending CN102833939A (en) | 2011-06-13 | 2011-06-13 | Capacitor performance optimization method and circuit board designed by applying same |
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| CN (1) | CN102833939A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109089375A (en) * | 2018-09-26 | 2018-12-25 | 郑州云海信息技术有限公司 | A kind of analysis method and system that signal integrity is influenced for pcb board via hole |
| CN109246923A (en) * | 2018-10-09 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of pcb board and a kind of electronic equipment |
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| CN1917741A (en) * | 2005-08-18 | 2007-02-21 | Tdk株式会社 | Flexible substrate, mounting structure, display unit and portable electronic apparatus |
| CN101005730A (en) * | 2006-01-20 | 2007-07-25 | 佛山市顺德区顺达电脑厂有限公司 | Circuit board for reducing electromagnetic interference of electronic product |
| CN101068453A (en) * | 2007-06-26 | 2007-11-07 | 福建星网锐捷网络有限公司 | Welding pad design method, pad structure, printing circuit board and equipment |
| CN101651237A (en) * | 2009-08-27 | 2010-02-17 | 广东省粤晶高科股份有限公司 | Assembling method of lithium battery protection circuit board with chip directly placed on |
| US7746660B1 (en) * | 2006-10-10 | 2010-06-29 | Xilinx, Inc. | Reduced mounting inductance and increased self-resonant frequency range |
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2011
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030128522A1 (en) * | 2002-01-10 | 2003-07-10 | Eriko Takeda | Radio frequency module |
| CN1917741A (en) * | 2005-08-18 | 2007-02-21 | Tdk株式会社 | Flexible substrate, mounting structure, display unit and portable electronic apparatus |
| CN101005730A (en) * | 2006-01-20 | 2007-07-25 | 佛山市顺德区顺达电脑厂有限公司 | Circuit board for reducing electromagnetic interference of electronic product |
| US7746660B1 (en) * | 2006-10-10 | 2010-06-29 | Xilinx, Inc. | Reduced mounting inductance and increased self-resonant frequency range |
| CN101068453A (en) * | 2007-06-26 | 2007-11-07 | 福建星网锐捷网络有限公司 | Welding pad design method, pad structure, printing circuit board and equipment |
| CN101651237A (en) * | 2009-08-27 | 2010-02-17 | 广东省粤晶高科股份有限公司 | Assembling method of lithium battery protection circuit board with chip directly placed on |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109089375A (en) * | 2018-09-26 | 2018-12-25 | 郑州云海信息技术有限公司 | A kind of analysis method and system that signal integrity is influenced for pcb board via hole |
| CN109089375B (en) * | 2018-09-26 | 2021-07-27 | 郑州云海信息技术有限公司 | Analysis method and system for influence of PCB (printed circuit board) via hole on signal integrity |
| CN109246923A (en) * | 2018-10-09 | 2019-01-18 | 郑州云海信息技术有限公司 | A kind of pcb board and a kind of electronic equipment |
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Application publication date: 20121219 |