CN102832928B - Three-value adiabatic domino addition unit - Google Patents

Abstract

The invention discloses a ternary adiabatic domino addition unit, which comprises a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generation circuit and a standard sum signal generation circuit, and a first ternary adiabatic domino word operation circuit. The domino word operation circuit is respectively connected with the carry signal generating circuit and the standard and signal generating circuit, and the second ternary adiabatic domino word operation circuit is connected with the carry signal generating circuit and the standard and signal generating circuit respectively, and the low-order carry signal input of the carry signal generating circuit is The terminal is connected to the low-order carry signal input terminal of the local and signal generating circuit; the advantage is that under the premise of ensuring correct logic function, the structure is simple, and compared with the three-valued conventional domino adder unit using DC power supply, its power consumption is saved. About 54%, compared with the ternary addition unit based on the DTCTGAL circuit design, the number of transistors is reduced by about 47%.

Description

A Three-valued Adiabatic Domino Addition Unit

technical field

The invention relates to a ternary addition unit, in particular to a ternary adiabatic domino addition unit.

Background technique

The current digital circuit system is mainly implemented by binary logic, and the logic values that can be transmitted by a single signal line are only 0 and 1, and the space and time utilization of the circuit is low. The use of multi-valued logic can greatly reduce the number of circuit input variables and increase the amount of information carried by each connection, thereby reducing the area of the chip and enhancing the data processing capability. Due to its advantages in circuit area and speed, domino circuits are widely used in various high-performance circuits. Therefore, the combination of multi-valued logic and domino circuits can further reduce the circuit area, increase the information density of the circuit, and reduce the circuit cost. .

Addition is the most basic arithmetic operation. In theory, subtraction, multiplication, division, and address calculation can all be realized by addition. Therefore, the adder is not only a key component of the digital system but also one of the most widely used components. The power consumption of the adder determines the power consumption of the entire digital system to a large extent. The power consumption determines the power consumption of the adder. At present, the traditional adding unit causes great waste due to the one-time consumption of the charge from the power supply to the ground; while the adiabatic adder using the AC pulse power supply can fully recover the charge stored in the circuit node and effectively reduce the power consumption of the circuit . In view of this, it has practical significance to apply multi-valued logic, adiabatic logic and domino circuit to the design of adding unit.

Contents of the invention

The technical problem to be solved by the present invention is to provide a ternary adiabatic domino addition unit with low power consumption under the premise of ensuring correct logic function.

The technical scheme adopted by the present invention to solve the above technical problems is: a ternary adiabatic domino addition unit, comprising a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generation circuit, a standard and Signal generation circuit, a first clock signal input end, a second clock signal input end and a third clock signal input end, the carry signal generation circuit is provided with a low-order carry signal input end, an addend word operation signal input end, an added The digital word operation signal input end, the high-order carry signal output end and the complementary high-order carry signal output end, the said basic position and signal generating circuit is provided with an addend word operation signal input end, an augend word operation signal input end, and a low-order carry signal The input terminal, the complementary low-order carry signal input terminal and the base and signal output terminal, the signal input terminal of the first ternary adiabatic domino word operation circuit is used to access the addend input signal, and the first ternary adiabatic domino The signal output end of the word operation circuit is connected with the addend word operation signal input end of the described carry signal generation circuit and the adder word operation signal input end of the described home and signal generation circuit respectively, and the second tertiary value The signal input end of the adiabatic domino word operation circuit is used to access the summand input signal, and the signal output end of the second ternary adiabatic domino word operation circuit is respectively connected with the summand word operation of the carry signal generation circuit The signal input end is connected with the summed word operation signal input end of the said home position and signal generating circuit, and the low bit carry signal input end of the said carry signal generating circuit is connected with the low bit carry signal input of the said home position sum signal generating circuit terminal connection, the first three-value adiabatic domino word operation circuit, the second three-value adiabatic domino word operation circuit and the carry signal generation circuit are respectively connected to the first clock signal input end and the The second clock signal input terminal is connected, and the home position and signal generation circuit are respectively connected with the first clock signal input terminal, the second clock signal input terminal and the third clock signal input terminal. .

The output signals of the signal output end of the first ternary adiabatic domino word operation circuit are three addend word operation signals corresponding to the addend input signal connected to the signal input end, which are respectively the first addend when the addend is logic 0 An addend word operation signal, a second addend word operation signal when the addend is logic 1, and a third addend word operation signal when the addend is logic 2, wherein the addend word operation of the carry signal generating circuit The signal input end is connected to the second addend word operation signal and the third addend word operation signal, and the addend word operation signal input end of the basic sum signal generating circuit is connected to the first addend word operation signal. Addend word operation signal, the second addend word operation signal and the third addend word operation signal, the output signal of the signal output terminal of the second ternary adiabatic domino word operation circuit is its signal input The three summand word operation signals corresponding to the summand input signal connected to the terminal are the first summand word operation signal when the summand is logic 0, and the second summand word operation signal when the summand is logic 1. The addend word operation signal and the third addend word operation signal when the addend is logic 2, wherein the input end of the addend word operation signal of the carry signal generation circuit is connected to the second addend word operation signal and the third summand word operation signal, the input end of the sum signal generating circuit of the said first summand word operation signal is connected to the first summand word operation signal, the The second summand word operation signal and the third summand word operation signal.

The first ternary adiabatic domino word operation circuit includes a word operation module and a waveform conversion module, and the word operation module is composed of a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth Composed of PMOS transistors, sixth PMOS transistors, first NMOS transistors, second NMOS transistors, third NMOS transistors, fourth NMOS transistors, fifth NMOS transistors, sixth NMOS transistors and seventh NMOS transistors, the first NMOS transistors The gate of the transistor is connected in parallel with the gate of the fourth NMOS transistor, and its parallel terminal is a signal input terminal, the drain of the first NMOS transistor, the source of the first PMOS transistor and the The gate of the third PMOS transistor is connected in parallel, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second PMOS transistor is connected to the first NMOS transistor. The drains of the three PMOS transistors are connected, the source of the third PMOS transistor, the drain of the third NMOS transistor and the drain of the seventh NMOS transistor are connected in parallel, and the fourth PMOS transistor The source of the fourth NMOS transistor, the drain of the fourth NMOS transistor, the gate of the sixth PMOS transistor and the gate of the seventh NMOS transistor are connected in parallel, and the source of the fourth NMOS transistor is connected to the The drain of the fifth NMOS transistor is connected, the source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the sixth PMOS transistor is connected to the sixth PMOS transistor. The drains of the six NMOS transistors are connected in parallel, the grid of the first PMOS transistor, the drain of the second PMOS transistor, the grid of the fourth PMOS transistor, and the grid of the fifth PMOS transistor The drain, the gate of the second NMOS transistor, the source of the third NMOS transistor, the gate of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected to the first A clock signal input terminal, the drain of the first PMOS transistor, the gate of the second PMOS transistor, the drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor, The source of the second NMOS transistor, the gate of the third NMOS transistor, the source of the fifth NMOS transistor and the gate of the sixth NMOS transistor are connected to the second clock signal in parallel At the input end, the waveform conversion module is composed of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor and the thirteenth NMOS transistor, and the eighth NMOS transistor The drain of the tube is connected to the drain of the first NMOS tube, the source of the eighth NMOS tube is connected to the gate of the ninth NMOS tube, and the drain of the tenth NMOS tube It is connected to the source of the seventh NMOS transistor, the source of the tenth NMOS transistor is connected to the gate of the eleventh NMOS transistor, and the drain of the twelfth NMOS transistor is connected to the gate of the eleventh NMOS transistor. The source of the sixth PMOS transistor is connected, the source of the twelfth NMOS transistor is connected to the gate of the thirteenth NMOS transistor, the gate of the eighth NMOS transistor, the No. The gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected to the first clock signal input terminal in parallel, the source of the ninth NMOS transistor and the source of the eleventh NMOS transistor The source of the thirteenth NMOS transistor is connected to the second clock signal input end in parallel, the drain of the ninth NMOS transistor is the first signal output end, and the drain of the eleventh NMOS transistor is the first signal output end. Two signal output terminals, the drain of the thirteenth NMOS transistor is the third signal output terminal, the circuit structure of the second ternary adiabatic domino word operation circuit is the same as that of the first ternary adiabatic domino word operation circuit The same, the difference between the two is that the signal input terminal of the first three-value adiabatic domino word operation circuit is connected to the addend input signal, and the first signal output end of the first three-value adiabatic domino word operation circuit outputs the sum The first addend word operation signal when the number is logic 0, the second signal output terminal of the first ternary adiabatic domino word operation circuit outputs the second addend word operation signal when the addend is logic 1, and the The third signal output end of the first three-value adiabatic domino word operation circuit outputs the third addend word operation signal when the addend is logic 2, and the signal input end of the second three-value adiabatic domino word operation circuit is connected to The summand input signal, the first signal output terminal of the second ternary adiabatic domino word operation circuit outputs the first summand word operation signal when the summand is logic 0, and the second ternary adiabatic domino word operation signal The second signal output terminal of the domino literal operation circuit outputs the second summand literal operation signal when the summand is logic 1, and the third signal output terminal of the second ternary adiabatic domino literal operation circuit outputs the summand The third summand word operation signal when it is logic 2.

The carry signal generating circuit is composed of the seventh PMOS transistor, the eighth PMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, the eighteenth NMOS transistor, the tenth Nine NMOS tubes, twenty NMOS tubes, twenty-first NMOS tubes, twenty-second NMOS tubes, twenty-third NMOS tubes, twenty-fourth NMOS tubes, twenty-fifth NMOS tubes, and twenty-sixth NMOS tubes Composed of tubes, the source of the seventh PMOS tube, the gate of the eighth PMOS tube, the drain of the fourteenth NMOS tube, the drain of the twenty-first NMOS tube, The drain of the twenty-third NMOS transistor and the drain of the twenty-fourth NMOS transistor are connected in parallel to the complementary high-order carry signal output end of the carry signal generating circuit, and the fourteenth NMOS transistor The source of the tube, the drain of the fifteenth NMOS tube, the drain of the seventeenth NMOS tube and the drain of the eighteenth NMOS tube are connected, and the fifteenth NMOS tube the source of the sixteenth NMOS transistor, the source of the seventeenth NMOS transistor, the source of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor pole, the source of the twenty-second NMOS transistor is connected to the source of the twenty-fifth NMOS transistor, the source of the eighteenth NMOS transistor is connected to the nineteenth NMOS transistor The drain is connected, the source of the twenty-first NMOS transistor is connected to the drain of the twenty-first NMOS transistor, and the source of the twenty-third NMOS transistor is connected to the twenty-second NMOS transistor. The drain of the NMOS transistor is connected, the source of the twenty-fourth NMOS transistor is connected to the drain of the twenty-fifth NMOS transistor, the source of the eighth PMOS transistor is connected to the second The drains of the sixteenth NMOS transistors are connected in parallel to the high-order carry signal output end of the carry signal generation circuit, and the gate of the fourteenth NMOS transistor is the low-order carry signal input end of the carry signal generation circuit. The gate of the eighteenth NMOS transistor and the gate of the twentieth NMOS transistor are both connected to the second addend word operation signal when the addend is logic 1, and the gate of the fifteenth NMOS transistor is pole, the gate of the twenty-third NMOS transistor and the gate of the twenty-fourth NMOS transistor are all connected to the third addend word operation signal when the addend is logic 2, and the tenth The gates of the nine NMOS transistors and the gates of the twenty-second NMOS transistors are connected to the second summand word operation signal when the summand is logic 1, and the gates of the seventeenth NMOS transistors are , the gate of the twenty-first NMOS transistor and the gate of the twenty-fifth NMOS transistor are both connected to the third summand word operation signal when the summand is logic 2, and the second The drains of the seven PMOS transistors, the source of the sixteenth NMOS transistor, and the gate of the twenty-sixth NMOS transistor are connected to the first clock signal input terminal in parallel, and the gate of the seventh PMOS transistor pole, the gate of the sixteenth NMOS transistor, the eighth P The drain of the MOS transistor and the source of the twenty-sixth NMOS transistor are connected in parallel to the second clock signal input end.

The said position and signal generation circuit includes a first control circuit for controlling logic 1 generation, a second control circuit for controlling logic 2 generation and a position and signal output circuit, and the first control circuit is composed of the ninth PMOS tube, the twenty-seventh NMOS tube, the twenty-eighth NMOS tube, the twenty-ninth NMOS tube, the thirty NMOS tube, the thirty-first NMOS tube, the thirty-second NMOS tube, the thirty-third NMOS tube, The thirty-fourth NMOS tube, the thirty-fifth NMOS tube, the thirty-sixth NMOS tube, the thirty-seventh NMOS tube, the thirty-eighth NMOS tube, the thirty-ninth NMOS tube, the fortieth NMOS tube and the fourth Eleven NMOS transistors, the source of the ninth PMOS transistor, the drain of the twenty-seventh NMOS transistor, the drain of the thirtieth NMOS transistor, the thirty-second NMOS transistor The drain of the tube, the drain of the thirty-fourth NMOS tube, the drain of the thirty-seventh NMOS tube and the drain of the thirty-ninth NMOS tube are connected to the first control signal in parallel output terminal, the first control signal output terminal outputs a control signal of a logic 1 signal, the source of the twenty-seventh NMOS transistor is connected to the drain of the twenty-eighth NMOS transistor, and the The source of the twenty-eighth NMOS transistor, the drain of the twenty-ninth NMOS transistor, the source of the thirty-first NMOS transistor are connected to the source of the thirty-third NMOS transistor, The source of the twenty-ninth NMOS transistor, the source of the thirty-sixth NMOS transistor are connected to the drain of the forty-first NMOS transistor, and the source of the thirty-first NMOS transistor pole is connected to the drain of the thirty-first NMOS transistor, the source of the thirty-second NMOS transistor is connected to the drain of the thirty-third NMOS transistor, and the thirty-fourth NMOS transistor is connected to the drain. The source of the NMOS transistor is connected to the drain of the thirty-fifth NMOS transistor, the source of the thirty-seventh NMOS transistor is connected to the drain of the thirty-eighth NMOS transistor, and the The source of the thirty-ninth NMOS transistor is connected to the drain of the fortieth NMOS transistor, the source of the thirty-fifth NMOS transistor, the drain of the thirty-sixth NMOS transistor, The source of the thirty-eighth NMOS transistor is connected to the source of the fortieth NMOS transistor, the gate of the twenty-seventh NMOS transistor is connected to the gate of the thirty-fourth NMOS transistor The first addend word operation signal when the addend is logic 0 is connected, and the gate of the 30th NMOS transistor and the gate of the thirty-seventh NMOS transistor are connected with the addend being logic 1. When the second addend word operation signal, the gate of the thirty-second NMOS transistor and the gate of the thirty-ninth NMOS transistor are connected to the third addend word when the addend is logic 2 Operation signal, the gate of the twenty-eighth NMOS transistor and the gate of the fortieth NMOS transistor are both connected to the second summand word operation signal when the summand is logic 1, and the The grid of the thirty-first NMOS transistor and the grid of the thirty-fifth NMOS transistor are both connected to Input the first summand word operation signal when the summand is logic 0, the gate of the thirty-third NMOS transistor and the gate of the thirty-eighth NMOS transistor are connected to the summand as The third summand word operation signal when the logic is 2, the second control circuit is composed of the tenth PMOS tube, the forty-second NMOS tube, the forty-third NMOS tube, the forty-fourth NMOS tube, the forty-fourth NMOS tube, and the forty-fourth NMOS tube. Five NMOS tubes, forty-sixth NMOS tubes, forty-seventh NMOS tubes, forty-eighth NMOS tubes, forty-ninth NMOS tubes, fiftieth NMOS tubes, fifty-first NMOS tubes, fifty-second NMOS tubes tube, the fifty-third NMOS tube, the fifty-fourth NMOS tube, the fifty-fifth NMOS tube and the fifty-sixth NMOS tube, the source of the tenth PMOS tube, the forty-second NMOS tube the drain of the forty-sixth NMOS transistor, the drain of the forty-eighth NMOS transistor, the drain of the fiftieth NMOS transistor, the fifty-third The drain of the NMOS transistor and the drain of the fifty-fifth NMOS transistor are connected in parallel to the second control signal output end, and the second control signal output end outputs a control signal of a logic 2 signal, and the fourth The source of the twelfth NMOS transistor is connected to the drain of the forty-third NMOS transistor, the source of the forty-third NMOS transistor, the drain of the forty-fourth NMOS transistor, the The source of the forty-seventh NMOS transistor is connected to the source of the forty-ninth NMOS transistor, the source of the forty-fourth NMOS transistor, and the drain of the forty-fifth NMOS transistor It is connected to the source of the fifty-second NMOS transistor, the source of the forty-sixth NMOS transistor is connected to the drain of the forty-seventh NMOS transistor, and the forty-eighth NMOS transistor is connected to the drain of the forty-seventh NMOS transistor. The source of the tube is connected to the drain of the forty-ninth NMOS tube, the source of the fiftieth NMOS tube is connected to the drain of the fifty-first NMOS tube, and the fifth The source of the thirteenth NMOS transistor is connected to the drain of the fifty-fourth NMOS transistor, and the source of the fifty-fifth NMOS transistor is connected to the drain of the fifty-sixth NMOS transistor. The source of the fifty-first NMOS transistor, the drain of the fifty-second NMOS transistor, the source of the fifty-fourth NMOS transistor, and the source of the fifty-sixth NMOS transistor connected, the gate of the forty-second NMOS transistor and the gate of the fiftieth NMOS transistor are connected to the first addend word operation signal when the addend is logic 0, and the fortieth The gates of the six NMOS transistors and the gates of the fifty-third NMOS transistors are connected to the second addend word operation signal when the addend is logic 1, and the gates of the forty-eighth NMOS transistors and The gate of the fifty-fifth NMOS transistor is connected to the third addend word operation signal when the addend is logic 2, the gate of the forty-third NMOS transistor and the fifty-sixth The gates of the NMOS transistors are all connected to the second summand word operation signal when the summand is logic 1, and the forty-seventh NMO The grid of the S tube and the grid of the fifty-first NMOS tube are connected to the first summand word operation signal when the summand is logic 0, and the grid of the forty-ninth NMOS tube is The gate of the fifty-fourth NMOS transistor is connected to the third summand literal operation signal when the summand is logic 2, and the described basic position and signal output circuit is composed of the eleventh PMOS transistor and the tenth PMOS transistor. Composed of two PMOS transistors and a fifty-seventh NMOS transistor, the gate of the eleventh PMOS transistor is connected to the first control signal output end, and the gate of the twelfth PMOS transistor is connected to the The second control signal output terminal is connected, the source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor and the drain of the fifty-seventh NMOS transistor are connected in parallel and connected in parallel terminal is the standard and signal output terminal of the said standard and signal generating circuit, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, and the drain of the twelfth PMOS transistor , the gate of the forty-first NMOS transistor, the gate of the forty-fifth NMOS transistor, and the source of the fifty-seventh NMOS transistor are connected to the second clock signal input terminal in parallel, so The drain of the ninth PMOS transistor, the drain of the tenth PMOS transistor, the source of the forty-first NMOS transistor, the source of the forty-fifth NMOS transistor, and the first The gate of the fifty-seventh NMOS transistor is connected to the first clock signal input end in parallel, the drain of the eleventh PMOS transistor is connected to the third clock signal input end, and the gate of the twenty-ninth NMOS transistor The gate of the forty-fourth NMOS transistor is connected in parallel and its parallel connection end is the complementary low-order carry signal input end of the described local sum signal generating circuit, and the grid of the thirty-sixth NMOS transistor and The gates of the fifty-second NMOS transistors are connected in parallel, and the parallel connection terminal is the low-order carry signal input terminal of the local sum signal generating circuit.

Compared with the prior art, the present invention has the advantages of applying multi-valued logic, adiabatic logic and domino circuit to the design of the adding unit, combining the switch signal theory to design a ternary adiabatic domino adding unit that meets the correct logic function, The addition unit is composed of a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generation circuit and a standard sum signal generation circuit, the logic function is correct, and the structure is simple. Compared with the conventional domino adder unit, the power consumption of the adiabatic ternary adding unit is reduced by about 54%, and compared with the ternary adding unit based on the DTCTGAL circuit design, the number of transistors is reduced by about 47%.

Description of drawings

Fig. 1 (a) is the circuit schematic diagram of the present invention;

Fig. 1 (b) is the circuit symbol diagram of the present invention;

Fig. 2 (a) is the circuit diagram of the word operation module of the first ternary adiabatic domino word operation circuit of embodiment;

Fig. 2 (b) is the circuit diagram of the waveform conversion module of the first ternary adiabatic domino word operation circuit of embodiment;

Fig. 2 (c) is the circuit symbol diagram of the first ternary adiabatic domino word operation circuit of embodiment;

Fig. 3 (a) is the circuit diagram of the carry signal generating circuit of the embodiment;

Fig. 3 (b) is the circuit symbol diagram of the carry signal generating circuit of the embodiment;

Fig. 4 (a) is the circuit diagram of the first control circuit of the home position and signal generating circuit of the embodiment;

Fig. 4 (b) is the circuit diagram of the second control circuit of the home position and signal generating circuit of the embodiment;

Fig. 4 (c) is the circuit diagram of the home and signal output circuit of the home and signal generating circuit of the embodiment;

Fig. 4 (d) is the circuit symbol diagram of the home position and signal generating circuit of the embodiment;

Fig. 5 is the waveform diagram of three clock signals of the embodiment;

Fig. 6 is the analog waveform figure of the present invention;

Fig. 7 is a comparison diagram of transient energy consumption between the three-value adiabatic domino addition unit of the present invention and the three-value conventional domino addition unit.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

As shown in Figure 1(a) and Figure 1(b), a ternary adiabatic domino addition unit includes a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generation circuit, The base sum signal generating circuit, the first clock signal input end, the second clock signal input end and the third clock signal input end, the carry signal generating circuit is provided with a low-order carry signal input end, an addend word operation signal input end, and an addend The word operation signal input end, the high-order carry signal output end and the complementary high-order carry signal output end. The low-order carry signal input terminal and the base and signal output terminal, the signal input terminal of the first ternary adiabatic domino word operation circuit is used to access the addend input signal, and the signal output end of the first ternary adiabatic domino word operation circuit is respectively connected to the carry The addend word operation signal input end of the signal generation circuit is connected to the addend word operation signal input end of the home position and signal generation circuit, and the signal input end of the second ternary adiabatic domino word operation circuit is used to access the summand input signal, The signal output end of the second ternary adiabatic domino word operation circuit is respectively connected with the summand word operation signal input end of the carry signal generation circuit and the sum sum signal generation circuit. The low-order carry signal input end is connected with the low-order carry signal input end of the home position and signal generating circuit, and the first three-value adiabatic domino word operation circuit, the second three-value adiabatic domino word operation circuit and the carry signal generation circuit are respectively connected to the first clock signal The input terminal is connected to the second clock signal input terminal, and the home position and signal generating circuit are respectively connected to the first clock signal input terminal, the second clock signal input terminal and the third clock signal input terminal. The output signals of the signal output end of the first ternary adiabatic domino word operation circuit are three addend word operation signals corresponding to the addend input signal connected to the signal input end, which are respectively the first addend when the addend is logic 0 The word operation signal, the second addend word operation signal when the addend is logic 1, and the third addend word operation signal when the addend is logic 2, wherein the addend word operation signal input terminal of the carry signal generation circuit is connected to the first The two addend word operation signal and the third addend word operation signal, the addend word operation signal input terminal of the original sum signal generating circuit is connected to the first addend word operation signal, the second addend word operation signal and the third addend word operation signal Word operation signal, the output signal of the signal output terminal of the second ternary adiabatic domino word operation circuit is three summand word operation signals corresponding to the summand input signal connected to its signal input end, respectively, the summand is logic The first summand word operation signal when the summand is 0, the second summand word operation signal when the summand is logic 1, and the third summand word operation signal when the summand is logic 2, wherein the carry signal generates The input terminal of the summand word operation signal of the circuit is connected to the second summand word operation signal and the third summand word operation signal, and the input terminal of the sum signal generating circuit is connected to the first summand word operation signal. A digital word operation signal, a second summand word operation signal and a third summand word operation signal.

The design principle of the present invention is as follows: firstly introduce the switch signal theory, introduce switch variables and signal variables and the corresponding switch algebra and signal algebra in the multi-valued logic circuit, and provide a reliable theoretical basis for the design of the multi-valued circuit. Signal theory shows that the voltage switch in the CMOS circuit can be used to control the ground short circuit or the source short circuit of the output voltage signal, and can directly control the transmission of the output voltage signal. The truth table of the ternary adder is shown in Table 1, where A is the addend input signal, B is the augend input signal, C _in is the low carry signal from the low bit, S is the basic bit and output signal, and C _out is the transmission Give the high bit carry signal to the high bit.

Table 1 Truth table of ternary adder

Since the evaluation circuit of the domino circuit generally only has NMOS tubes or PMOS tubes, it is impossible to directly distinguish the logic 1 signal, so we first need to obtain a three-value adiabatic domino word operation circuit, so that the input signal of the three-value adder first passes through the three-value adiabatic domino After the word operation circuit, the required signal is obtained by outputting. Assuming that the addend input signal is A and the summand input signal is B, the output signals after the three-valued adiabatic domino word operation circuit are ⁰ A ⁰ , ¹ A ¹ , ² A ² , ⁰ B ⁰ , ¹ B ¹ and ² B ² . The three clock signal input terminals (the first clock signal input terminal, the second clock signal input terminal and the third clock signal input terminal) of the ternary adiabatic domino adding unit are respectively connected to a clock signal, and the three clock signals can be recorded as The first clock signal clk, the second clock signal and a third clock signal Among them, the first clock signal clk, the second clock signal The amplitude level corresponds to logic 2, the third clock signal The amplitude level corresponds to logic 1, the second clock signal with the third clock signal In the same phase, the first clock signal clk is opposite to the first two (that is, the phase difference is 180 degrees), and then according to the switch signal theory and the truth table of the ternary adder, the carry signal generation circuit and the standard sum signal generation circuit are obtained, thereby obtaining Circuit diagram of a ternary adiabatic domino adder unit.

Embodiment: a ternary adiabatic domino addition unit, comprising a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generating circuit and a standard sum signal generating circuit; the first ternary adiabatic domino The word operation circuit includes a word operation module and a waveform conversion module. As shown in Fig. 2(a), the text operation module consists of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a An NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and a seventh NMOS transistor N7, the gate of the first NMOS transistor N1 The gate of the fourth NMOS transistor N4 is connected in parallel and its parallel terminal is a signal input terminal, the drain of the first NMOS transistor N1, the source of the first PMOS transistor P1 and the gate of the third PMOS transistor P3 are connected in parallel, The source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, the source of the second PMOS transistor P2 is connected to the drain of the third PMOS transistor P3, the source of the third PMOS transistor P3, the third NMOS The drain of the transistor N3 and the drain of the seventh NMOS transistor N7 are connected in parallel, the source of the fourth PMOS transistor P4, the drain of the fourth NMOS transistor N4, the gate of the sixth PMOS transistor P6 and the seventh NMOS transistor N7 The gates are connected in parallel, the source of the fourth NMOS transistor N4 is connected to the drain of the fifth NMOS transistor N5, the source of the fifth PMOS transistor P5 is connected to the drain of the sixth PMOS transistor P6, and the source of the sixth PMOS transistor P6 pole and the drain of the sixth NMOS transistor N6 are connected in parallel, the gate of the first PMOS transistor P1, the drain of the second PMOS transistor P2, the gate of the fourth PMOS transistor P4, the drain of the fifth PMOS transistor P5, the drain of the fifth PMOS transistor P5, The gate of the second NMOS transistor N2, the source of the third NMOS transistor N3, the gate of the fifth NMOS transistor N5, and the source of the sixth NMOS transistor N6 are connected to the first clock signal input terminal in parallel to receive the first clock signal clk, the drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2, the drain of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, the source of the second NMOS transistor N2, the third NMOS The gate of the transistor N3, the source of the fifth NMOS transistor N5, and the gate of the sixth NMOS transistor N6 are connected to the second clock signal input terminal in parallel to receive the second clock signal As shown in Figure 2(b), the waveform conversion module consists of the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12 and the thirteenth NMOS transistor N13, the drain of the eighth NMOS transistor N8 is connected to the drain of the first NMOS transistor N1, the source of the eighth NMOS transistor N8 is connected to the gate of the ninth NMOS transistor N9, and the drain of the tenth NMOS transistor N10 is connected to the gate of the ninth NMOS transistor N10. The source of the seventh NMOS transistor N7 is connected, the source of the tenth NMOS transistor N10 is connected to the gate of the eleventh NMOS transistor N11, the drain of the twelfth NMOS transistor N12 is connected to the source of the sixth PMOS transistor P6, The source of the twelfth NMOS transistor N12 is connected to the gate of the thirteenth NMOS transistor N13, the gate of the eighth NMOS transistor N8, the gate of the tenth NMOS transistor N10, and the gate of the twelfth NMOS transistor N12 are connected in parallel. The first clock signal clk is connected to the first clock signal input terminal, and the source of the ninth NMOS transistor N9, the source of the eleventh NMOS transistor N11 and the source of the thirteenth NMOS transistor N13 are connected in parallel to the second clock Signal input terminal, access to the second clock signal The drain of the ninth NMOS transistor N9 is the first signal output end, the drain of the eleventh NMOS transistor N11 is the second signal output end, and the drain of the thirteenth NMOS transistor N13 is the third signal output end; the first ternary adiabatic domino The circuit symbol diagram of the word operation circuit is shown in Figure 2(c); the circuit structure of the second ternary adiabatic domino word operation circuit is the same as that of the first ternary adiabatic domino word operation circuit, the difference between the two is that the first ternary adiabatic domino word operation circuit The signal input terminal of the domino word operation circuit is connected to the addend input signal A, and the first signal output end of the first ternary adiabatic domino word operation circuit outputs the first addend word operation signal ⁰ A ⁰ when the addend is logic 0, The second signal output terminal of the first three-value adiabatic domino word operation circuit outputs the second addend word operation signal ¹ A ¹ when the addend is logic 1, and the third signal output terminal of the first three-value adiabatic domino word operation circuit outputs The third addend word operation signal ² A ² when the addend is logic 2, the signal input terminal of the second ternary adiabatic domino word operation circuit is connected to the summand input signal B, the second ternary adiabatic domino word operation circuit The first signal output terminal outputs the first summand word operation signal ⁰ B ⁰ when the summand is logic 0, and the second signal output terminal of the second ternary adiabatic domino word operation circuit outputs the signal when the summand is logic 1 The second summand word operation signal ¹ B ¹ , the third signal output end of the second ternary adiabatic domino word operation circuit outputs the third summand word operation signal ² B ² when the summand is logic 2.

As shown in Figure 3(a), in this embodiment, the carry signal generating circuit is composed of the seventh PMOS transistor P7, the eighth PMOS transistor P8, the fourteenth NMOS transistor N14, the fifteenth NMOS transistor N15, and the sixteenth NMOS transistor N16, the seventeenth NMOS tube N17, the eighteenth NMOS tube N18, the nineteenth NMOS tube N19, the twentieth NMOS tube N20, the twenty-first NMOS tube N21, the twenty-second NMOS tube N22, the twenty-third The NMOS transistor N23, the twenty-fourth NMOS transistor N24, the twenty-fifth NMOS transistor N25 and the twenty-sixth NMOS transistor N26 are composed of the source of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, and the fourteenth PMOS transistor P8. The drain of the NMOS transistor N14, the drain of the twenty-first NMOS transistor N21, the drain of the twenty-third NMOS transistor N23 and the drain of the twenty-fourth NMOS transistor N24 are connected to the complementary high-order carry of the carry signal generating circuit Signal output terminal, output complementary high-order carry signal The source of the fourteenth NMOS transistor N14, the drain of the fifteenth NMOS transistor N15, the drain of the seventeenth NMOS transistor N17 and the drain of the eighteenth NMOS transistor N18 are connected, and the source of the fifteenth NMOS transistor N15 , the drain of the sixteenth NMOS transistor N16, the source of the seventeenth NMOS transistor N17, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20, the source of the twenty-second NMOS transistor N22 electrode is connected to the source of the twenty-fifth NMOS transistor N25, the source of the eighteenth NMOS transistor N18 is connected to the drain of the nineteenth NMOS transistor N19, the source of the twenty-first NMOS transistor N21 is connected to the twentieth NMOS transistor N21 The drain of the transistor N20 is connected, the source of the twenty-third NMOS transistor N23 is connected to the drain of the twenty-second NMOS transistor N22, the source of the twenty-fourth NMOS transistor N24 is connected to the drain of the twenty-fifth NMOS transistor N25 pole connection, the source of the eighth PMOS transistor P8 and the drain of the twenty-sixth NMOS transistor N26 are connected in parallel to the high-order carry signal output end of the carry signal generating circuit, and the high-order carry signal C _out is output, and the drain of the fourteenth NMOS transistor N14 The gate is the low-order carry signal input terminal of the carry signal generation circuit, which is connected to the low-order carry signal C _in . The second addend word operation signal ¹ A ¹ , the gate of the fifteenth NMOS transistor N15, the gate of the twenty-third NMOS transistor N23 and the gate of the twenty-fourth NMOS transistor N24 are all connected to the addend as logic 2 When the third addend word operation signal ² A ² is used, the gate of the nineteenth NMOS transistor N19 and the gate of the twenty-second NMOS transistor N22 are connected to the second addend word when the addend is logic 1 Operation signal ¹ B ¹ , the gate of the seventeenth NMOS transistor N17, the gate of the twenty-first NMOS transistor N21 and the gate of the twenty-fifth NMOS transistor N25 are all connected to the third gate when the summand is logic 2. The summed word operation signal ² B ² , the drain of the seventh PMOS transistor P7, the source of the sixteenth NMOS transistor N16, and the gate of the twenty-sixth NMOS transistor N26 are connected to the first clock signal input terminal in parallel, and connected to input the first clock signal clk, the gate of the seventh PMOS transistor P7, the gate of the sixteenth NMOS transistor N16, the drain of the eighth PMOS transistor P8 and the source of the twenty-sixth NMOS transistor N26 are connected to the second Clock signal input terminal, access to the second clock signal The circuit symbol diagram of the carry signal generation circuit is shown in Figure 3(b).

In this embodiment, the home position sum signal generating circuit includes a first control circuit for controlling logic 1 generation, a second control circuit for controlling logic 2 generation, and a home position sum signal output circuit. As shown in Figure 4(a), the first control circuit consists of the ninth PMOS transistor P9, the twenty-seventh NMOS transistor N27, the twenty-eighth NMOS transistor N28, the twenty-ninth NMOS transistor N29, and the thirtieth NMOS transistor N30 , the thirty-first NMOS transistor N31, the thirty-second NMOS transistor N32, the thirty-third NMOS transistor N33, the thirty-fourth NMOS transistor N34, the thirty-fifth NMOS transistor N35, the thirty-sixth NMOS transistor N36, the thirty-sixth NMOS transistor N36, Composed of the thirty-seventh NMOS transistor N37, the thirty-eighth NMOS transistor N38, the thirty-ninth NMOS transistor N39, the fortieth NMOS transistor N40 and the forty-first NMOS transistor N41, the source of the ninth PMOS transistor P9, the second The drain of the seventeenth NMOS transistor N27, the drain of the thirty-second NMOS transistor N30, the drain of the thirty-second NMOS transistor N32, the drain of the thirty-fourth NMOS transistor N34, the drain of the thirty-seventh NMOS transistor N37 and the drain of the thirty-ninth NMOS transistor N39 are connected to the first control signal output end in parallel, and the first control signal output end outputs a control signal _Y1 of a logic 1 signal, and the source of the twenty-seventh NMOS transistor N27 is connected to the first control signal output end. The drain of the twenty-eighth NMOS transistor N28 is connected, the source of the twenty-eighth NMOS transistor N28, the drain of the twenty-ninth NMOS transistor N29, the source of the thirty-first NMOS transistor N31 and the thirty-third NMOS transistor The source of N33 is connected, the source of the twenty-ninth NMOS transistor N29, the source of the thirty-sixth NMOS transistor N36 and the drain of the forty-first NMOS transistor N41 are connected, and the source of the thirty-ninth NMOS transistor N30 is connected to The drain of the thirty-first NMOS transistor N31 is connected, the source of the thirty-second NMOS transistor N32 is connected to the drain of the thirty-third NMOS transistor N33, the source of the thirty-fourth NMOS transistor N34 is connected to the thirty-fifth NMOS transistor N34 The drain of the NMOS transistor N35 is connected, the source of the thirty-seventh NMOS transistor N37 is connected to the drain of the thirty-eighth NMOS transistor N38, the source of the thirty-ninth NMOS transistor N39 is connected to the drain of the fortieth NMOS transistor N40 connection, the source of the thirty-fifth NMOS transistor N35, the drain of the thirty-sixth NMOS transistor N36, the source of the thirty-eighth NMOS transistor N38 and the source of the fortieth NMOS transistor N40 are connected, the twenty The gate of the seventh NMOS transistor N27 and the gate of the thirty-fourth NMOS transistor N34 are connected to the first addend word operation signal ⁰ A ⁰ when the addend is logic 0, and the gate of the thirtieth NMOS transistor N30 is connected to the gate of the third NMOS transistor N30. The gate of the thirty-seventh NMOS transistor N37 is connected to the second addend word operation signal ¹ A ¹ when the addend is logic 1, the gate of the thirty-second NMOS transistor N32 and the gate of the thirty-ninth NMOS transistor N39 The poles are evenly connected to the second addend word operation signal ² A ² when the addend is logic 2, the gate of the twenty-eighth NMOS transistor N28 and the gate of the fortieth NMOS transistor N40 are both connected to the addend as logic 1, the second summand word operation signal ¹ B ¹ , the gate of the thirty-first NMOS transistor N31 pole and the gate of the thirty-fifth NMOS transistor N35 are connected to the first summand word operation signal ⁰ B ⁰ when the summand is logic 0, the gate of the thirty-third NMOS transistor N33 and the gate of the thirty-eighth The grid of the NMOS transistor N38 is all connected to the third summand word operation signal ² B ² when the summand is logic 2; as shown in Figure 4 (b), the second control circuit consists of the tenth PMOS transistor P10, the first Forty-two NMOS tube N42, forty-third NMOS tube N43, forty-fourth NMOS tube N44, forty-fifth NMOS tube N45, forty-sixth NMOS tube N46, forty-seventh NMOS tube N47, forty-seventh Eighth NMOS tube N48, forty-ninth NMOS tube N49, fifty-first NMOS tube N50, fifty-first NMOS tube N51, fifty-second NMOS tube N52, fifty-third NMOS tube N53, fifty-fourth NMOS tube N54, the fifty-fifth NMOS transistor N55 and the fifty-sixth NMOS transistor N56, the source of the tenth PMOS transistor P10, the drain of the forty-second NMOS transistor N42, the drain of the forty-sixth NMOS transistor N46, The drain of the forty-eighth NMOS transistor N48, the drain of the fiftieth NMOS transistor N50, the drain of the fifty-third NMOS transistor N53, and the drain of the fifty-fifth NMOS transistor N55 are connected in parallel to the second control signal output terminal, the second control signal output terminal outputs the control signal Y ₂ of the logic 2 signal, the source of the forty-second NMOS transistor N42 is connected to the drain of the forty-third NMOS transistor N43, and the source of the forty-third NMOS transistor N43 pole, the drain of the forty-fourth NMOS transistor N44, the source of the forty-seventh NMOS transistor N47 and the source of the forty-ninth NMOS transistor N49 are connected, the source of the forty-fourth NMOS transistor N44, the fifty The source of the second NMOS transistor N52 is connected to the drain of the forty-fifth NMOS transistor N45, the source of the forty-sixth NMOS transistor N46 is connected to the drain of the forty-seventh NMOS transistor N47, and the forty-eighth NMOS transistor N48 The source of the forty-ninth NMOS transistor N49 is connected to the drain of the forty-ninth NMOS transistor N49, the source of the fiftieth NMOS transistor N50 is connected to the drain of the fifty-first NMOS transistor N51, and the source of the fifty-third NMOS transistor N53 is connected to the drain of the fifty-third NMOS transistor N53. The drain of the fifty-fourth NMOS transistor N54 is connected, the source of the fifty-fifth NMOS transistor N55 is connected to the drain of the fifty-sixth NMOS transistor N56, the source of the fifty-first NMOS transistor N51, the fifty-second NMOS transistor The drain of the transistor N52, the source of the fifty-fourth NMOS transistor N54 and the source of the fifty-sixth NMOS transistor N56 are connected, and the gate of the forty-second NMOS transistor N42 and the gate of the fiftieth NMOS transistor N50 are connected The first addend literal operation signal ⁰ A ⁰ when the addend is logic 0 is connected, and the gate of the forty-sixth NMOS transistor N46 and the gate of the fifty-third NMOS transistor N53 are both connected when the addend is logic 1 The second addend word operation signal ¹ A ¹ , the gate of the forty-eighth NMOS transistor N48 and the fifty-fifth The gates of NMOS transistor N55 are all connected to the third addend word operation signal ² A ² when the addend is logic 2, and the gates of the forty-third NMOS transistor N43 and the fifty-sixth NMOS transistor N56 are connected to Input the second summand literal operation signal ¹ B ¹ when the summand is logic 1, the gate of the forty-seventh NMOS transistor N47 and the gate of the fifty-first NMOS transistor N51 are connected to the summand as logic The first summand literal operation signal ⁰ B ⁰ at 0, the gate of the forty-ninth NMOS transistor N49 and the gate of the fifty-fourth NMOS transistor N54 are both connected to the third summand when the summand is logic 2 Addend word operation signal ² B ² ; as shown in Figure 4 (c), the home position and signal output circuit is made up of the eleventh PMOS transistor P11, the twelfth PMOS transistor P12 and the fifty-seventh NMOS transistor N57, the eleventh The gate of the PMOS transistor P11 is connected to the first control signal output end, the gate of the twelfth PMOS transistor P12 is connected to the second control signal output end, the source of the eleventh PMOS transistor P11, the source of the twelfth PMOS transistor P12 The source and the drain of the fifty-seventh NMOS transistor N57 are connected in parallel and its parallel connection end is the standard and signal output end of the standard and signal generating circuit, which outputs the standard and output signal S, the gate of the ninth PMOS transistor P9, the first The gate of the tenth PMOS transistor P10, the drain of the twelfth PMOS transistor P12, the gate of the forty-first NMOS transistor N41, the gate of the forty-fifth NMOS transistor N45, and the source of the fifty-seventh NMOS transistor N57 And connected to the second clock signal input terminal, access to the second clock signal The drain of the ninth PMOS transistor P9, the drain of the tenth PMOS transistor P10, the source of the forty-first NMOS transistor N41, the source of the forty-fifth NMOS transistor N45, and the gate of the fifty-seventh NMOS transistor N57 And connected to the first clock signal input terminal, connected to the first clock signal clk, the drain of the eleventh PMOS transistor P11 is connected to the third clock signal input terminal, connected to the third clock signal The gate of the twenty-ninth NMOS transistor N29 and the gate of the forty-fourth NMOS transistor N44 are connected in parallel, and the parallel connection end is the complementary low-order carry signal input end of the local and signal generating circuit, and the complementary low-order carry signal is connected. The gate of the thirty-sixth NMOS transistor N36 and the gate of the fifty-second NMOS transistor N52 are connected in parallel, and the parallel terminal is the low-order carry signal input end of the local sum signal generating circuit, which is connected to the low-order carry signal C _in . The circuit symbol diagram of the local and signal generation circuit is shown in Figure 4(d).

The design idea of the carry signal generation circuit in this embodiment is as follows: firstly, according to the switch signal theory and the truth table of the ternary adder, the complementary high-order carry signal is obtained and the switch-level structural formulas of the high-order carry signal C _out are:

${\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; clk</span>}}<span\; class="notranslate">\; *</span>{\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}}^{\mathrm{<span\; class="notranslate">\; 0.5</span>}}<span\; class="notranslate">\; \#</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; clk</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; clk</span>}_{\mathrm{<span\; class="notranslate">\; 1.5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

In formula (1), means when When it is low, clk precharges the dynamic node of the complementary high-order carry signal output; the latter item indicates that when is high level, and when the input signal A+B+C _in > 2, the charge stored in the dynamic node at the output terminal of the complementary high-order carry signal is recovered to the process of clk; formula (2) represents the complementary high-order carry signal The process of obtaining the high-order carry signal C _out through the adiabatic inverter. From formula (1) and formula (2) can get the circuit diagram of the carry signal generation circuit shown in the figure.

The design idea of the standard and signal generating circuit of this embodiment is as follows: firstly, according to the switch signal theory and the truth table of the ternary adder, the switch-level structural formula and circuit of the standard and output signal S are obtained, but it is different from the high-order carry signal C _out , the standard position and the output signal S have three logic values of 0, 1, and 2, so different circuits are required to control the generation of the logic 1 signal and the logic 2 signal respectively. Let Y ₁ and Y ₂ be the control signals of the logic 1 signal and the logic 2 signal respectively, then the switch level structure formula is:

In formula (3), means when When it is low level, clk precharges the dynamic node of the first control signal output terminal; the latter item indicates that when is high level, and when the input signal A+B+C _in =1, the charge stored in the dynamic node at the output end of the first control signal is recovered to the process of clk, Y ₁ becomes low level; the formula (4) represents The working process of the circuit is similar to formula (3), except that when the input signal A+B+C _in =2, the charge of the dynamic node at the output end of the second control signal is recovered to clk, and Y ₂ becomes low level. According to formula (3) and formula (4), the circuit diagrams of the first control circuit and the second control circuit as shown in the figure can be obtained. The first control signal _Y1 and the second control signal _Y2 can control the generation of the logic 1 signal and the logic 2 signal, thereby obtaining the home position and output signal S of the ternary adder, and the switch stage structural formula of the home position and signal generating circuit is:

$\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; =</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{{\mathrm{<span\; class="notranslate">\; clk</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; 1.5</span>}}<span\; class="notranslate">\; \#</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; clk</span>}}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; 1.5</span>}}<span\; class="notranslate">\; \#</span>\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; clk</span>}}<span\; class="notranslate">\; *</span>\mathrm{<span\; class="notranslate">\; clk</span>}_{\mathrm{<span\; class="notranslate">\; 1.5</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

In formula (5), The working process of the circuit indicated is: when Y ₁ is low level, due to The amplitude of represents a logic value of 1, so the output of this bit and the output signal S is 1; when Y ₂ is low, due to The amplitude of represents a logic value of 2, and the output signal S is 2 at this time. Indicates that when clk is high, the charge stored on the node of this bit and the signal output terminal is recycled to the process of. It can be seen from formula (3) and formula (4), when clk is high level, is a low level, the node of the first control signal output terminal and the node of the second control signal output terminal are charged to a high level, and when clk is a high level, the node of the first control signal output terminal and the second control signal output In the case that the nodes at the end are all low level, that is, the first control signal Y1 and the second control signal _Y2 will not both be low level, thus ensuring and Will not short circuit.

In this embodiment, each output signal of the word operation module in the first ternary adiabatic domino word operation circuit and each output signal of the word operation module in the second ternary adiabatic domino word operation circuit are converted by the waveform conversion module and then sent to The carry signal generation circuit and the corresponding end of the base and signal generation circuit, the waveform conversion module optimizes the waveform of each output signal of the word operation module, and obtains a slowly changing trapezoidal wave signal suitable for an adiabatic circuit. The slowly changing trapezoidal wave signal and the clock phase The error is extremely small, which can reduce the extra power consumption of the subsequent adiabatic domino circuit due to the phase difference between the signal and the clock during charging and discharging, and ensure that the circuit has correct logic, laying the foundation for the design of a three-valued adiabatic domino complex circuit.

Using Spice software, under TSMC 0.25μm CMOS process parameters, the ternary adiabatic domino addition unit is simulated, and the simulation waveform is shown in Figure 6. The levels corresponding to the logic values 0, 1, and 2 are 0V, 1.25V, and 2.5V respectively; clk1, clk, The amplitudes are 1.25V, 1.25V, 2.5V, 2.5V, and the frequency is 20MHz; the width-length ratio of NMOS is 0.36μm/0.24μm, and the width-length ratio of PMOS is 0.72μm/0.24μm; the load capacitance is 10fF ; A and B are the addend input signal and the augend input signal respectively; S is the standard and output signal, and C _out is the high-order carry signal. Analysis of Figure 6 shows that the logic function of the ternary adiabatic domino addition unit is consistent with the truth table of the ternary adder, which proves that the logic function of the designed ternary adiabatic domino addition unit is correct.

Under the same parameters, the transient energy consumption of the three-value adiabatic domino addition unit and the three-value conventional domino addition unit using DC power supply are compared, and the energy consumption comparison diagram is shown in Figure 7. The concave bottom of the transient energy consumption curve of the ternary adiabatic domino adding unit in Fig. 7 indicates that the energy is recovered to the power clock, thereby effectively reducing the power consumption of the circuit. After analysis, compared with the three-value conventional domino adder unit using DC power supply, the power consumption of the adiabatic three-value adder unit is about 54%, which proves that the designed circuit has obvious low power consumption characteristics. Compared with the ternary addition unit based on the DTCTGAL circuit design, the number of transistors in the adiabatic ternary addition unit is reduced by about 47%, which reduces the cost of the circuit. The ternary adiabatic domino adding unit of the present invention can form a ternary low-power adder with more digits, which promotes the practical process of the ternary digital system.

Claims (5)

1. a Three-value adiabatic domino addition unit, it is characterized in that comprising the first tri-valued, thermal-insulating domino word computing circuit, second tri-valued, thermal-insulating domino word computing circuit, carry signal produces circuit, one's own department or unit and signal generating circuit, first clock signal input terminal, second clock signal input part and the 3rd clock signal input terminal, described carry signal produces circuit and is provided with low order carry signal input part, addend word computing signal input part, summand word computing signal input part, high-order carry signal output end and the high-order carry signal output end of complementation, described one's own department or unit and signal generating circuit are provided with addend word computing signal input part, summand word computing signal input part, low order carry signal input part, complementary low order carry signal input part and one's own department or unit and signal output part, the signal input part of the first described tri-valued, thermal-insulating domino word computing circuit is for accessing addend input signal, the addend word computing signal input part of the signal output part of the first described tri-valued, thermal-insulating domino word computing circuit produces circuit respectively addend word computing signal input part and described one's own department or unit and signal generating circuit with described carry signal is connected, the signal input part of the second described tri-valued, thermal-insulating domino word computing circuit is for accessing summand input signal, the summand word computing signal input part of the signal output part of the second described tri-valued, thermal-insulating domino word computing circuit produces circuit respectively summand word computing signal input part and described one's own department or unit and signal generating circuit with described carry signal is connected, the low order carry signal input part that described carry signal produces circuit is connected with the low order carry signal input part of described one's own department or unit and signal generating circuit, the first described tri-valued, thermal-insulating domino word computing circuit, the second described tri-valued, thermal-insulating domino word computing circuit and described carry signal produce circuit and are connected with the first described clock signal input terminal and described second clock signal input part respectively, described one's own department or unit and signal generating circuit respectively with the first described clock signal input terminal, described second clock signal input part is connected with the 3rd described clock signal input terminal.

2. a kind of Three-value adiabatic domino addition unit according to claim 1, it is characterized in that three addend word computing signals that the addend input signal that output signal is with its signal input part accesses of the signal output part of the first described tri-valued, thermal-insulating domino word computing circuit is corresponding, be respectively the first addend word computing signal when addend is logical zero, the 3rd addend word computing signal when the second addend word computing signal when addend is logical one and addend are logic 2, wherein said carry signal produces the second addend word computing signal described in the access of addend word computing signal input part of circuit and the 3rd described addend word computing signal, the first addend word computing signal described in the access of addend word computing signal input part of described one's own department or unit and signal generating circuit, the second described addend word computing signal and the 3rd described addend word computing signal, three summand word computing signals that the summand input signal that output signal is with its signal input part accesses of the signal output part of the second described tri-valued, thermal-insulating domino word computing circuit is corresponding, be respectively the first summand word computing signal when summand is logical zero, the 3rd summand word computing signal when the second summand word computing signal when summand is logical one and summand are logic 2, wherein said carry signal produces the second summand word computing signal described in the access of summand word computing signal input part of circuit and the 3rd described summand word computing signal, the first summand word computing signal described in the access of summand word computing signal input part of described one's own department or unit and signal generating circuit, the second described summand word computing signal and the 3rd described summand word computing signal.

3. a kind of Three-value adiabatic domino addition unit according to claim 2, it is characterized in that the first described tri-valued, thermal-insulating domino word computing circuit comprises word computing module and waveform transformation module, described word computing module is by the first PMOS, second PMOS, 3rd PMOS, 4th PMOS, 5th PMOS, 6th PMOS, first NMOS tube, second NMOS tube, 3rd NMOS tube, 4th NMOS tube, 5th NMOS tube, 6th NMOS tube and the 7th NMOS tube composition, the grid of the first described NMOS tube and the grid of the 4th described NMOS tube and connect and itself and connect end for signal input part, the drain electrode of the first described NMOS tube, the source electrode of the first described PMOS and the grid of the 3rd described PMOS also connect, the source electrode of the first described NMOS tube is connected with the drain electrode of the second described NMOS tube, the source electrode of the second described PMOS is connected with the drain electrode of the 3rd described PMOS, the source electrode of the 3rd described PMOS, the drain electrode of the 3rd described NMOS tube and the drain electrode of the 7th described NMOS tube also connect, the source electrode of the 4th described PMOS, the drain electrode of the 4th described NMOS tube, the grid of the 6th described PMOS and the grid of the 7th described NMOS tube also connect, the source electrode of the 4th described NMOS tube is connected with the drain electrode of the 5th described NMOS tube, the source electrode of the 5th described PMOS is connected with the drain electrode of the 6th described PMOS, the source electrode of the 6th described PMOS and the drain electrode of the 6th described NMOS tube also connect, the grid of the first described PMOS, the drain electrode of the second described PMOS, the grid of the 4th described PMOS, the drain electrode of the 5th described PMOS, the grid of the second described NMOS tube, the source electrode of the 3rd described NMOS tube, the grid of the 5th described NMOS tube and the source electrode of the 6th described NMOS tube are connected to the first clock signal input terminal, the drain electrode of the first described PMOS, the grid of the second described PMOS, the drain electrode of the 4th described PMOS, the grid of the 5th described PMOS, the source electrode of the second described NMOS tube, the grid of the 3rd described NMOS tube, the source electrode of the 5th described NMOS tube and the grid of the 6th described NMOS tube are connected to second clock signal input part, described waveform transformation module is by the 8th NMOS tube, 9th NMOS tube, tenth NMOS tube, 11 NMOS tube, 12 NMOS tube and the 13 NMOS tube composition, the drain electrode of the 8th described NMOS tube is connected with the drain electrode of the first described NMOS tube, the source electrode of the 8th described NMOS tube is connected with the grid of the 9th described NMOS tube, the drain electrode of the tenth described NMOS tube is connected with the source electrode of the 7th described NMOS tube, the source electrode of the tenth described NMOS tube is connected with the grid of the 11 described NMOS tube, the drain electrode of the 12 described NMOS tube is connected with the source electrode of the 6th described PMOS, the source electrode of the 12 described NMOS tube is connected with the grid of the 13 described NMOS tube, the grid of the 8th described NMOS tube, the grid of the tenth described NMOS tube and the grid of the 12 described NMOS tube are connected to the first clock signal input terminal, the source electrode of the 9th described NMOS tube, the source electrode of the 11 described NMOS tube and the source electrode of the 13 described NMOS tube are connected to second clock signal input part, the drain electrode of the 9th described NMOS tube is the first signal output part, the drain electrode of the 11 described NMOS tube is secondary signal output terminal, the drain electrode of the 13 described NMOS tube is the 3rd signal output part, the circuit structure of the second described tri-valued, thermal-insulating domino word computing circuit is identical with the first described tri-valued, thermal-insulating domino word computing circuit, both differences are the signal input part access addend input signal of the first described tri-valued, thermal-insulating domino word computing circuit, the first addend word computing signal when first signal output part output addend of the first described tri-valued, thermal-insulating domino word computing circuit is logical zero, the second addend word computing signal when the secondary signal output terminal output addend of the first described tri-valued, thermal-insulating domino word computing circuit is logical one, the 3rd addend word computing signal when 3rd signal output part output addend of the first described tri-valued, thermal-insulating domino word computing circuit is logic 2, the signal input part access summand input signal of the second described tri-valued, thermal-insulating domino word computing circuit, the first summand word computing signal when first signal output part output summand of the second described tri-valued, thermal-insulating domino word computing circuit is logical zero, the second summand word computing signal when the secondary signal output terminal output summand of the second described tri-valued, thermal-insulating domino word computing circuit is logical one, the 3rd summand word computing signal when 3rd signal output part output summand of the second described tri-valued, thermal-insulating domino word computing circuit is logic 2.

4. a kind of Three-value adiabatic domino addition unit according to claim 3, it is characterized in that described carry signal produces circuit by the 7th PMOS, 8th PMOS, 14 NMOS tube, 15 NMOS tube, 16 NMOS tube, 17 NMOS tube, 18 NMOS tube, 19 NMOS tube, 20 NMOS tube, 21 NMOS tube, 22 NMOS tube, 23 NMOS tube, 24 NMOS tube, 25 NMOS tube and the 26 NMOS tube composition, the source electrode of the 7th described PMOS, the grid of the 8th described PMOS, the drain electrode of the 14 described NMOS tube, the drain electrode of the 21 described NMOS tube, the drain electrode of the 23 described NMOS tube and the drain electrode of the 24 described NMOS tube are connected to the high-order carry signal output end of complementation that described carry signal produces circuit, the source electrode of the 14 described NMOS tube, the drain electrode of the 15 described NMOS tube, the drain electrode of the 17 described NMOS tube is connected with the drain electrode of the 18 described NMOS tube, the source electrode of the 15 described NMOS tube, the drain electrode of the 16 described NMOS tube, the source electrode of the 17 described NMOS tube, the source electrode of the 19 described NMOS tube, the source electrode of the 20 described NMOS tube, the source electrode of the 22 described NMOS tube is connected with the source electrode of the 25 described NMOS tube, the source electrode of the 18 described NMOS tube is connected with the drain electrode of the 19 described NMOS tube, the source electrode of the 21 described NMOS tube is connected with the drain electrode of the 20 described NMOS tube, the source electrode of the 23 described NMOS tube is connected with the drain electrode of the 22 described NMOS tube, the source electrode of the 24 described NMOS tube is connected with the drain electrode of the 25 described NMOS tube, the source electrode of the 8th described PMOS and the drain electrode of the 26 described NMOS tube are connected to the high-order carry signal output end that described carry signal produces circuit, the grid of the 14 described NMOS tube is the low order carry signal input part that described carry signal produces circuit, the grid of the 18 described NMOS tube and the grid of the 20 described NMOS tube all access the second addend word computing signal when addend is logical one, the grid of the 15 described NMOS tube, the grid of the 23 described NMOS tube and the grid of the 24 described NMOS tube all access the 3rd addend word computing signal when addend is logic 2, the grid of the 19 described NMOS tube and the grid of the 22 described NMOS tube all access the second summand word computing signal when summand is logical one, the grid of the 17 described NMOS tube, the grid of the 21 described NMOS tube and the grid of the 25 described NMOS tube all access the 3rd summand word computing signal when summand is logic 2, the drain electrode of the 7th described PMOS, the source electrode of the 16 described NMOS tube and the grid of the 26 described NMOS tube are connected to the first clock signal input terminal, the grid of the 7th described PMOS, the grid of the 16 described NMOS tube, the drain electrode of the 8th described PMOS and the source electrode of the 26 described NMOS tube are connected to second clock signal input part.

5. a kind of Three-value adiabatic domino addition unit according to claim 4, it is characterized in that described one's own department or unit and signal generating circuit comprise the first control circuit produced for steering logic 1, the second control circuit produced for steering logic 2 and one's own department or unit and signal output apparatus, described first control circuit is by the 9th PMOS, 27 NMOS tube, 28 NMOS tube, 29 NMOS tube, 30 NMOS tube, 31 NMOS tube, 32 NMOS tube, 33 NMOS tube, 34 NMOS tube, 35 NMOS tube, 36 NMOS tube, 37 NMOS tube, 38 NMOS tube, 39 NMOS tube, 40 NMOS tube and the 41 NMOS tube composition, the source electrode of the 9th described PMOS, the drain electrode of the 27 described NMOS tube, the drain electrode of the 30 described NMOS tube, the drain electrode of the 32 described NMOS tube, the drain electrode of the 34 described NMOS tube, the drain electrode of the 37 described NMOS tube and the drain electrode of the 39 described NMOS tube are connected to the first control signal output terminal, the control signal of the first described control signal output terminal output logic 1 signal, the source electrode of the 27 described NMOS tube is connected with the drain electrode of the 28 described NMOS tube, the source electrode of the 28 described NMOS tube, the drain electrode of the 29 described NMOS tube, the source electrode of the 31 described NMOS tube is connected with the source electrode of the 33 described NMOS tube, the source electrode of the 29 described NMOS tube, the source electrode of the 36 described NMOS tube is connected with the drain electrode of the 41 described NMOS tube, the source electrode of the 30 described NMOS tube is connected with the drain electrode of the 31 described NMOS tube, the source electrode of the 32 described NMOS tube is connected with the drain electrode of the 33 described NMOS tube, the source electrode of the 34 described NMOS tube is connected with the drain electrode of the 35 described NMOS tube, the source electrode of the 37 described NMOS tube is connected with the drain electrode of the 38 described NMOS tube, the source electrode of the 39 described NMOS tube is connected with the drain electrode of the 40 described NMOS tube, the source electrode of the 35 described NMOS tube, the drain electrode of the 36 described NMOS tube, the source electrode of the 38 described NMOS tube is connected with the source electrode of the 40 described NMOS tube, the grid of the 27 described NMOS tube and the grid of the 34 described NMOS tube all access the first addend word computing signal when addend is logical zero, the grid of the 30 described NMOS tube and the grid of the 37 described NMOS tube all access the second addend word computing signal when addend is logical one, the grid of the 32 described NMOS tube and the grid of the 39 described NMOS tube all access the 3rd addend word computing signal when addend is logic 2, the grid of the 28 described NMOS tube and the grid of the 40 described NMOS tube all access the second summand word computing signal when summand is logical one, the grid of the 31 described NMOS tube and the grid of the 35 described NMOS tube all access the first summand word computing signal when summand is logical zero, the grid of the 33 described NMOS tube and the grid of the 38 described NMOS tube all access the 3rd summand word computing signal when summand is logic 2, described second control circuit is by the tenth PMOS, 42 NMOS tube, 43 NMOS tube, 44 NMOS tube, 45 NMOS tube, 46 NMOS tube, 47 NMOS tube, 48 NMOS tube, 49 NMOS tube, 50 NMOS tube, 51 NMOS tube, 52 NMOS tube, 53 NMOS tube, 54 NMOS tube, 55 NMOS tube and the 56 NMOS tube composition, the source electrode of the tenth described PMOS, the drain electrode of the 42 described NMOS tube, the drain electrode of the 46 described NMOS tube, the drain electrode of the 48 described NMOS tube, the drain electrode of the 50 described NMOS tube, the drain electrode of the 53 described NMOS tube and the drain electrode of the 55 described NMOS tube are connected to the second control signal output terminal, the control signal of the second described control signal output terminal output logic 2 signal, the source electrode of the 42 described NMOS tube is connected with the drain electrode of the 43 described NMOS tube, the source electrode of the 43 described NMOS tube, the drain electrode of the 44 described NMOS tube, the source electrode of the 47 described NMOS tube is connected with the source electrode of the 49 described NMOS tube, the source electrode of the 44 described NMOS tube, the drain electrode of the 45 described NMOS tube is connected with the source electrode of the 52 described NMOS tube, the source electrode of the 46 described NMOS tube is connected with the drain electrode of the 47 described NMOS tube, the source electrode of the 48 described NMOS tube is connected with the drain electrode of the 49 described NMOS tube, the source electrode of the 50 described NMOS tube is connected with the drain electrode of the 51 described NMOS tube, the source electrode of the 53 described NMOS tube is connected with the drain electrode of the 54 described NMOS tube, the source electrode of the 55 described NMOS tube is connected with the drain electrode of the 56 described NMOS tube, the source electrode of the 51 described NMOS tube, the drain electrode of the 52 described NMOS tube, the source electrode of the 54 described NMOS tube is connected with the source electrode of the 56 described NMOS tube, the grid of the 42 described NMOS tube and the grid of the 50 described NMOS tube all access the first addend word computing signal when addend is logical zero, the grid of the 46 described NMOS tube and the grid of the 53 described NMOS tube all access the second addend word computing signal when addend is logical one, the grid of the 48 described NMOS tube and the grid of the 55 described NMOS tube all access the 3rd addend word computing signal when addend is logic 2, the grid of the 43 described NMOS tube and the grid of the 56 described NMOS tube all access the second summand word computing signal when summand is logical one, the grid of the 47 described NMOS tube and the grid of the 51 described NMOS tube all access the first summand word computing signal when summand is logical zero, the grid of the 49 described NMOS tube and the grid of the 54 described NMOS tube all access the 3rd summand word computing signal when summand is logic 2, described one's own department or unit and signal output apparatus are by the 11 PMOS, 12 PMOS and the 57 NMOS tube composition, the grid of the 11 described PMOS is connected with the first described control signal output terminal, the grid of the 12 described PMOS is connected with the second described control signal output terminal, the source electrode of the 11 described PMOS, the source electrode of the 12 described PMOS and the drain electrode of the 57 described NMOS tube and connect and itself and connect one's own department or unit and signal output part that end is described one's own department or unit and signal generating circuit, the grid of the 9th described PMOS, the grid of the tenth described PMOS, the drain electrode of the 12 described PMOS, the grid of the 41 described NMOS tube, the grid of the 45 described NMOS tube and the source electrode of the 57 described NMOS tube are connected to second clock signal input part, the drain electrode of the 9th described PMOS, the drain electrode of the tenth described PMOS, the source electrode of 41 described NMOS tube, the source electrode of the 45 described NMOS tube and the grid of the 57 described NMOS tube are connected to the first clock signal input terminal, the drain electrode of the 11 described PMOS is connected with the 3rd clock signal input terminal, the grid of the 29 described NMOS tube and the grid of the 44 described NMOS tube and connect and itself and connect the complementary low order carry signal input part that end is described one's own department or unit and signal generating circuit, the grid of the 36 described NMOS tube and the grid of the 52 described NMOS tube and connect and itself and connect the low order carry signal input part that end is described one's own department or unit and signal generating circuit.