CN102832928A - Three-value adiabatic domino addition unit - Google Patents

Abstract

The invention discloses a ternary adiabatic domino addition unit, which comprises a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generation circuit and a standard sum signal generation circuit, and a first ternary adiabatic domino word operation circuit. The domino word operation circuit is respectively connected with the carry signal generating circuit and the standard and signal generating circuit, and the second ternary adiabatic domino word operation circuit is connected with the carry signal generating circuit and the standard and signal generating circuit respectively, and the low-order carry signal input of the carry signal generating circuit is The terminal is connected to the low-order carry signal input terminal of the local and signal generating circuit; the advantage is that under the premise of ensuring correct logic function, the structure is simple, and compared with the three-valued conventional domino adder unit using DC power supply, its power consumption is saved. About 54%, compared with the ternary addition unit based on the DTCTGAL circuit design, the number of transistors is reduced by about 47%.

Description

A kind of tri-valued, thermal-insulating domino adder unit

Technical field

The present invention relates to a kind of three value adder units, especially relate to a kind of tri-valued, thermal-insulating domino adder unit.

Background technology

The current digit Circuits System mainly adopts two-valued function to realize, the logical value that its single holding wire can transmit has only 0 and 1 two kind, and the room and time utilance of circuit is lower.Adopt multi valued logic can significantly reduce circuit input variable number, improve the amount of information that every line carries, thereby reduce area of chip, strengthen data-handling capacity.Therefore domino circuit combines multi valued logic because its advantage on circuit area and speed is widely used in the various high performance circuits with domino circuit, can further reduce circuit area, improves the information density of circuit, reduces circuit cost.

Add operation is the most basic arithmetical operation, and subtraction, multiplication, division, address computation etc. can realize with addition in theory.Therefore; Adder be the critical component of digital system also be to use one of parts the most widely; The power consumption of adder is determining the power consumption of whole digital system to a great extent, and adder unit is as the main modular that constitutes adder, and its power consumption has determined the power consumption of adder again.At present traditional adder unit has caused great waste because electric charge is disposable consuming from the power supply to ground; And the abundant charge stored in the recovery circuit node of the adiabatic adder that adopts the alternating-current pulse power supply effectively reduces the power consumption of circuit.Given this, multi valued logic, adiabatic logic and domino circuit are applied in the design of adder unit and have realistic meaning.

Summary of the invention

Technical problem to be solved by this invention provides and is a kind ofly guaranteeing to have under the prerequisite of correct logic functions the tri-valued, thermal-insulating domino adder unit that power consumption is lower.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of tri-valued, thermal-insulating domino adder unit; Comprise the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; Carry signal produces circuit; One's own department or unit and signal generating circuit; First clock signal input terminal; Second clock signal input part and the 3rd clock signal input terminal; Described carry signal produces circuit and is provided with low level carry signal input; Addend literal computing signal input part; Summand literal computing signal input part; High-order carry signal output and complementary high-order carry signal output; Described one's own department or unit and signal generating circuit are provided with addend literal computing signal input part; Summand literal computing signal input part; Low level carry signal input; Complementary low level carry signal input and one's own department or unit and signal output part; The signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit is used to insert the addend input signal; The signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit produces the addend literal computing signal input part of circuit with described carry signal respectively and the addend literal computing signal input part of described one's own department or unit and signal generating circuit is connected; The signal input part of the described second tri-valued, thermal-insulating domino literal computing circuit is used to insert the summand input signal; The signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit produces the summand literal computing signal input part of circuit with described carry signal respectively and the summand literal computing signal input part of described one's own department or unit and signal generating circuit is connected; The low level carry signal input that described carry signal produces circuit is connected with the low level carry signal input of described one's own department or unit and signal generating circuit; The described first tri-valued, thermal-insulating domino literal computing circuit; The described second tri-valued, thermal-insulating domino literal computing circuit produces circuit with described carry signal and is connected with described second clock signal input part with described first clock signal input terminal respectively, described one's own department or unit and signal generating circuit respectively with described first clock signal input terminal; Described second clock signal input part is connected with described the 3rd clock signal input terminal.

The output signal of the signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit is three the corresponding addend literal computing signals of addend input signal that insert with its signal input part; Be respectively the three addend literal computing signal of first addend literal computing signal, second addend literal computing signal when addend be logical one and the addend of addend when being logical zero when being logic 2; The addend literal computing signal input part that wherein said carry signal produces circuit inserts described second addend literal computing signal and described the 3rd addend literal computing signal; The addend literal computing signal input part of described one's own department or unit and signal generating circuit inserts the described first addend literal computing signal, the described second addend literal computing signal and described the 3rd addend literal computing signal; The output signal of the signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit is three the corresponding summand literal computing signals of summand input signal that insert with its signal input part; Be respectively the three summand literal computing signal of first summand literal computing signal, second summand literal computing signal when summand be logical one and the summand of summand when being logical zero when being logic 2; The summand literal computing signal input part that wherein said carry signal produces circuit inserts described second summand literal computing signal and described the 3rd summand literal computing signal, and the summand literal computing signal input part of described one's own department or unit and signal generating circuit inserts the described first summand literal computing signal, the described second summand literal computing signal and described the 3rd summand literal computing signal.

The described first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module; Described literal computing module is managed by a PMOS; The 2nd PMOS pipe; The 3rd PMOS pipe; The 4th PMOS pipe; The 5th PMOS pipe; The 6th PMOS pipe; The one NMOS pipe; The 2nd NMOS pipe; The 3rd NMOS pipe; The 4th NMOS pipe; The 5th NMOS pipe; The 6th NMOS pipe and the 7th NMOS pipe are formed; The grid of the grid of described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end and be signal input part; The drain electrode of described NMOS pipe; The grid of the source electrode of described PMOS pipe and described the 3rd PMOS pipe also connects; The source electrode of described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe; The source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe; The source electrode of described the 3rd PMOS pipe; The drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th PMOS pipe; The drain electrode of described the 4th NMOS pipe; The grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe; The source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe; The drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects; The grid of described PMOS pipe; The drain electrode of described the 2nd PMOS pipe; The grid of described the 4th PMOS pipe; The drain electrode of described the 5th PMOS pipe; The grid of described the 2nd NMOS pipe; The source electrode of described the 3rd NMOS pipe; The source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to first clock signal input terminal; The drain electrode of described PMOS pipe; The grid of described the 2nd PMOS pipe; The drain electrode of described the 4th PMOS pipe; The grid of described the 5th PMOS pipe; The source electrode of described the 2nd NMOS pipe; The grid of described the 3rd NMOS pipe; The grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part; Described waveform transformation module is managed by the 8th NMOS; The 9th NMOS pipe; The tenth NMOS pipe; The 11 NMOS pipe; The 12 NMOS pipe and the 13 NMOS pipe are formed; The drain electrode of described the 8th NMOS pipe is connected with the drain electrode of described NMOS pipe; The source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe; The drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe; The source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe; The drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe; The source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe; The grid of described the 8th NMOS pipe; The grid of the grid of described the tenth NMOS pipe and described the 12 NMOS pipe is connected to first clock signal input terminal; The source electrode of described the 9th NMOS pipe; The source electrode of the source electrode of described the 11 NMOS pipe and described the 13 NMOS pipe is connected to the second clock signal input part; The drain electrode of described the 9th NMOS pipe is first signal output part; The drain electrode of described the 11 NMOS pipe is the secondary signal output; The drain electrode of described the 13 NMOS pipe is the 3rd signal output part; The circuit structure of the described second tri-valued, thermal-insulating domino literal computing circuit is identical with the described first tri-valued, thermal-insulating domino literal computing circuit; Both differences are that the signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit inserts the addend input signal; The first addend literal computing signal when first signal output part output addend of the described first tri-valued, thermal-insulating domino literal computing circuit is logical zero; The second addend literal computing signal when the secondary signal output output addend of the described first tri-valued, thermal-insulating domino literal computing circuit is logical one; The 3rd addend literal computing signal when the 3rd signal output part output addend of the described first tri-valued, thermal-insulating domino literal computing circuit is logic 2; The signal input part of the described second tri-valued, thermal-insulating domino literal computing circuit inserts the summand input signal; The first summand literal computing signal when first signal output part output summand of the described second tri-valued, thermal-insulating domino literal computing circuit is logical zero; The second summand literal computing signal when the secondary signal output output summand of the described second tri-valued, thermal-insulating domino literal computing circuit is logical one, the 3rd summand literal computing signal when the 3rd signal output part output summand of the described second tri-valued, thermal-insulating domino literal computing circuit is logic 2.

Described carry signal produces circuit and is managed by the 7th PMOS; The 8th PMOS pipe; The 14 NMOS pipe; The 15 NMOS pipe; The 16 NMOS pipe; The 17 NMOS pipe; The 18 NMOS pipe; The 19 NMOS pipe; The 20 NMOS pipe; The 21 NMOS pipe; The 22 NMOS pipe; The 23 NMOS pipe; The 24 NMOS pipe; The 25 NMOS pipe and the 26 NMOS pipe are formed; The source electrode of described the 7th PMOS pipe; The grid of described the 8th PMOS pipe; The drain electrode of described the 14 NMOS pipe; The drain electrode of described the 21 NMOS pipe; The drain electrode of the drain electrode of described the 23 NMOS pipe and described the 24 NMOS pipe is connected to the complementary high-order carry signal output that described carry signal produces circuit; The source electrode of described the 14 NMOS pipe; The drain electrode of described the 15 NMOS pipe; The drain electrode of described the 17 NMOS pipe is connected with the drain electrode of described the 18 NMOS pipe; The source electrode of described the 15 NMOS pipe; The drain electrode of described the 16 NMOS pipe; The source electrode of described the 17 NMOS pipe; The source electrode of described the 19 NMOS pipe; The source electrode of described the 20 NMOS pipe; The source electrode of described the 22 NMOS pipe is connected with the source electrode of described the 25 NMOS pipe; The source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe; The source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 20 NMOS pipe; The source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe; The source electrode of described the 24 NMOS pipe is connected with the drain electrode of described the 25 NMOS pipe; The drain electrode of the source electrode of described the 8th PMOS pipe and described the 26 NMOS pipe is connected to the high-order carry signal output that described carry signal produces circuit; The grid of described the 14 NMOS pipe is the low level carry signal input that described carry signal produces circuit; The second addend literal computing signal the when grid of the grid of described the 18 NMOS pipe and described the 20 NMOS pipe all inserts addend and is logical one; The grid of described the 15 NMOS pipe; The 3rd addend literal computing signal the when grid of the grid of described the 23 NMOS pipe and described the 24 NMOS pipe all inserts addend and is logic 2; The second summand literal computing signal the when grid of the grid of described the 19 NMOS pipe and described the 22 NMOS pipe all inserts summand and is logical one; The grid of described the 17 NMOS pipe; The 3rd summand literal computing signal the when grid of the grid of described the 21 NMOS pipe and described the 25 NMOS pipe all inserts summand and is logic 2; The drain electrode of described the 7th PMOS pipe; The grid of the source electrode of described the 16 NMOS pipe and described the 26 NMOS pipe is connected to first clock signal input terminal, the grid of described the 7th PMOS pipe; The grid of described the 16 NMOS pipe; The source electrode of the drain electrode of described the 8th PMOS pipe and described the 26 NMOS pipe is connected to the second clock signal input part.

Described one's own department or unit and signal generating circuit comprise the first control circuit that is used for control logic 1 generation; Be used for second control circuit and one's own department or unit and signal output apparatus that control logic 2 produces; Described first control circuit is managed by the 9th PMOS; The 27 NMOS pipe; The 28 NMOS pipe; The 29 NMOS pipe; The 30 NMOS pipe; The 31 NMOS pipe; The 32 NMOS pipe; The 33 NMOS pipe; The 34 NMOS pipe; The 35 NMOS pipe; The 36 NMOS pipe; The 37 NMOS pipe; The 38 NMOS pipe; The 39 NMOS pipe; The 40 NMOS pipe and the 41 NMOS pipe are formed; The source electrode of described the 9th PMOS pipe; The drain electrode of described the 27 NMOS pipe; The drain electrode of described the 30 NMOS pipe; The drain electrode of described the 32 NMOS pipe; The drain electrode of described the 34 NMOS pipe; The drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe is connected to first control signal output ends; The control signal of the described first control signal output ends output logic, 1 signal; The source electrode of described the 27 NMOS pipe is connected with the drain electrode of described the 28 NMOS pipe; The source electrode of described the 28 NMOS pipe; The drain electrode of described the 29 NMOS pipe; The source electrode of described the 31 NMOS pipe is connected with the source electrode of described the 33 NMOS pipe; The source electrode of described the 29 NMOS pipe; The source electrode of described the 36 NMOS pipe is connected with the drain electrode of described the 41 NMOS pipe; The source electrode of described the 30 NMOS pipe is connected with the drain electrode of described the 31 NMOS pipe; The source electrode of described the 32 NMOS pipe is connected with the drain electrode of described the 33 NMOS pipe; The source electrode of described the 34 NMOS pipe is connected with the drain electrode of described the 35 NMOS pipe; The source electrode of described the 37 NMOS pipe is connected with the drain electrode of described the 38 NMOS pipe; The source electrode of described the 39 NMOS pipe is connected with the drain electrode of described the 40 NMOS pipe; The source electrode of described the 35 NMOS pipe; The drain electrode of described the 36 NMOS pipe; The source electrode of described the 38 NMOS pipe is connected with the source electrode of described the 40 NMOS pipe; The first addend literal computing signal the when grid of the grid of described the 27 NMOS pipe and described the 34 NMOS pipe all inserts addend and is logical zero; The second addend literal computing signal the when grid of the grid of described the 30 NMOS pipe and described the 37 NMOS pipe all inserts addend and is logical one; The 3rd addend literal computing signal the when grid of the grid of described the 32 NMOS pipe and described the 39 NMOS pipe all inserts addend and is logic 2; The second summand literal computing signal the when grid of the grid of described the 28 NMOS pipe and described the 40 NMOS pipe all inserts summand and is logical one; The first summand literal computing signal the when grid of the grid of described the 31 NMOS pipe and described the 35 NMOS pipe all inserts summand and is logical zero; The 3rd summand literal computing signal the when grid of the grid of described the 33 NMOS pipe and described the 38 NMOS pipe all inserts summand and is logic 2; Described second control circuit is managed by the tenth PMOS; The 42 NMOS pipe; The 43 NMOS pipe; The 44 NMOS pipe; The 45 NMOS pipe; The 46 NMOS pipe; The 47 NMOS pipe; The 48 NMOS pipe; The 49 NMOS pipe; The 50 NMOS pipe; The 51 NMOS pipe; The 52 NMOS pipe; The 53 NMOS pipe; The 54 NMOS pipe; The 55 NMOS pipe and the 56 NMOS pipe are formed; The source electrode of described the tenth PMOS pipe; The drain electrode of described the 42 NMOS pipe; The drain electrode of described the 46 NMOS pipe; The drain electrode of described the 48 NMOS pipe; The drain electrode of described the 50 NMOS pipe; The drain electrode of the drain electrode of described the 53 NMOS pipe and described the 55 NMOS pipe is connected to second control signal output ends; The control signal of the described second control signal output ends output logic, 2 signals; The source electrode of described the 42 NMOS pipe is connected with the drain electrode of described the 43 NMOS pipe; The source electrode of described the 43 NMOS pipe; The drain electrode of described the 44 NMOS pipe; The source electrode of described the 47 NMOS pipe is connected with the source electrode of described the 49 NMOS pipe; The source electrode of described the 44 NMOS pipe; The drain electrode of described the 45 NMOS pipe is connected with the source electrode of described the 52 NMOS pipe; The source electrode of described the 46 NMOS pipe is connected with the drain electrode of described the 47 NMOS pipe; The source electrode of described the 48 NMOS pipe is connected with the drain electrode of described the 49 NMOS pipe; The source electrode of described the 50 NMOS pipe is connected with the drain electrode of described the 51 NMOS pipe; The source electrode of described the 53 NMOS pipe is connected with the drain electrode of described the 54 NMOS pipe; The source electrode of described the 55 NMOS pipe is connected with the drain electrode of described the 56 NMOS pipe; The source electrode of described the 51 NMOS pipe; The drain electrode of described the 52 NMOS pipe; The source electrode of described the 54 NMOS pipe is connected with the source electrode of described the 56 NMOS pipe; The first addend literal computing signal the when grid of the grid of described the 42 NMOS pipe and described the 50 NMOS pipe all inserts addend and is logical zero; The second addend literal computing signal the when grid that the grid of described the 46 NMOS pipe and described the 53 NMOS manage all inserts addend and is logical one; The 3rd addend literal computing signal the when grid of the grid of described the 48 NMOS pipe and described the 55 NMOS pipe all inserts addend and is logic 2; The second summand literal computing signal the when grid of the grid of described the 43 NMOS pipe and described the 56 NMOS pipe all inserts summand and is logical one; The first summand literal computing signal the when grid of the grid of described the 47 NMOS pipe and described the 51 NMOS pipe all inserts summand and is logical zero; The 3rd summand literal computing signal the when grid that the grid of described the 49 NMOS pipe and described the 54 NMOS manage all inserts summand and is logic 2; Described one's own department or unit and signal output apparatus are managed by the 11 PMOS; The 12 PMOS pipe and the 57 NMOS pipe are formed; The grid of described the 11 PMOS pipe is connected with described first control signal output ends; The grid of described the 12 PMOS pipe is connected with described second control signal output ends; The source electrode of described the 11 PMOS pipe; The drain electrode of the source electrode of described the 12 PMOS pipe and described the 57 NMOS pipe and connect and itself and connect one's own department or unit and the signal output part of end for described one's own department or unit and signal generating circuit; The grid of described the 9th PMOS pipe; The grid of described the tenth PMOS pipe; The drain electrode of described the 12 PMOS pipe; The grid of described the 41 NMOS pipe; The source electrode of the grid of described the 45 NMOS pipe and described the 57 NMOS pipe is connected to the second clock signal input part; The drain electrode of described the 9th PMOS pipe; The drain electrode of described the tenth PMOS pipe; The source electrode of described 41 NMOS pipe; The grid of the source electrode of described the 45 NMOS pipe and described the 57 NMOS pipe is connected to first clock signal input terminal; The drain electrode of described the 11 PMOS pipe is connected with the 3rd clock signal input terminal; The grid of the grid of described the 29 NMOS pipe and described the 44 NMOS pipe and connect and itself and connect the complementary low level carry signal input of end for described one's own department or unit and signal generating circuit, the grid of the grid of described the 36 NMOS pipe and described the 52 NMOS pipe and connect and itself and connect the low level carry signal input that end is described one's own department or unit and signal generating circuit.

Compared with prior art; The invention has the advantages that through with multi valued logic; Adiabatic logic and domino circuit are applied in the design of adder unit; Go out to meet the tri-valued, thermal-insulating domino adder unit of correct logic functions in conjunction with the switching signal Design Theory; This adder unit is by the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; Carry signal produces circuit and one's own department or unit and signal generating circuit and forms; Logic function is correct; And it is simple in structure; Compare with the conventional domino adder unit of three values that adopts DC power supply; These thermal insulation three value adder unit Power Cutbacks about 54%; Compare with three value adder units based on the DTCTGAL circuit design, its number of transistors reduces about 47%.

Description of drawings

Fig. 1 (a) is circuit theory diagrams of the present invention;

Fig. 1 (b) is circuit symbol figure of the present invention;

Fig. 2 (a) is the circuit diagram of literal computing module of the first tri-valued, thermal-insulating domino literal computing circuit of embodiment;

Fig. 2 (b) is the circuit diagram of waveform transformation module of the first tri-valued, thermal-insulating domino literal computing circuit of embodiment;

Fig. 2 (c) is the circuit symbol figure of the first tri-valued, thermal-insulating domino literal computing circuit of embodiment;

Fig. 3 (a) is the circuit diagram that the carry signal of embodiment produces circuit;

Fig. 3 (b) is the circuit symbol figure that the carry signal of embodiment produces circuit;

Fig. 4 (a) is the circuit diagram of first control circuit of one's own department or unit and the signal generating circuit of embodiment;

Fig. 4 (b) is the circuit diagram of second control circuit of one's own department or unit and the signal generating circuit of embodiment;

Fig. 4 (c) is one's own department or unit and the one's own department or unit of signal generating circuit and the circuit diagram of signal output apparatus of embodiment;

Fig. 4 (d) is the one's own department or unit of embodiment and the circuit symbol figure of signal generating circuit;

Fig. 5 is the oscillogram of three clock signals of embodiment;

Fig. 6 is analog waveform figure of the present invention;

Fig. 7 is the transient state energy consumption comparison diagram of tri-valued, thermal-insulating domino adder unit of the present invention and the conventional domino adder unit of three values.

Embodiment

Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.

Shown in Fig. 1 (a) and Fig. 1 (b); A kind of tri-valued, thermal-insulating domino adder unit; Comprise the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; Carry signal produces circuit; One's own department or unit and signal generating circuit; First clock signal input terminal; Second clock signal input part and the 3rd clock signal input terminal; Carry signal produces circuit and is provided with low level carry signal input; Addend literal computing signal input part; Summand literal computing signal input part; High-order carry signal output and complementary high-order carry signal output; One's own department or unit and signal generating circuit are provided with addend literal computing signal input part; Summand literal computing signal input part; Low level carry signal input; Complementary low level carry signal input and one's own department or unit and signal output part; The signal input part of the first tri-valued, thermal-insulating domino literal computing circuit is used to insert the addend input signal; The signal output part of the first tri-valued, thermal-insulating domino literal computing circuit produces the addend literal computing signal input part of circuit with carry signal respectively and the addend literal computing signal input part of one's own department or unit and signal generating circuit is connected; The signal input part of the second tri-valued, thermal-insulating domino literal computing circuit is used to insert the summand input signal; The signal output part of the second tri-valued, thermal-insulating domino literal computing circuit produces the summand literal computing signal input part of circuit with carry signal respectively and the summand literal computing signal input part of one's own department or unit and signal generating circuit is connected; The low level carry signal input that carry signal produces circuit is connected with the low level carry signal input of one's own department or unit and signal generating circuit; The first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit and carry signal produce circuit and are connected with the second clock signal input part with first clock signal input terminal respectively, one's own department or unit and signal generating circuit respectively with first clock signal input terminal; The second clock signal input part is connected with the 3rd clock signal input terminal.The output signal of the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is three the corresponding addend literal computing signals of addend input signal that insert with its signal input part; Be respectively the first addend literal computing signal of addend when being logical zero; The 3rd addend literal computing signal when second addend literal computing signal when addend is logical one and addend are logic 2; Wherein the addend literal computing signal input part of carry signal generation circuit inserts the second addend literal computing signal and the 3rd addend literal computing signal; The addend literal computing signal input part of one's own department or unit and signal generating circuit inserts the first addend literal computing signal; The second addend literal computing signal and the 3rd addend literal computing signal; The output signal of the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is three the corresponding summand literal computing signals of summand input signal that insert with its signal input part; Be respectively the first summand literal computing signal of summand when being logical zero; The 3rd summand literal computing signal when second summand literal computing signal when summand is logical one and summand are logic 2; Wherein the summand literal computing signal input part of carry signal generation circuit inserts the second summand literal computing signal and the 3rd summand literal computing signal, and the summand literal computing signal input part of one's own department or unit and signal generating circuit inserts the first summand literal computing signal; The second summand literal computing signal and the 3rd summand literal computing signal.

Design principle of the present invention is: insertion switch signal theory at first; Insertion switch variable and signal variable reach corresponding switch algebraically and signal algebraically with it in MULTI-VALUED LOGIC CIRCUIT; For the design of multivalued circuit provides reliable theoretical foundation; Can know that by the switching signal theory voltage switch in the cmos circuit can be used for controlling to the ground short circuit of output voltage signal or connects the source short circuit, and can directly control transmission output voltage signal.Three value adder truth tables are as shown in table 1, wherein ABe the addend input signal, BBe the summand input signal, C _InBe low level carry signal from low level, SBe one's own department or unit and output signal, C _OutFor flowing to high-order high-order carry signal.

Table 1 three value adder truth tables

Owing to generally have only NMOS pipe or PMOS pipe in the evaluation circuit of domino circuit; Can't directly differentiate the logical one signal; So we at first need obtain tri-valued, thermal-insulating domino literal computing circuit, the input signal that makes three value adders is at first through exporting the signal that obtains needs behind the tri-valued, thermal-insulating domino literal computing circuit.If the addend input signal is A, the summand input signal is B, then through the output signal behind the tri-valued, thermal-insulating domino literal computing circuit does ⁰A ⁰, ¹A ¹, ²A ², ⁰B ⁰, ¹B ¹With ²B ²Ternary unit adiabatic method Duominuojia three clock signal input terminal (a first clock signal input terminal, a second clock signal input terminal and a third clock signal input terminal) respectively connected to a clock signal, three clock signals can be denoted as first clock signal clk, a second clock signal and the third clock signal

wherein the first clock signal clk, the second clock signal

amplitude level corresponding to logic 2, the third clock signal

amplitude level corresponding to logic 1, second clock signal

and the third clock signal

in phase with the first clock signal clk and the first two reverse direction (i.e., the phase difference of 180 degrees), then the switching signal theory and the three values of a truth table of the adder, the carry signal obtained and a generating circuit and a standard signal generating circuit, to obtain a three-value unit adiabatic Duominuojia circuit diagram method.

Embodiment: a kind of tri-valued, thermal-insulating domino adder unit comprises that the first tri-valued, thermal-insulating domino literal computing circuit, the second tri-valued, thermal-insulating domino literal computing circuit, carry signal produce circuit and one's own department or unit and signal generating circuit; The first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module.Shown in Fig. 2 (a); The literal computing module is by PMOS pipe P1; The 2nd PMOS manages P2; The 3rd PMOS manages P3; The 4th PMOS manages P4; The 5th PMOS manages P5; The 6th PMOS manages P6; The one NMOS manages N1; The 2nd NMOS manages N2; The 3rd NMOS manages N3; The 4th NMOS manages N4; The 5th NMOS manages N5; The 6th NMOS pipe N6 and the 7th NMOS pipe N7 form; The grid of the grid of the one NMOS pipe N1 and the 4th NMOS pipe N4 and connect and itself and connect end and be signal input part; The drain electrode of the one NMOS pipe N1; The grid of the source electrode of the one PMOS pipe P1 and the 3rd PMOS pipe P3 also connects; The source electrode of the one NMOS pipe N1 is connected with the drain electrode of the 2nd NMOS pipe N2; The source electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 3rd PMOS pipe P3; The source electrode of the 3rd PMOS pipe P3; The drain electrode of the drain electrode of the 3rd NMOS pipe N3 and the 7th NMOS pipe N7 also connects; The source electrode of the 4th PMOS pipe P4; The drain electrode of the 4th NMOS pipe N4; The grid of the grid of the 6th PMOS pipe P6 and the 7th NMOS pipe N7 also connects; The source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5; The source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 6th PMOS pipe P6; The drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe N6 also connects; The grid of the one PMOS pipe P1; The drain electrode of the 2nd PMOS pipe P2; The grid of the 4th PMOS pipe P4; The drain electrode of the 5th PMOS pipe P5; The grid of the 2nd NMOS pipe N2; The source electrode of the 3rd NMOS pipe N3; The source electrode of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to first clock signal input terminal; Insert the first clock signal clk; The drain electrode of the one PMOS pipe P1; The grid of the 2nd PMOS pipe P2; The drain electrode of the 4th PMOS pipe P4; The grid of the 5th PMOS pipe P5; The source electrode of the 2nd NMOS pipe N2; The grid of the 3rd NMOS pipe N3; The grid of the source electrode of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the second clock signal input part, inserts the second clock signal

Shown in Fig. 2 (b); The waveform transformation module is by the 8th NMOS pipe N8; The 9th NMOS manages N9; The tenth NMOS manages N10; The 11 NMOS manages N11; The 12 NMOS pipe N12 and the 13 NMOS pipe N13 form; The drain electrode of the 8th NMOS pipe N8 is connected with the drain electrode of NMOS pipe N1; The source electrode of the 8th NMOS pipe N8 is connected with the grid of the 9th NMOS pipe N9; The drain electrode of the tenth NMOS pipe N10 is connected with the source electrode of the 7th NMOS pipe N7; The source electrode of the tenth NMOS pipe N10 is connected with the grid of the 11 NMOS pipe N11; The drain electrode of the 12 NMOS pipe N12 is connected with the source electrode of the 6th PMOS pipe P6; The source electrode of the 12 NMOS pipe N12 is connected with the grid of the 13 NMOS pipe N13; The grid of the 8th NMOS pipe N8; The grid of the grid of the tenth NMOS pipe N10 and the 12 NMOS pipe N12 is connected to first clock signal input terminal; Insert the first clock signal clk; The source electrode of the 9th NMOS pipe N9; The source electrode of the source electrode of the 11 NMOS pipe N11 and the 13 NMOS pipe N13 is connected to the second clock signal input part, inserts the second clock signal

The drain electrode of the 9th NMOS pipe N9 is first signal output part, and the drain electrode of the 11 NMOS pipe N11 is the secondary signal output, and the drain electrode of the 13 NMOS pipe N13 is the 3rd signal output part; The circuit symbol figure of the first tri-valued, thermal-insulating domino literal computing circuit is shown in Fig. 2 (c); The circuit structure of the second tri-valued, thermal-insulating domino literal computing circuit is identical with the first tri-valued, thermal-insulating domino literal computing circuit; Both differences are that the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit inserts addend input signal A, the first addend literal computing signal when first signal output part output addend of the first tri-valued, thermal-insulating domino literal computing circuit is logical zero ⁰A ⁰, the second addend literal computing signal when the secondary signal output output addend of the first tri-valued, thermal-insulating domino literal computing circuit is logical one ¹A ¹, the 3rd addend literal computing signal when the 3rd signal output part output addend of the first tri-valued, thermal-insulating domino literal computing circuit is logic 2 ²A ², the signal input part of the second tri-valued, thermal-insulating domino literal computing circuit inserts summand input signal B, the first summand literal computing signal when first signal output part output summand of the second tri-valued, thermal-insulating domino literal computing circuit is logical zero ⁰B ⁰The second summand literal computing signal when the secondary signal output output summand of the second tri-valued, thermal-insulating domino literal computing circuit is logical one ¹B ¹, the 3rd summand literal computing signal when the 3rd signal output part output summand of the second tri-valued, thermal-insulating domino literal computing circuit is logic 2 ²B ²

Shown in Fig. 3 (a); In the present embodiment; Carry signal produces circuit by the 7th PMOS pipe P7; The 8th PMOS manages P8; The 14 NMOS manages N14; The 15 NMOS manages N15; The 16 NMOS manages N16; The 17 NMOS manages N17; The 18 NMOS manages N18; The 19 NMOS manages N19; The 20 NMOS manages N20; The 21 NMOS manages N21; The 22 NMOS manages N22; The 23 NMOS manages N23; The 24 NMOS manages N24; The 25 NMOS pipe N25 and the 26 NMOS pipe N26 form; The source electrode of the 7th PMOS pipe P7; The grid of the 8th PMOS pipe P8; The drain electrode of the 14 NMOS pipe N14; The drain electrode of the 21 NMOS pipe N21; The drain electrode of the drain electrode of the 23 NMOS pipe N23 and the 24 NMOS pipe N24 is connected to the complementary high-order carry signal output that carry signal produces circuit, exports complementary high-order carry signal The source electrode of the 14 NMOS pipe N14; The drain electrode of the 15 NMOS pipe N15; The drain electrode of the 17 NMOS pipe N17 is connected with the drain electrode of the 18 NMOS pipe N18; The source electrode of the 15 NMOS pipe N15; The drain electrode of the 16 NMOS pipe N16; The source electrode of the 17 NMOS pipe N17; The source electrode of the 19 NMOS pipe N19; The source electrode of the 20 NMOS pipe N20; The source electrode of the 22 NMOS pipe N22 is connected with the source electrode of the 25 NMOS pipe N25; The source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 19 NMOS pipe N19; The source electrode of the 21 NMOS pipe N21 is connected with the drain electrode of the 20 NMOS pipe N20; The source electrode of the 23 NMOS pipe N23 is connected with the drain electrode of the 22 NMOS pipe N22; The source electrode of the 24 NMOS pipe N24 is connected with the drain electrode of the 25 NMOS pipe N25; The drain electrode of the source electrode of the 8th PMOS pipe P8 and the 26 NMOS pipe N26 is connected to the high-order carry signal output that carry signal produces circuit, exports high-order carry signal C _Out, the grid of the 14 NMOS pipe N14 is the low level carry signal input that carry signal produces circuit, inserts low level carry signal C _In, the second addend literal computing signal the when grid of the grid of the 18 NMOS pipe N18 and the 20 NMOS pipe N20 all inserts addend and is logical one ¹A ¹, the 3rd addend literal computing signal the when grid of the grid of the 15 NMOS pipe N15, the 23 NMOS pipe N23 and the grid of the 24 NMOS pipe N24 all insert addend and be logic 2 ²A ², the second summand literal computing signal the when grid of the grid of the 19 NMOS pipe N19 and the 22 NMOS pipe N22 all inserts summand and is logical one ¹B ¹, the 3rd summand literal computing signal the when grid of the grid of the 17 NMOS pipe N17, the 21 NMOS pipe N21 and the grid of the 25 NMOS pipe N25 all insert summand and be logic 2 ²B ²The grid of the source electrode of the drain electrode of the 7th PMOS pipe P7, the 16 NMOS pipe N16 and the 26 NMOS pipe N26 is connected to first clock signal input terminal; Insert the first clock signal clk; The source electrode of the drain electrode of the grid of the grid of the 7th PMOS pipe P7, the 16 NMOS pipe N16, the 8th PMOS pipe P8 and the 26 NMOS pipe N26 is connected to the second clock signal input part, inserts the second clock signal Carry signal produces the circuit symbol figure of circuit shown in Fig. 3 (b).

In the present embodiment, one's own department or unit and signal generating circuit comprise the first control circuit that is used for control logic 1 and produces, second control circuit and one's own department or unit and the signal output apparatus that is used for control logic 2 generations.Shown in Fig. 4 (a); First control circuit is by the 9th PMOS pipe P9; The 27 NMOS manages N27; The 28 NMOS manages N28; The 29 NMOS manages N29; The 30 NMOS manages N30; The 31 NMOS manages N31; The 32 NMOS manages N32; The 33 NMOS manages N33; The 34 NMOS manages N34; The 35 NMOS manages N35; The 36 NMOS manages N36; The 37 NMOS manages N37; The 38 NMOS manages N38; The 39 NMOS manages N39; The 40 NMOS pipe N40 and the 41 NMOS pipe N41 form; The source electrode of the 9th PMOS pipe P9; The drain electrode of the 27 NMOS pipe N27; The drain electrode of the 30 NMOS pipe N30; The drain electrode of the 32 NMOS pipe N32; The drain electrode of the 34 NMOS pipe N34; The drain electrode of the drain electrode of the 37 NMOS pipe N37 and the 39 NMOS pipe N39 is connected to first control signal output ends, the control signal Y of the first control signal output ends output logic, 1 signal ₁The source electrode of the 27 NMOS pipe N27 is connected with the drain electrode of the 28 NMOS pipe N28; The source electrode of the 28 NMOS pipe N28; The drain electrode of the 29 NMOS pipe N29; The source electrode of the 31 NMOS pipe N31 is connected with the source electrode of the 33 NMOS pipe N33; The source electrode of the 29 NMOS pipe N29; The source electrode of the 36 NMOS pipe N36 is connected with the drain electrode of the 41 NMOS pipe N41; The source electrode of the 30 NMOS pipe N30 is connected with the drain electrode of the 31 NMOS pipe N31; The source electrode of the 32 NMOS pipe N32 is connected with the drain electrode of the 33 NMOS pipe N33; The source electrode of the 34 NMOS pipe N34 is connected with the drain electrode of the 35 NMOS pipe N35; The source electrode of the 37 NMOS pipe N37 is connected with the drain electrode of the 38 NMOS pipe N38; The source electrode of the 39 NMOS pipe N39 is connected with the drain electrode of the 40 NMOS pipe N40; The source electrode of the 35 NMOS pipe N35; The drain electrode of the 36 NMOS pipe N36; The source electrode of the source electrode of the 38 NMOS pipe N38 and the 40 NMOS pipe N40 is connected, the first addend literal computing signal the when grid that the grid of the 27 NMOS pipe N27 and the 34 NMOS manage N34 all inserts addend and is logical zero ⁰A ⁰, the second addend literal computing signal the when grid of the grid of the 30 NMOS pipe N30 and the 37 NMOS pipe N37 all inserts addend and is logical one ¹A ¹, the second addend literal computing signal the when grid of the grid of the 32 NMOS pipe N32 and the 39 NMOS pipe N39 all inserts addend and is logic 2 ²A ², the second summand literal computing signal the when grid of the grid of the 28 NMOS pipe N28 and the 40 NMOS pipe N40 all inserts summand and is logical one ¹B ¹, the first summand literal computing signal the when grid of the grid of the 31 NMOS pipe N31 and the 35 NMOS pipe N35 all inserts summand and is logical zero ⁰B ⁰, the 3rd summand literal computing signal the when grid of the grid of the 33 NMOS pipe N33 and the 38 NMOS pipe N38 all inserts summand and is logic 2 ²B ²Shown in Fig. 4 (b); Second control circuit is by the tenth PMOS pipe P10; The 42 NMOS manages N42; The 43 NMOS manages N43; The 44 NMOS manages N44; The 45 NMOS manages N45; The 46 NMOS manages N46; The 47 NMOS manages N47; The 48 NMOS manages N48; The 49 NMOS manages N49; The 50 NMOS manages N50; The 51 NMOS manages N51; The 52 NMOS manages N52; The 53 NMOS manages N53; The 54 NMOS manages N54; The 55 NMOS pipe N55 and the 56 NMOS pipe N56 form; The source electrode of the tenth PMOS pipe P10; The drain electrode of the 42 NMOS pipe N42; The drain electrode of the 46 NMOS pipe N46; The drain electrode of the 48 NMOS pipe N48; The drain electrode of the 50 NMOS pipe N50; The drain electrode of the drain electrode of the 53 NMOS pipe N53 and the 55 NMOS pipe N55 is connected to second control signal output ends, the control signal Y of the second control signal output ends output logic, 2 signals ₂The source electrode of the 42 NMOS pipe N42 is connected with the drain electrode of the 43 NMOS pipe N43; The source electrode of the 43 NMOS pipe N43; The drain electrode of the 44 NMOS pipe N44; The source electrode of the 47 NMOS pipe N47 is connected with the source electrode of the 49 NMOS pipe N49; The source electrode of the 44 NMOS pipe N44; The source electrode of the 52 NMOS pipe N52 is connected with the drain electrode of the 45 NMOS pipe N45; The source electrode of the 46 NMOS pipe N46 is connected with the drain electrode of the 47 NMOS pipe N47; The source electrode of the 48 NMOS pipe N48 is connected with the drain electrode of the 49 NMOS pipe N49; The source electrode of the 50 NMOS pipe N50 is connected with the drain electrode of the 51 NMOS pipe N51; The source electrode of the 53 NMOS pipe N53 is connected with the drain electrode of the 54 NMOS pipe N54; The source electrode of the 55 NMOS pipe N55 is connected with the drain electrode of the 56 NMOS pipe N56; The source electrode of the 51 NMOS pipe N51; The drain electrode of the 52 NMOS pipe N52; The source electrode of the source electrode of the 54 NMOS pipe N54 and the 56 NMOS pipe N56 is connected, the first addend literal computing signal the when grid that the grid of the 42 NMOS pipe N42 and the 50 NMOS manage N50 all inserts addend and is logical zero ⁰A ⁰, the second addend literal computing signal the when grid that the grid of the 46 NMOS pipe N46 and the 53 NMOS manage N53 all inserts addend and is logical one ¹A ¹, the 3rd addend literal computing signal the when grid of the grid of the 48 NMOS pipe N48 and the 55 NMOS pipe N55 all inserts addend and is logic 2 ²A ², the second summand literal computing signal the when grid of the grid of the 43 NMOS pipe N43 and the 56 NMOS pipe N56 all inserts summand and is logical one ¹B ¹, the first summand literal computing signal the when grid of the grid of the 47 NMOS pipe N47 and the 51 NMOS pipe N51 all inserts summand and is logical zero ⁰B ⁰The 3rd summand literal computing signal the when grid that the grid of the 49 NMOS pipe N49 and the 54 NMOS manage N54 all inserts summand and is logic 2 ²B ²Shown in Fig. 4 (c); One's own department or unit and signal output apparatus are by the 11 PMOS pipe P11; The 12 PMOS pipe P12 and the 57 NMOS pipe N57 form; The grid of the 11 PMOS pipe P11 is connected with first control signal output ends; The grid of the 12 PMOS pipe P12 is connected with second control signal output ends; The source electrode of the 11 PMOS pipe P11; The drain electrode of the source electrode of the 12 PMOS pipe P12 and the 57 NMOS pipe N57 and connect and itself and connect one's own department or unit and the signal output part of end for one's own department or unit and signal generating circuit; Output one's own department or unit and output signal S; The grid of the 9th PMOS pipe P9; The grid of the tenth PMOS pipe P10; The drain electrode of the 12 PMOS pipe P12; The grid of the 41 NMOS pipe N41; The source electrode of the grid of the 45 NMOS pipe N45 and the 57 NMOS pipe N57 is connected to the second clock signal input part, inserts the second clock signal

The grid of the source electrode of the source electrode of the drain electrode of the drain electrode of the 9th PMOS pipe P9, the tenth PMOS pipe P10, the 41 NMOS pipe N41, the 45 NMOS pipe N45 and the 57 NMOS pipe N57 is connected to first clock signal input terminal; Insert the first clock signal clk; The drain electrode of the 11 PMOS pipe P11 is connected with the 3rd clock signal input terminal, inserts the 3rd clock signal

The grid of the grid of the 29 NMOS pipe N29 and the 44 NMOS pipe N44 and connect and itself and connect the complementary low level carry signal input of end for one's own department or unit and signal generating circuit, insert complementary low level carry signal

The grid of the grid of the 36 NMOS pipe N36 and the 52 NMOS pipe N52 and connect and itself and connect the low level carry signal input of end, access low level carry signal C for one's own department or unit and signal generating circuit _InThe circuit symbol figure of one's own department or unit and signal generating circuit is shown in Fig. 4 (d).

The mentality of designing that the carry signal of present embodiment produces circuit is: at first according to the truth table of switching signal theory and three value adders, obtain complementary high-order carry signal

With high-order carry signal C _OutThe switching stage structural formula be respectively:

$\stackrel{\&OverBar;}{C_{\mathrm{out}}}=\mathrm{clk}*{\stackrel{\&OverBar;}{\mathrm{clk}}}^{0.5}\#\mathrm{clk}{*}^{1.5}\stackrel{\&OverBar;}{\mathrm{clk}}*[A_1^1{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2*({C_{\mathrm{in}}}^{1.5}+C_{\mathrm{in}}^{1.5}){\#}^2{A}^2{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1*({C_{\mathrm{in}}}^{1.5}+C_{\mathrm{in}}^{1.5})$

${\#}^2{A}^2{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2*({C_{\mathrm{in}}}^{1.5}+C_{\mathrm{in}}^{1.5}){\#}^0{A}^0{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2{*}^{1.5}{C}_{\mathrm{in}}{\#}^1{A}^1{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1{*}^{1.5}{C}_{\mathrm{in}}{\#}^2{A}^2{*}^{1.5}\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="HDA00001897499800014.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_0^0{*}^{1.5}{C}_{\mathrm{in}}]---\left(1\right)$

$=\mathrm{clk}*{\stackrel{\&OverBar;}{\mathrm{clk}}}^{1.5}\#\mathrm{clk}{*}^{1.5}\stackrel{\&OverBar;}{\mathrm{clk}}*(A_1^1{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2{\#}^2{A}^2{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1{\#}^2{A}^2{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2{\#}^0{A}^0{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2{*}^{1.5}{C}_{\mathrm{in}}$

${\#A}^1{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1*C_{\mathrm{in}}^{1.5}{\#}^2{A}^2{*}^{1.5}\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="HDA00001897499800014.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_0^0{*}^{1.5}{C}_{\mathrm{in}})$

$C_{\mathrm{out}}=\stackrel{\&OverBar;}{\mathrm{clk}}*{\stackrel{\&OverBar;}{C_{\mathrm{out}}}}^{0.5}\#\stackrel{\&OverBar;}{\mathrm{clk}}{*}^{1.5}\mathrm{clk}---\left(2\right)$

In the formula (1),

Expression is worked as

During for low level, clk carries out precharge to the dynamic node of the high-order carry signal output of complementation; The expression in back is worked as

Be high level, and input signal A+B+C _In＞2 o'clock, the electric charge that is stored in the dynamic node of complementary high-order carry signal output was recovered to the process of clk; What formula (2) was represented is complementary high-order carry signal

Obtain high-order carry signal C through adiabatic inverter _OutProcess.Can obtain the circuit diagram of carry signal generation circuit as shown in the figure by formula (1) and formula (2).

The one's own department or unit of present embodiment and the mentality of designing of signal generating circuit are: the truth table of at first theoretical and three value adders according to switching signal, obtain one's own department or unit and export switching stage structural formula and the circuit of signal S, but with high-order carry signal C _OutDifference, one's own department or unit has 0,1 with output signal S, and therefore 2 three kinds of logical values need the generation of different circuits difference control logic 1 signal and logic 2 signals.Make Y ₁, Y ₂Be respectively the control signal of logical one signal and logic 2 signals, then its switching stage structural formula is:

${\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1=\mathrm{clk}*{\stackrel{\&OverBar;}{\mathrm{clk}}}^{0.5}\#\mathrm{clk}{*}^{1.5}\stackrel{\&OverBar;}{\mathrm{clk}}*[{}^{1.5}\stackrel{\&OverBar;}{C_{\mathrm{in}}}*\left({}^{1.5}A_0^0{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1{\#}^{1.5}A_1^1{*}^{1.5}\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="HDA00001897499800014.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_0^0{\#}^{1.5}A_2^2{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2\right)$

${\#}^{1.5}{C}_{\mathrm{in}}*\left({}^{1.5}A_0^0{*}^{1.5}\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="HDA00001897499800014.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_0^0{\#}^{1.5}A_1^1{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2{\#}^{1.5}A_2^2{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1\right)]---\left(3\right)$

${\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2=\mathrm{clk}*{\stackrel{\&OverBar;}{\mathrm{clk}}}^{0.5}\#\mathrm{clk}{*}^{1.5}\stackrel{\&OverBar;}{\mathrm{clk}}*[{}^{1.5}\stackrel{\&OverBar;}{C_{\mathrm{in}}}*\left({}^{1.5}A_0^0{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2{\#}^{1.5}A_1^1{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1{\#}^{1.5}A_2^2{*}^{1.5}\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="HDA00001897499800014.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_0^0\right)$

${\#}^{1.5}{C}_{\mathrm{in}}*\left({}^{1.5}A_0^0{*}^{1.5}\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">B</figure-callout>}_1^1{\#}^{1.5}A_1^1{*}^{1.5}\mathrm{<figure-callout\; id="0"\; label="B"\; filenames="HDA00001897499800014.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_0^0{\#}^{1.5}A_2^2{*}^{1.5}\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">B</figure-callout>}_2^2\right)]---\left(4\right)$

In the formula (3),

Expression is worked as

During for low level, clk carries out precharge to the dynamic node of first control signal output ends; The expression in back is worked as Be high level, and input signal A+B+C _InThe electric charge that was stored in the dynamic node of first control signal output ends at=1 o'clock is recovered to the process of clk, and Y1 becomes low level; The circuit working process and the formula (3) of formula (4) expression are similar, and different is as input signal A+B+C _InThe electric charge of the dynamic node of 1: second control signal output ends is recovered to clk, Y ₂Become low level.Can obtain as shown in the figure first control circuit and the circuit diagram of second control circuit according to formula (3) and formula (4).Utilize the first control signal Y ₁With the second control signal Y ₂Can control logic 1 signal and the generation of logic 2 signals, thus one's own department or unit and output signal S of three value adders obtained, and the switching stage structural formula of one's own department or unit and signal generating circuit is:

$S=\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="clk"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">clk</figure-callout>}}_1}*{{\mathrm{<figure-callout\; id="1"\; label="Y"\; filenames="HDA00001897499800023.png,HDA00001897499800031.png"\; state="\{\{state\}\}">Y</figure-callout>}}_1}^{1.5}*\stackrel{\&OverBar;}{\mathrm{clk}}*{{\mathrm{<figure-callout\; id="2"\; label="Y"\; filenames="HDA00001897499800021.png,HDA00001897499800023.png"\; state="\{\{state\}\}">Y</figure-callout>}}_2}^{1.5}\#\stackrel{\&OverBar;}{\mathrm{clk}}{*}^{1.5}\mathrm{clk}---\left(5\right)$

In the formula (5),

The circuit working process of expression is: work as Y ₁During for low level, because Amplitude represent logical value 1, so one's own department or unit is output as 1 with output signal S; Work as Y ₂During for low level, because

Amplitude represent logical value 2, this moment, one's own department or unit was output as 2 with output signal S.

indicates that when clk is high, and the signal output terminal based on the node stored in the charge is recovered

process.Can know by formula (3) and formula (4), when clk is high level,

Be low level; The node of the node of first control signal output ends and second control signal output ends is recharged to high level; And can not occur when clk is high level; The node of the node of first control signal output ends and second control signal output ends is low level situation, i.e. the first control signal Y ₁With the second control signal Y ₂Can not be low level, thereby guarantee

With

Can short circuit.

In the present embodiment; After all changing by the waveform transformation module, each output signal of each output signal of the first tri-valued, thermal-insulating domino literal computing circuit Chinese words computing module and the second tri-valued, thermal-insulating domino literal computing circuit Chinese words computing module is transported to the respective end that carry signal produces circuit and one's own department or unit and signal generating circuit; The waveform transformation module is carried out waveform optimization to each output signal of literal computing module; Obtain being applicable to the gradual trapezoidal wave signal of adiabatic circuits; This gradual trapezoidal wave signal and clock phase error are minimum; Can reduce the extra power consumption that level adiabatic domino circuit in back produces because of the phase difference of signal and clock when discharging and recharging; Guarantee that circuit has correct logic, for the design of tri-valued, thermal-insulating domino complicated circuit is laid a good foundation.

Utilize Spice software, under TSMC 0.25 μ m CMOS technological parameter, tri-valued, thermal-insulating domino adder unit is simulated, its analog waveform figure as shown in Figure 6.Wherein logical value 0,1, and 2 corresponding level are respectively 0V, 1.25V, 2.5V; Clk1,

Clk,

Amplitude be respectively 1.25V, 1.25V, 2.5V, 2.5V, frequency all is 20MHz; The NMOS breadth length ratio is all got 0.36 μ m/0.24 μ m, and the PMOS breadth length ratio is all got 0.72 μ m/0.24 μ m; Load capacitance is 10fF; A and B are respectively addend input signal and summand input signal; S is one's own department or unit and output signal, C _OutBe high-order carry signal.Analysis chart 6 can know that the logic function of this tri-valued, thermal-insulating domino adder unit is consistent with the truth table of three value adders, and the logic function of the provable thus tri-valued, thermal-insulating domino adder unit that designs is correct.

Under identical parameters, tri-valued, thermal-insulating domino adder unit and the conventional domino adder unit of three values that adopts DC power supply are carried out the transient state energy consumption relatively, its energy consumption comparison diagram is as shown in Figure 7.The concave bottom of tri-valued, thermal-insulating domino adder unit transient state energy consumption curve representes that energy is recovered to power clock among Fig. 7, thereby reduces circuit power consumption effectively.Through analyzing, compare with the conventional domino adder unit of three values that adopts DC power supply, it is about 54% that this thermal insulation three is worth adder unit Power Cutbacks, prove to design circuit low-power consumption characteristic obvious.Compare with three value adder units based on the DTCTGAL circuit design, it is about 47% that these thermal insulation three value adder unit number of transistors reduce, and reduced the cost of circuit.Utilize tri-valued, thermal-insulating domino adder unit of the present invention can constitute more three value low-power consumption adders of long number, promoted the practicalization of three value digital systems.

Claims (5)

1. A ternary adiabatic domino addition unit, characterized in that it comprises a first ternary adiabatic domino word operation circuit, a second ternary adiabatic domino word operation circuit, a carry signal generation circuit, a standard sum signal generation circuit, and a first clock signal input terminal, the second clock signal input terminal and the third clock signal input terminal, the carry signal generating circuit is provided with a low-order carry signal input terminal, an addend word operation signal input end, an augend word operation signal input end, a high-order A carry signal output terminal and a complementary high-order carry signal output terminal, the home position and signal generating circuit is provided with an adder word operation signal input end, an augend word operation signal input end, a low-order carry signal input end, and a complementary low-order carry signal input end and standard and signal output end, the signal input end of the first three-value adiabatic domino word operation circuit is used to access the addend input signal, and the signal output ends of the first three-value adiabatic domino word operation circuit are respectively It is connected with the addend word operation signal input end of the said carry signal generation circuit and the adder word operation signal input end of the said base sum signal generation circuit, and the signal input of the second ternary adiabatic domino word operation circuit The terminal is used to access the summand input signal, and the signal output terminal of the second ternary adiabatic domino word operation circuit is respectively connected with the summand word operation signal input terminal of the carry signal generating circuit and the basic position It is connected with the input terminal of the summed word operation signal of the signal generating circuit, and the low-order carry signal input end of the said carry signal generating circuit is connected with the low-order carry signal input end of the said base and signal generating circuit, and the first The ternary adiabatic domino word operation circuit, the second ternary adiabatic domino word operation circuit and the carry signal generating circuit are all connected to the first clock signal input end and the second clock signal input end respectively connected, the said home position and signal generating circuit are respectively connected with said first clock signal input end, said second clock signal input end and said third clock signal input end. 2. a kind of ternary adiabatic domino addition unit according to claim 1, it is characterized in that the output signal of the signal output end of the first ternary adiabatic domino word operation circuit is the addend input connected with its signal input end The three addend word operation signals corresponding to the signal are the first addend word operation signal when the addend is logic 0, the second addend word operation signal when the addend is logic 1, and the addend word operation signal when the addend is logic 2. The third addend word operation signal, wherein the addend word operation signal input terminal of the carry signal generating circuit is connected to the second addend word operation signal and the third addend word operation signal, the The addend word operation signal input terminal of the basic position and signal generating circuit is connected to the first addend word operation signal, the second addend word operation signal and the third addend word operation signal, so The output signals of the signal output end of the second ternary adiabatic domino word operation circuit described above are three summand word operation signals corresponding to the summand input signal connected to the signal input end, respectively when the summand is logic 0 The first augend literal operation signal, the second augend literal operation signal when the augend is logic 1, and the third augend literal operation signal when the augend is logic 2, wherein the carry signal The input end of the summand word operation signal of the generating circuit is connected to the second summand word operation signal and the third summand word operation signal, and the summand word operation signal of the basic position and signal generating circuit is The operation signal input port is connected with the first summand word operation signal, the second summand word operation signal and the third summand word operation signal. 3. A kind of ternary adiabatic domino adding unit according to claim 2, characterized in that said first ternary adiabatic domino word operation circuit comprises a word operation module and a waveform conversion module, and said word operation module consists of the first A PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a Five NMOS transistors, sixth NMOS transistors and seventh NMOS transistors, the gate of the first NMOS transistor is connected in parallel with the gate of the fourth NMOS transistor, and the parallel connection end is a signal input end, the The drain of the first NMOS transistor, the source of the first PMOS transistor and the gate of the third PMOS transistor are connected in parallel, and the source of the first NMOS transistor is connected to the second NMOS transistor The drain of the tube is connected, the source of the second PMOS tube is connected to the drain of the third PMOS tube, the source of the third PMOS tube, the drain of the third NMOS tube connected in parallel with the drain of the seventh NMOS transistor, the source of the fourth PMOS transistor, the drain of the fourth NMOS transistor, the gate of the sixth PMOS transistor and the The gate of the seventh NMOS transistor is connected in parallel, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth PMOS transistor is connected to the sixth PMOS transistor. The drain of the tube is connected, the source of the sixth PMOS tube is connected in parallel with the drain of the sixth NMOS tube, the gate of the first PMOS tube, the drain of the second PMOS tube pole, the gate of the fourth PMOS transistor, the drain of the fifth PMOS transistor, the gate of the second NMOS transistor, the source of the third NMOS transistor, the first The gate of the fifth NMOS transistor and the source of the sixth NMOS transistor are connected to the first clock signal input terminal in parallel, the drain of the first PMOS transistor, the gate of the second PMOS transistor, the The drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the source of the second NMOS transistor, the gate of the third NMOS transistor, the fifth NMOS transistor The source of the sixth NMOS transistor and the gate of the sixth NMOS transistor are connected to the second clock signal input terminal in parallel, and the waveform conversion module is composed of the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor tube, the twelfth NMOS tube and the thirteenth NMOS tube, the drain of the eighth NMOS tube is connected to the drain of the first NMOS tube, the source of the eighth NMOS tube is connected to the The gate of the ninth NMOS transistor is connected, the drain of the tenth NMOS transistor is connected to the source of the seventh NMOS transistor, and the source of the tenth NMOS transistor is connected to the tenth NMOS transistor. The gate of an NMOS transistor is connected, the drain of the twelfth NMOS transistor is connected to the source of the sixth PMOS transistor, and the source of the twelfth NMOS transistor is connected to the source of the sixth PMOS transistor. The gate of the thirteenth NMOS transistor is connected, the gate of the eighth NMOS transistor, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected to the first clock signal input in parallel end, the source of the ninth NMOS transistor, the source of the eleventh NMOS transistor and the source of the thirteenth NMOS transistor are connected to the second clock signal input end in parallel, and the first The drain of the ninth NMOS transistor is the first signal output end, the drain of the eleventh NMOS transistor is the second signal output end, the drain of the thirteenth NMOS transistor is the third signal output end, and the drain of the eleventh NMOS transistor is the third signal output end. The circuit structure of the two- and three-value adiabatic domino word operation circuit is the same as that of the first three-value adiabatic domino word operation circuit, and the difference between the two is that the signal input terminal of the first three-value adiabatic domino word operation circuit is connected to the plus number input signal, the first signal output terminal of the first three-value adiabatic domino word operation circuit outputs the first addend word operation signal when the addend is logic 0, and the first three-value adiabatic domino word operation circuit The second signal output end of the first ternary adiabatic domino word operation circuit outputs the second addend word operation signal when the addend is logic 1, and the third signal output end of the first ternary adiabatic domino word operation circuit outputs the third addend when the addend is logic 2 Addend word operation signal, the signal input end of the second ternary adiabatic domino word operation circuit is connected to the summand input signal, and the output of the first signal output end of the second ternary adiabatic domino word operation circuit is output by The first summand word operation signal when the addend is logic 0, the second signal output terminal of the second ternary adiabatic domino word operation circuit outputs the second summand word operation when the addend is logic 1 signal, the third signal output terminal of the second ternary adiabatic domino word operation circuit outputs the third addend word operation signal when the addend is logic 2. 4. A ternary adiabatic domino addition unit according to claim 3, characterized in that said carry signal generation circuit consists of a seventh PMOS transistor, an eighth PMOS transistor, a fourteenth NMOS transistor, and a fifteenth NMOS transistor , the sixteenth NMOS tube, the seventeenth NMOS tube, the eighteenth NMOS tube, the nineteenth NMOS tube, the twenty NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube and the twenty-sixth NMOS tube, the source of the seventh PMOS tube, the gate of the eighth PMOS tube, the The drain of the fourteenth NMOS transistor, the drain of the twenty-first NMOS transistor, the drain of the twenty-third NMOS transistor, and the drain of the twenty-fourth NMOS transistor are connected in parallel to the The complementary high-order carry signal output terminal of the carry signal generating circuit, the source of the fourteenth NMOS transistor, the drain of the fifteenth NMOS transistor, the drain of the seventeenth NMOS transistor and The drain of the eighteenth NMOS transistor is connected, the source of the fifteenth NMOS transistor, the drain of the sixteenth NMOS transistor, the source of the seventeenth NMOS transistor, the The source of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor, the source of the twenty-second NMOS transistor and the source of the twenty-fifth NMOS transistor are connected, The source of the eighteenth NMOS transistor is connected to the drain of the nineteenth NMOS transistor, and the source of the twenty-first NMOS transistor is connected to the drain of the twentieth NMOS transistor , the source of the twenty-third NMOS transistor is connected to the drain of the twenty-second NMOS transistor, the source of the twenty-fourth NMOS transistor is connected to the twenty-fifth NMOS transistor The drain of the eighth PMOS transistor and the drain of the twenty-sixth NMOS transistor are connected in parallel to the high-order carry signal output end of the carry signal generating circuit, and the tenth The gates of the four NMOS transistors are the low-order carry signal input terminals of the carry signal generating circuit, and the gates of the eighteenth NMOS transistor and the gates of the twenty NMOS transistor are connected to the addend as logic The second addend word operation signal at 1 o'clock, the grid of the fifteenth NMOS transistor, the grid of the twenty-third NMOS transistor and the grid of the twenty-fourth NMOS transistor are all connected to Input the third addend word operation signal when the addend is logic 2, the gate of the nineteenth NMOS transistor and the gate of the twenty-second NMOS transistor are connected when the addend is logic 1 The second summand word operation signal, the grid of the seventeenth NMOS transistor, the grid of the twenty-first NMOS transistor and the grid of the twenty-fifth NMOS transistor are connected to The third summand word operation signal when the summand is logic 2, the drain of the seventh PMOS transistor, the source of the sixteenth NMOS transistor and the twenty-sixth NMOS transistor The gate is connected to the first clock signal input terminal in parallel, and the first The gates of the seven PMOS transistors, the gate of the sixteenth NMOS transistor, the drain of the eighth PMOS transistor and the source of the twenty-sixth NMOS transistor are connected in parallel to the second clock signal input end. 5. A kind of ternary adiabatic domino adding unit according to claim 4, characterized in that said home position and signal generating circuit comprises a first control circuit for controlling logic 1 generation, and a first control circuit for controlling logic 2 generation Two control circuits and standard and signal output circuits, the first control circuit consists of a ninth PMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor, a thirty NMOS transistor, The thirty-first NMOS tube, the thirty-second NMOS tube, the thirty-third NMOS tube, the thirty-fourth NMOS tube, the thirty-fifth NMOS tube, the thirty-sixth NMOS tube, the thirty-seventh NMOS tube, the thirty-seventh NMOS tube, The thirty-eighth NMOS transistor, the thirty-ninth NMOS transistor, the fortieth NMOS transistor, and the forty-first NMOS transistor, the source of the ninth PMOS transistor, and the drain of the twenty-seventh NMOS transistor , the drain of the 30th NMOS transistor, the drain of the thirty-second NMOS transistor, the drain of the thirty-fourth NMOS transistor, the drain of the thirty-seventh NMOS transistor The pole and the drain of the thirty-ninth NMOS transistor are connected in parallel to the first control signal output end, and the first control signal output end outputs a control signal of a logic 1 signal, and the twenty-seventh NMOS transistor The source of the twenty-eighth NMOS tube is connected to the drain of the twenty-eighth NMOS tube, the source of the twenty-eighth NMOS tube, the drain of the twenty-ninth NMOS tube, the thirty-ninth NMOS tube The source of an NMOS transistor is connected to the source of the thirty-third NMOS transistor, the source of the twenty-ninth NMOS transistor, the source of the thirty-sixth NMOS transistor are connected to the source of the thirty-sixth NMOS transistor The drain of the forty-first NMOS transistor is connected, the source of the thirty-first NMOS transistor is connected to the drain of the thirty-first NMOS transistor, and the source of the thirty-second NMOS transistor is connected to the drain of the thirty-second NMOS transistor. The drain of the thirty-third NMOS transistor is connected, the source of the thirty-fourth NMOS transistor is connected to the drain of the thirty-fifth NMOS transistor, and the thirty-seventh NMOS transistor The source of the thirty-eighth NMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, the source of the thirty-ninth NMOS transistor is connected to the drain of the fortieth NMOS transistor, and the thirty-ninth NMOS transistor is connected to the drain of the thirty-eighth NMOS transistor. The source of the fifth NMOS transistor, the drain of the thirty-sixth NMOS transistor, the source of the thirty-eighth NMOS transistor and the source of the fortieth NMOS transistor are connected, and the first The grid of the twenty-seventh NMOS transistor and the grid of the thirty-fourth NMOS transistor are connected to the first addend word operation signal when the addend is logic 0, and the grid of the thirty-fourth NMOS transistor is and the gate of the thirty-seventh NMOS transistor are connected to the second addend word operation signal when the addend is logic 1, the gate of the thirty-second NMOS transistor and the thirty-second The grids of the nine NMOS transistors are all connected to the third addend word operation signal when the addend is logic 2, and the grids of the twenty-eighth NMOS transistors and the fortieth NMOS transistors are connected Input the second summand word operation signal when the summand is logic 1, the The gate of the thirty-first NMOS transistor and the gate of the thirty-fifth NMOS transistor are both connected to the first summand word operation signal when the summand is logic 0, and the thirty-third The grid of the NMOS transistor and the grid of the thirty-eighth NMOS transistor are all connected to the third summand word operation signal when the summand is logic 2, and the second control circuit is composed of the tenth PMOS transistor , the forty-second NMOS tube, the forty-third NMOS tube, the forty-fourth NMOS tube, the forty-fifth NMOS tube, the forty-sixth NMOS tube, the forty-seventh NMOS tube, the forty-eighth NMOS tube, The forty-ninth NMOS tube, the fiftieth NMOS tube, the fifty-first NMOS tube, the fifty-second NMOS tube, the fifty-third NMOS tube, the fifty-fourth NMOS tube, the fifty-fifth NMOS tube, and the fifth Sixteen NMOS transistors, the source of the tenth PMOS transistor, the drain of the forty-second NMOS transistor, the drain of the forty-sixth NMOS transistor, the forty-eighth NMOS transistor The drain of the NMOS transistor, the drain of the fiftieth NMOS transistor, the drain of the fifty-third NMOS transistor, and the drain of the fifty-fifth NMOS transistor are connected to the second control signal in parallel output terminal, the second control signal output terminal outputs a control signal of a logic 2 signal, the source of the forty-second NMOS transistor is connected to the drain of the forty-third NMOS transistor, and the The source of the forty-third NMOS transistor, the drain of the forty-fourth NMOS transistor, the source of the forty-seventh NMOS transistor are connected to the source of the forty-ninth NMOS transistor, The source of the forty-fourth NMOS transistor, the drain of the forty-fifth NMOS transistor are connected to the source of the fifty-second NMOS transistor, and the forty-sixth NMOS transistor The source is connected to the drain of the forty-seventh NMOS transistor, the source of the forty-eighth NMOS transistor is connected to the drain of the forty-ninth NMOS transistor, and the fifty-ninth NMOS transistor is connected to the drain. The source of the NMOS transistor is connected to the drain of the fifty-first NMOS transistor, the source of the fifty-third NMOS transistor is connected to the drain of the fifty-fourth NMOS transistor, and the The source of the fifty-fifth NMOS transistor is connected to the drain of the fifty-sixth NMOS transistor, the source of the fifty-first NMOS transistor, the drain of the fifty-second NMOS transistor, The source of the fifty-fourth NMOS transistor is connected to the source of the fifty-sixth NMOS transistor, the gate of the forty-second NMOS transistor is connected to the gate of the fiftieth NMOS transistor The poles are evenly connected to the first addend word operation signal when the addend is logic 0, and the gate of the forty-sixth NMOS transistor and the gate of the fifty-third NMOS transistor are both connected to the addend. The second addend word operation signal when the logic is 1, the gate of the forty-eighth NMOS transistor and the grid of the fifty-fifth NMOS transistor are connected to the third addend when the addend is logic 2 Digital word operation signal, the gate of the forty-third NMOS transistor and the gate of the fifty-sixth NMOS transistor are connected to The second summand word operation signal when the summand is logic 1, the gate of the forty-seventh NMOS transistor and the gate of the fifty-first NMOS transistor are connected to the summand as logic The first summand word operation signal at 0, the gate of the forty-ninth NMOS transistor and the gate of the fifty-fourth NMOS transistor are connected to the third summand when the summand is logic 2 The summand word operation signal, the said basic position and signal output circuit is composed of the eleventh PMOS transistor, the twelfth PMOS transistor and the fifty-seventh NMOS transistor, and the grid of the eleventh PMOS transistor is connected to the The first control signal output end of the described twelfth PMOS transistor is connected to the second control signal output end, the source electrode of the eleventh PMOS transistor, the twelfth PMOS transistor The source of the PMOS transistor is connected in parallel with the drain of the fifty-seventh NMOS transistor and its parallel connection end is the standard and signal output end of the described standard and signal generating circuit, and the gate of the ninth PMOS transistor is pole, the gate of the tenth PMOS transistor, the drain of the twelfth PMOS transistor, the gate of the forty-first NMOS transistor, the gate of the forty-fifth NMOS transistor The source of the fifty-seventh NMOS transistor is connected to the second clock signal input terminal in parallel, the drain of the ninth PMOS transistor, the drain of the tenth PMOS transistor, the forty The source of an NMOS transistor, the source of the forty-fifth NMOS transistor, and the gate of the fifty-seventh NMOS transistor are connected to the first clock signal input terminal in parallel, and the eleventh PMOS transistor The drain is connected to the third clock signal input end, the gate of the twenty-ninth NMOS transistor and the gate of the forty-fourth NMOS transistor are connected in parallel, and the parallel terminals are the standard and The complementary low-order carry signal input end of the signal generation circuit, the gate of the thirty-sixth NMOS transistor and the gate of the fifty-second NMOS transistor are connected in parallel, and the parallel connection terminal is the standard sum signal The low-order carry signal input terminal of the generation circuit.

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