CN102832926A - Low power consumption multiposition three-valued Domino adder - Google Patents
Low power consumption multiposition three-valued Domino adder Download PDFInfo
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Abstract
本发明公开了一种多位三值低功耗多米诺加法器，由n位三值绝热多米诺加法单元组成，第k位三值绝热多米诺加法单元和第k+1位三值绝热多米诺加法单元的低位进位信号输出端通过一个绝热多米诺缓冲器连接，第k位三值绝热多米诺加法单元和第k+1位三值绝热多米诺加法单元的互补低位进位信号输出端也通过一个绝热多米诺缓冲器连接，第j位三值绝热多米诺加法单元的本位和信号输出端依次连接有n-j个绝热多米诺缓冲器，第j位三值绝热多米诺加法单元的加数信号输入端和被加数信号输入端均依次连接有j-1个绝热多米诺缓冲器，k=1，2，……，n-1，j=1，2，……，n ， m=1，2，……，n-1；优点是与采用直流电源的常规三值多米诺加法器相比功耗节省约61%。
The invention discloses a multi-bit ternary low power consumption domino adder, which is composed of an n -bit ternary adiabatic domino addition unit, a kth ternary adiabatic domino addition unit and a k+1 th ternary adiabatic domino addition unit The low-order carry signal output terminal is connected through an adiabatic domino buffer, and the complementary low-order carry signal output terminals of the k -th ternary-value adiabatic domino addition unit and the k +1-th ternary-value adiabatic domino addition unit are also connected through an adiabatic domino buffer, The base and signal output terminals of the j -th ternary adiabatic domino addition unit are sequentially connected with n - j adiabatic domino buffers, and the adder signal input end and the augend signal input end of the j -th ternary adiabatic domino addition unit are both There are j- 1 adiabatic domino buffers connected sequentially, k =1,2,..., n- 1, j =1,2,..., n , m =1,2,..., n-1 ; advantages Compared with the conventional three-value domino adder using a DC power supply, the power consumption is saved by about 61%.
Description
Technical field
The present invention relates to a kind of three value adders, especially relate to a kind of multidigit three value low-power consumption domino adders.
Background technology
The current digit Circuits System mainly adopts two-valued function to realize, the logical value that its single holding wire can transmit has only 0 and 1 two kind, and the room and time utilance of circuit is lower.Adopt multi valued logic can significantly reduce circuit input variable number, improve the amount of information that every line carries, thereby reduce area of chip, strengthen data-handling capacity.Therefore domino circuit combines multi valued logic because its advantage on circuit area and speed is widely used in the various high performance circuits with domino circuit, can further reduce circuit area, improves the information density of circuit, reduces circuit cost.
Add operation is the most basic arithmetical operation, and subtraction, multiplication, division, address computation etc. can realize with addition in theory.Therefore, adder be the critical component of digital system also be to use one of parts the most widely, the power consumption of adder is determining the power consumption of whole digital system to a great extent.At present traditional adder has caused great waste because electric charge is disposable consuming from the power supply to ground; And the abundant charge stored in the recovery circuit node of the adiabatic adder that adopts the alternating-current pulse power supply effectively reduces the power consumption of circuit.Given this, multi valued logic, adiabatic logic and domino circuit are applied in the design of adder and have realistic meaning.
Summary of the invention
Technical problem to be solved by this invention provides and is a kind ofly guaranteeing to have under the prerequisite of correct logic functions, the multidigit three value low-power consumption domino adders that power consumption is lower.
The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of multidigit three value low-power consumption domino adders, by
nPosition tri-valued, thermal-insulating domino adder unit is formed; Described tri-valued, thermal-insulating domino adder unit is provided with the addend signal input part; The summand signal input part; Low level carry signal input; Complementary low level carry signal input; High-order carry signal output; Complementary high-order carry signal output; One's own department or unit and signal output part; First clock signal input terminal; Second clock signal input part and the 3rd clock signal input terminal; The low level carry signal input of the 1st tri-valued, thermal-insulating domino adder unit inserts 0; The complementary low level carry signal input of the 1st tri-valued, thermal-insulating domino adder unit is connected with described second clock signal input part, the
kThe high-order carry signal output of position tri-valued, thermal-insulating domino adder unit and the
K+1The low level carry signal output of position tri-valued, thermal-insulating domino adder unit connects through an adiabatic domino buffer, the
kThe complementary high-order carry signal output of position tri-valued, thermal-insulating domino adder unit and the
kThe complementary low level carry signal output of+1 tri-valued, thermal-insulating domino adder unit also connects through an adiabatic domino buffer, the
jThe one's own department or unit and the signal output part of position tri-valued, thermal-insulating domino adder unit are connected with in turn
n-
jIndividual adiabatic domino buffer, the
jThe addend signal input part and the summand signal input part of position tri-valued, thermal-insulating domino adder unit all are connected with in turn
J-1 adiabatic domino buffer, wherein,
k=1,2 ...,
N-1,
j=1,2 ...,
N, m=1,2 ...,
N-1
A kind of multidigit three value low-power consumption domino adders are made up of four tri-valued, thermal-insulating domino adder units; Every described tri-valued, thermal-insulating domino adder unit comprises the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; Carry signal produces circuit; One's own department or unit and signal generating circuit; First clock signal input terminal; Second clock signal input part and the 3rd clock signal input terminal; Described carry signal produces circuit and is provided with low level carry signal input; Addend literal computing signal input part; Summand literal computing signal input part; High-order carry signal output and complementary high-order carry signal output; Described one's own department or unit and signal generating circuit are provided with addend literal computing signal input part; Summand literal computing signal input part; Low level carry signal input; Complementary low level carry signal input and one's own department or unit and signal output part; The signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit is used to insert the addend input signal; The signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit produces the addend literal computing signal input part of circuit with described carry signal respectively and the addend literal computing signal input part of described one's own department or unit and signal generating circuit is connected; The signal input part of the described second tri-valued, thermal-insulating domino literal computing circuit is used to insert the summand input signal; The signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit produces the summand literal computing signal input part of circuit with described carry signal respectively and the summand literal computing signal input part of described one's own department or unit and signal generating circuit is connected; The low level carry signal input that described carry signal produces circuit is connected with the low level carry signal input of described one's own department or unit and signal generating circuit; The described first tri-valued, thermal-insulating domino literal computing circuit; The described second tri-valued, thermal-insulating domino literal computing circuit produces circuit with described carry signal and is connected with described second clock signal input part with described first clock signal input terminal respectively; Described one's own department or unit and signal generating circuit respectively with described first clock signal input terminal; Described second clock signal input part is connected with described the 3rd clock signal input terminal; First clock signal input terminal of the 1st tri-valued, thermal-insulating domino adder unit and the 3rd tri-valued, thermal-insulating domino adder unit all inserts first clock signal of amplitude level counterlogic 2; The second clock signal input part of the 1st tri-valued, thermal-insulating domino adder unit and the 3rd tri-valued, thermal-insulating domino adder unit all inserts the second clock signal of amplitude level counterlogic 2; The 3rd clock signal input terminal of the 1st tri-valued, thermal-insulating domino adder unit and the 3rd tri-valued, thermal-insulating domino adder unit all inserts the 3rd clock signal of amplitude level counterlogic 1; First clock signal input terminal of the 2nd tri-valued, thermal-insulating domino adder unit and the 4th tri-valued, thermal-insulating domino adder unit all inserts the second clock signal of amplitude level counterlogic 2; The second clock signal input part of the 2nd tri-valued, thermal-insulating domino adder unit and the 4th tri-valued, thermal-insulating domino adder unit all inserts first clock signal of amplitude level counterlogic 2; The 3rd clock signal input terminal of the 2nd tri-valued, thermal-insulating domino adder unit and the 4th tri-valued, thermal-insulating domino adder unit all inserts the 4th clock signal of amplitude level counterlogic 1; Wherein said first clock signal and described the 4th clock signal homophase; Described second clock signal and described the 3rd clock signal homophase, and 180 degree of phasic difference mutually of described first clock signal and described the 3rd clock signal.
The output signal of the signal output part of the described first tri-valued, thermal-insulating domino literal computing circuit is three the corresponding addend literal computing signals of addend input signal that insert with its signal input part; Be respectively the three addend literal computing signal of first addend literal computing signal, second addend literal computing signal when addend be logical one and the addend of addend when being logical zero when being logic 2; The addend literal computing signal input part that wherein said carry signal produces circuit inserts described second addend literal computing signal and described the 3rd addend literal computing signal; The addend literal computing signal input part of described one's own department or unit and signal generating circuit inserts the described first addend literal computing signal, the described second addend literal computing signal and described the 3rd addend literal computing signal; The output signal of the signal output part of the described second tri-valued, thermal-insulating domino literal computing circuit is three the corresponding summand literal computing signals of summand input signal that insert with its signal input part; Be respectively the three summand literal computing signal of first summand literal computing signal, second summand literal computing signal when summand be logical one and the summand of summand when being logical zero when being logic 2; The summand literal computing signal input part that wherein said carry signal produces circuit inserts described second summand literal computing signal and described the 3rd summand literal computing signal, and the summand literal computing signal input part of described one's own department or unit and signal generating circuit inserts the described first summand literal computing signal, the described second summand literal computing signal and described the 3rd summand literal computing signal.
The described first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module; Described literal computing module is managed by a PMOS; The 2nd PMOS pipe; The 3rd PMOS pipe; The 4th PMOS pipe; The 5th PMOS pipe; The 6th PMOS pipe; The one NMOS pipe; The 2nd NMOS pipe; The 3rd NMOS pipe; The 4th NMOS pipe; The 5th NMOS pipe; The 6th NMOS pipe and the 7th NMOS pipe are formed; The grid of the grid of described NMOS pipe and described the 4th NMOS pipe and connect and itself and connect end and be signal input part; The drain electrode of described NMOS pipe; The grid of the source electrode of described PMOS pipe and described the 3rd PMOS pipe also connects; The source electrode of described NMOS pipe is connected with the drain electrode of described the 2nd NMOS pipe; The source electrode of described the 2nd PMOS pipe is connected with the drain electrode of described the 3rd PMOS pipe; The source electrode of described the 3rd PMOS pipe; The drain electrode of the drain electrode of described the 3rd NMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th PMOS pipe; The drain electrode of described the 4th NMOS pipe; The grid of the grid of described the 6th PMOS pipe and described the 7th NMOS pipe also connects; The source electrode of described the 4th NMOS pipe is connected with the drain electrode of described the 5th NMOS pipe; The source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 6th PMOS pipe; The drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe also connects; The grid of described PMOS pipe; The drain electrode of described the 2nd PMOS pipe; The grid of described the 4th PMOS pipe; The drain electrode of described the 5th PMOS pipe; The grid of described the 2nd NMOS pipe; The source electrode of described the 3rd NMOS pipe; The source electrode of the grid of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to first clock signal input terminal; The drain electrode of described PMOS pipe; The grid of described the 2nd PMOS pipe; The drain electrode of described the 4th PMOS pipe; The grid of described the 5th PMOS pipe; The source electrode of described the 2nd NMOS pipe; The grid of described the 3rd NMOS pipe; The grid of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected to the second clock signal input part; Described waveform transformation module is managed by the 8th NMOS; The 9th NMOS pipe; The tenth NMOS pipe; The 11 NMOS pipe; The 12 NMOS pipe and the 13 NMOS pipe are formed; The drain electrode of described the 8th NMOS pipe is connected with the drain electrode of described NMOS pipe; The source electrode of described the 8th NMOS pipe is connected with the grid of described the 9th NMOS pipe; The drain electrode of described the tenth NMOS pipe is connected with the source electrode of described the 7th NMOS pipe; The source electrode of described the tenth NMOS pipe is connected with the grid of described the 11 NMOS pipe; The drain electrode of described the 12 NMOS pipe is connected with the source electrode of described the 6th PMOS pipe; The source electrode of described the 12 NMOS pipe is connected with the grid of described the 13 NMOS pipe; The grid of described the 8th NMOS pipe; The grid of the grid of described the tenth NMOS pipe and described the 12 NMOS pipe is connected to first clock signal input terminal; The source electrode of described the 9th NMOS pipe; The source electrode of the source electrode of described the 11 NMOS pipe and described the 13 NMOS pipe is connected to the second clock signal input part; The drain electrode of described the 9th NMOS pipe is first signal output part; The drain electrode of described the 11 NMOS pipe is the secondary signal output; The drain electrode of described the 13 NMOS pipe is the 3rd signal output part; The circuit structure of the described second tri-valued, thermal-insulating domino literal computing circuit is identical with the described first tri-valued, thermal-insulating domino literal computing circuit; Both differences are that the signal input part of the described first tri-valued, thermal-insulating domino literal computing circuit inserts the addend input signal; The first addend literal computing signal when first signal output part output addend of the described first tri-valued, thermal-insulating domino literal computing circuit is logical zero; The second addend literal computing signal when the secondary signal output output addend of the described first tri-valued, thermal-insulating domino literal computing circuit is logical one; The 3rd addend literal computing signal when the 3rd signal output part output addend of the described first tri-valued, thermal-insulating domino literal computing circuit is logic 2; The signal input part of the described second tri-valued, thermal-insulating domino literal computing circuit inserts the summand input signal; The first summand literal computing signal when first signal output part output summand of the described second tri-valued, thermal-insulating domino literal computing circuit is logical zero; The second summand literal computing signal when the secondary signal output output summand of the described second tri-valued, thermal-insulating domino literal computing circuit is logical one, the 3rd summand literal computing signal when the 3rd signal output part output summand of the described second tri-valued, thermal-insulating domino literal computing circuit is logic 2.
Described carry signal produces circuit and is managed by the 7th PMOS; The 8th PMOS pipe; The 14 NMOS pipe; The 15 NMOS pipe; The 16 NMOS pipe; The 17 NMOS pipe; The 18 NMOS pipe; The 19 NMOS pipe; The 20 NMOS pipe; The 21 NMOS pipe; The 22 NMOS pipe; The 23 NMOS pipe; The 24 NMOS pipe; The 25 NMOS pipe and the 26 NMOS pipe are formed; The source electrode of described the 7th PMOS pipe; The grid of described the 8th PMOS pipe; The drain electrode of described the 14 NMOS pipe; The drain electrode of described the 21 NMOS pipe; The drain electrode of the drain electrode of described the 23 NMOS pipe and described the 24 NMOS pipe is connected to the complementary high-order carry signal output that described carry signal produces circuit; The complementary high-order carry signal output of described carry signal generation circuit is the complementary high-order carry signal output of described tri-valued, thermal-insulating domino adder unit; The source electrode of described the 14 NMOS pipe; The drain electrode of described the 15 NMOS pipe; The drain electrode of described the 17 NMOS pipe is connected with the drain electrode of described the 18 NMOS pipe; The source electrode of described the 15 NMOS pipe; The drain electrode of described the 16 NMOS pipe; The source electrode of described the 17 NMOS pipe; The source electrode of described the 19 NMOS pipe; The source electrode of described the 20 NMOS pipe; The source electrode of described the 22 NMOS pipe is connected with the source electrode of described the 25 NMOS pipe; The source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 19 NMOS pipe; The source electrode of described the 21 NMOS pipe is connected with the drain electrode of described the 20 NMOS pipe; The source electrode of described the 23 NMOS pipe is connected with the drain electrode of described the 22 NMOS pipe; The source electrode of described the 24 NMOS pipe is connected with the drain electrode of described the 25 NMOS pipe; The drain electrode of the source electrode of described the 8th PMOS pipe and described the 26 NMOS pipe is connected to the high-order carry signal output that described carry signal produces circuit; The high-order carry signal output of described carry signal generation circuit is the high-order carry signal output of described tri-valued, thermal-insulating domino adder unit; The grid of described the 14 NMOS pipe is the low level carry signal input that described carry signal produces circuit; The second addend literal computing signal the when grid of the grid of described the 18 NMOS pipe and described the 20 NMOS pipe all inserts addend and is logical one; The grid of described the 15 NMOS pipe; The 3rd addend literal computing signal the when grid of the grid of described the 23 NMOS pipe and described the 24 NMOS pipe all inserts addend and is logic 2; The second summand literal computing signal the when grid of the grid of described the 19 NMOS pipe and described the 22 NMOS pipe all inserts summand and is logical one; The grid of described the 17 NMOS pipe; The 3rd summand literal computing signal the when grid of the grid of described the 21 NMOS pipe and described the 25 NMOS pipe all inserts summand and is logic 2; The drain electrode of described the 7th PMOS pipe; The grid of the source electrode of described the 16 NMOS pipe and described the 26 NMOS pipe is connected to first clock signal input terminal, the grid of described the 7th PMOS pipe; The grid of described the 16 NMOS pipe; The source electrode of the drain electrode of described the 8th PMOS pipe and described the 26 NMOS pipe is connected to the second clock signal input part.
Described one's own department or unit and signal generating circuit comprise the first control circuit that is used for control logic 1 generation; Be used for second control circuit and one's own department or unit and signal output apparatus that control logic 2 produces; Described first control circuit is managed by the 9th PMOS; The 27 NMOS pipe; The 28 NMOS pipe; The 29 NMOS pipe; The 30 NMOS pipe; The 31 NMOS pipe; The 32 NMOS pipe; The 33 NMOS pipe; The 34 NMOS pipe; The 35 NMOS pipe; The 36 NMOS pipe; The 37 NMOS pipe; The 38 NMOS pipe; The 39 NMOS pipe; The 40 NMOS pipe and the 41 NMOS pipe are formed; The source electrode of described the 9th PMOS pipe; The drain electrode of described the 27 NMOS pipe; The drain electrode of described the 30 NMOS pipe; The drain electrode of described the 32 NMOS pipe; The drain electrode of described the 34 NMOS pipe; The drain electrode of the drain electrode of described the 37 NMOS pipe and described the 39 NMOS pipe is connected to first control signal output ends; The control signal of the described first control signal output ends output logic, 1 signal; The source electrode of described the 27 NMOS pipe is connected with the drain electrode of described the 28 NMOS pipe; The source electrode of described the 28 NMOS pipe; The drain electrode of described the 29 NMOS pipe; The source electrode of described the 31 NMOS pipe is connected with the source electrode of described the 33 NMOS pipe; The source electrode of described the 29 NMOS pipe; The source electrode of described the 36 NMOS pipe is connected with the drain electrode of described the 41 NMOS pipe; The source electrode of described the 30 NMOS pipe is connected with the drain electrode of described the 31 NMOS pipe; The source electrode of described the 32 NMOS pipe is connected with the drain electrode of described the 33 NMOS pipe; The source electrode of described the 34 NMOS pipe is connected with the drain electrode of described the 35 NMOS pipe; The source electrode of described the 37 NMOS pipe is connected with the drain electrode of described the 38 NMOS pipe; The source electrode of described the 39 NMOS pipe is connected with the drain electrode of described the 40 NMOS pipe; The source electrode of described the 35 NMOS pipe; The drain electrode of described the 36 NMOS pipe; The source electrode of described the 38 NMOS pipe is connected with the source electrode of described the 40 NMOS pipe; The first addend literal computing signal the when grid of the grid of described the 27 NMOS pipe and described the 34 NMOS pipe all inserts addend and is logical zero; The second addend literal computing signal the when grid of the grid of described the 30 NMOS pipe and described the 37 NMOS pipe all inserts addend and is logical one; The 3rd addend literal computing signal the when grid of the grid of described the 32 NMOS pipe and described the 39 NMOS pipe all inserts addend and is logic 2; The second summand literal computing signal the when grid of the grid of described the 28 NMOS pipe and described the 40 NMOS pipe all inserts summand and is logical one; The first summand literal computing signal the when grid of the grid of described the 31 NMOS pipe and described the 35 NMOS pipe all inserts summand and is logical zero; The 3rd summand literal computing signal the when grid of the grid of described the 33 NMOS pipe and described the 38 NMOS pipe all inserts summand and is logic 2; Described second control circuit is managed by the tenth PMOS; The 42 NMOS pipe; The 43 NMOS pipe; The 44 NMOS pipe; The 45 NMOS pipe; The 46 NMOS pipe; The 47 NMOS pipe; The 48 NMOS pipe; The 49 NMOS pipe; The 50 NMOS pipe; The 51 NMOS pipe; The 52 NMOS pipe; The 53 NMOS pipe; The 54 NMOS pipe; The 55 NMOS pipe and the 56 NMOS pipe are formed; The source electrode of described the tenth PMOS pipe; The drain electrode of described the 42 NMOS pipe; The drain electrode of described the 46 NMOS pipe; The drain electrode of described the 48 NMOS pipe; The drain electrode of described the 50 NMOS pipe; The drain electrode of the drain electrode of described the 53 NMOS pipe and described the 55 NMOS pipe is connected to second control signal output ends; The control signal of the described second control signal output ends output logic, 2 signals; The source electrode of described the 42 NMOS pipe is connected with the drain electrode of described the 43 NMOS pipe; The source electrode of described the 43 NMOS pipe; The drain electrode of described the 44 NMOS pipe; The source electrode of described the 47 NMOS pipe is connected with the source electrode of described the 49 NMOS pipe; The source electrode of described the 44 NMOS pipe; The drain electrode of described the 45 NMOS pipe is connected with the source electrode of described the 52 NMOS pipe; The source electrode of described the 46 NMOS pipe is connected with the drain electrode of described the 47 NMOS pipe; The source electrode of described the 48 NMOS pipe is connected with the drain electrode of described the 49 NMOS pipe; The source electrode of described the 50 NMOS pipe is connected with the drain electrode of described the 51 NMOS pipe; The source electrode of described the 53 NMOS pipe is connected with the drain electrode of described the 54 NMOS pipe; The source electrode of described the 55 NMOS pipe is connected with the drain electrode of described the 56 NMOS pipe; The source electrode of described the 51 NMOS pipe; The drain electrode of described the 52 NMOS pipe; The source electrode of described the 54 NMOS pipe is connected with the source electrode of described the 56 NMOS pipe; The first addend literal computing signal the when grid of the grid of described the 42 NMOS pipe and described the 50 NMOS pipe all inserts addend and is logical zero; The second addend literal computing signal the when grid that the grid of described the 46 NMOS pipe and described the 53 NMOS manage all inserts addend and is logical one; The 3rd addend literal computing signal the when grid of the grid of described the 48 NMOS pipe and described the 55 NMOS pipe all inserts addend and is logic 2; The second summand literal computing signal the when grid of the grid of described the 43 NMOS pipe and described the 56 NMOS pipe all inserts summand and is logical one; The first summand literal computing signal the when grid of the grid of described the 47 NMOS pipe and described the 51 NMOS pipe all inserts summand and is logical zero; The 3rd summand literal computing signal the when grid that the grid of described the 49 NMOS pipe and described the 54 NMOS manage all inserts summand and is logic 2; Described one's own department or unit and signal output apparatus are managed by the 11 PMOS; The 12 PMOS pipe and the 57 NMOS pipe are formed; The grid of described the 11 PMOS pipe is connected with described first control signal output ends; The grid of described the 12 PMOS pipe is connected with described second control signal output ends; The source electrode of described the 11 PMOS pipe; The drain electrode of the source electrode of described the 12 PMOS pipe and described the 57 NMOS pipe and connect and itself and connect one's own department or unit and the signal output part of end for described one's own department or unit and signal generating circuit; One's own department or unit of described one's own department or unit and signal generating circuit and signal output part are the one's own department or unit and the signal output part of described tri-valued, thermal-insulating domino adder unit; The grid of described the 9th PMOS pipe; The grid of described the tenth PMOS pipe; The drain electrode of described the 12 PMOS pipe; The grid of described the 41 NMOS pipe; The source electrode of the grid of described the 45 NMOS pipe and described the 57 NMOS pipe is connected to the second clock signal input part; The drain electrode of described the 9th PMOS pipe; The drain electrode of described the tenth PMOS pipe; The source electrode of described 41 NMOS pipe; The grid of the source electrode of described the 45 NMOS pipe and described the 57 NMOS pipe is connected to first clock signal input terminal; The drain electrode of described the 11 PMOS pipe is connected with the 3rd clock signal input terminal; The grid of the grid of described the 29 NMOS pipe and described the 44 NMOS pipe and connect and itself and connect the complementary low level carry signal input of end for described one's own department or unit and signal generating circuit; The complementary low level carry signal input of described one's own department or unit and signal generating circuit is the complementary low level carry signal input of described tri-valued, thermal-insulating domino adder unit; The grid of the grid of described the 36 NMOS pipe and described the 52 NMOS pipe and connect and itself and connect the low level carry signal input of end for described one's own department or unit and signal generating circuit, the low level carry signal input of described one's own department or unit and signal generating circuit is the low level carry signal input of tri-valued, thermal-insulating domino adder unit.
The output signal of described adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of described adiabatic domino buffer postpones the clock cycle half.
Compared with prior art; The invention has the advantages that through with multi valued logic; Adiabatic logic and domino circuit are applied in the design of adder; At first combine the switching signal Design Theory to go out to meet the tri-valued, thermal-insulating domino adder unit of correct logic functions; This tri-valued, thermal-insulating domino adder unit is by the first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit; Carry signal produces circuit and one's own department or unit and signal generating circuit and forms; Logic function is correct; And it is simple in structure; Compare with three value adder units based on the DTCTGAL circuit design; Its number of transistors reduces about 47%; Power consumption is lower; Multidigit three value low-power consumption domino adders based on this tri-valued, thermal-insulating domino adder unit are worth conventional domino adder with respect to three of employing DC power supply; Power Cutback is about 61%, has tangible low-power consumption characteristic.
Description of drawings
Fig. 1 is the circuit theory diagrams of four three value low-power consumption domino adders;
Fig. 2 (a) is the circuit theory diagrams of tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 2 (b) is the circuit symbol figure of tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 3 (a) is the circuit diagram of the literal computing module of the first tri-valued, thermal-insulating domino literal computing circuit of tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 3 (b) is the circuit diagram of the waveform transformation module of the first tri-valued, thermal-insulating domino literal computing circuit of tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 3 (c) is the circuit symbol figure of the first tri-valued, thermal-insulating domino literal computing circuit of the tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 4 (a) is the circuit diagram that the carry signal of the tri-valued, thermal-insulating domino adder unit among the embodiment produces circuit;
Fig. 4 (b) is the circuit symbol figure that the carry signal of the tri-valued, thermal-insulating domino adder unit among the embodiment produces circuit;
Fig. 5 (a) is the circuit diagram of first control circuit of one's own department or unit and the signal generating circuit of the tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 5 (b) is the circuit diagram of second control circuit of one's own department or unit and the signal generating circuit of the tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 5 (c) is one's own department or unit and the one's own department or unit of signal generating circuit and the circuit diagram of signal output apparatus of the tri-valued, thermal-insulating domino adder unit among the embodiment;
Fig. 5 (d) is the one's own department or unit of the tri-valued, thermal-insulating domino adder unit among the embodiment and the circuit symbol figure of signal generating circuit;
Fig. 6 is the oscillogram of clock signal;
Fig. 7 is the analog waveform figure of four three value low-power consumption domino adders;
Fig. 8 is the transient state energy consumption comparison diagram of the present invention and the conventional domino adder of three values.
Embodiment
Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.
A kind of multidigit three value low-power consumption domino adders, by
nPosition tri-valued, thermal-insulating domino adder unit is formed; Tri-valued, thermal-insulating domino adder unit is provided with the addend signal input part; The summand signal input part; Low level carry signal input; Complementary low level carry signal input; High-order carry signal output; Complementary high-order carry signal output; One's own department or unit and signal output part; First clock signal input terminal; Second clock signal input part and the 3rd clock signal input terminal; The low level carry signal input of the 1st tri-valued, thermal-insulating domino adder unit inserts 0; The complementary low level carry signal input of the 1st tri-valued, thermal-insulating domino adder unit is connected with described second clock signal input part, the
kThe high-order carry signal output of position tri-valued, thermal-insulating domino adder unit and the
K+1The low level carry signal output of position tri-valued, thermal-insulating domino adder unit connects through an adiabatic domino buffer, the
kThe complementary high-order carry signal output of position tri-valued, thermal-insulating domino adder unit and the
kThe complementary low level carry signal output of+1 tri-valued, thermal-insulating domino adder unit also connects through an adiabatic domino buffer, the
jThe one's own department or unit and the signal output part of position tri-valued, thermal-insulating domino adder unit are connected with in turn
n-
jIndividual adiabatic domino buffer, the
jThe addend signal input part and the summand signal input part of position tri-valued, thermal-insulating domino adder unit all are connected with in turn
J-1 adiabatic domino buffer, wherein,
k=1,2 ...,
N-1,
j=1,2 ...,
N, m=1,2 ...,
N-1
When multidigit three value low-power consumption domino adders were made up of 4 tri-valued, thermal-insulating domino adder units, we obtained four three value low-power consumption domino adders.
Example: Figure 1 A four three-valued low-power Duominuojia instruments, the four ternary adiabatic Duominuojia method units, three-value adiabatic Duominuojia method unit is provided with addend signal input terminal summand signal input terminal, the low carry signal input terminal, the complementary low-carry signal input terminal, the high carry signal output terminal, the complementary order bit of the signal output terminal, standard and a signal output terminal, a first clock signal input terminal, a second clock signal input terminal and third clock signal input terminal, the first a three-valued adiabatic Duominuojia law unit low carry signal input access to 0, the first a three-valued adiabatic Duominuojia law unit complementary low carry signal input terminal and said second clock signal input terminal, a first three-value insulation domino text arithmetic circuit signal input terminal of the three-value adiabatic Duominuojia method unit addend signal input terminal, the access addend input signal A, the first three-value insulation domino text operation signal of the circuit respectively, and the carry output signal addend signal generating circuit and the signal input terminal and the standard signal generating circuit addend input terminal, a second insulating domino text three-value calculating circuit for the three-value signal input unit is adiabatic method Duominuojia addend signal input, augend input signal for access to B, the value of second and third insulating domino text signal output terminal of the arithmetic circuit respectively, and the carry signal generating circuit input terminal and augend signal generating circuit and a signal based augend signal input connection, the carry signal generating circuit low carry signal input and standard and signal generating circuit low carry signal input terminal and connected with it and then end the three values of adiabatic Duominuojia law unit low carry signal input terminal The first three-value insulation domino text arithmetic circuit, a second three-value insulation domino text operation circuit and the carry signal generating circuits are respectively a first clock signal input terminal and the second clock signal input terminal, the bit and signal generating circuit with the first clock signal input terminal, a second clock signal input terminal and a third clock signal input terminal, the first a three-valued adiabatic Duominuojia law unit and three three-valued adiabatic Duominuojia law unit first clock signal input have access to the amplitude level corresponding to the logical two first clock signal clk, first a three-valued adiabatic Duominuojia law unit and three three-valued adiabatic Duominuojia law unit second clock signal inputs are connected amplitude level corresponding logic 2 second clock signal
first bit ternary adiabatic method Duominuojia 3 unit and the method of three-value unit adiabatic Duominuojia third clock signal input terminal are connected to logic 1 corresponds to the amplitude level of the third clock signal
The first two three-value unit and the method of adiabatic Duominuojia four ternary adiabatic method Duominuojia unit both a first clock signal input terminal of the amplitude level corresponding to the logic connected to the second clock signal 2
No. 2 three values adiabatic domino 4 adder unit and the ternary element adiabatic method Duominuojia second clock signal input terminal are connected amplitude level corresponding to a first clock signal Logic 2 clk, the first two three-value unit and the method of adiabatic Duominuojia four three Value adiabatic Duominuojia method unit a third clock signal input terminal are connected amplitude level corresponding to a logic 1 to the fourth clock signal clk
1 , shown in Figure 6, the first clock signal and the fourth clock signal phase, a second clock signal
and the third clock signal
phase, and the first clock signal and the third clock signal clk
180 degrees out of phase, the first three values of k-bit adiabatic Duominuojia law unit High carry signal output terminal (k +1)-bit ternary adiabatic Duominuojia law unit low carry signal output via an adiabatic domino buffers are connected, the first k-bit ternary adiabatic Duominuojia law unit complementary order bit signal output terminal and the first k 1-bit ternary adiabatic Duominuojia method means the complementary low-carry signal output terminal is also via an adiabatic domino buffer connected to the j-bit ternary adiabatic Duominuojia method unit standard and the signal output terminal in turn is connected to nj adiabatic domino buffers, j-bit ternary adiabatic Duominuojia method unit addend signal input terminal and the addend input terminal are connected in this order j-1 adiabatic domino buffers, where, k = 1,2,3, j = 1,2 , 3,4.
Like Fig. 2 (a); Tri-valued, thermal-insulating domino adder unit comprises the first tri-valued, thermal-insulating domino literal computing circuit in the present embodiment; The second tri-valued, thermal-insulating domino literal computing circuit; Carry signal produces circuit; One's own department or unit and signal generating circuit; First clock signal input terminal; Second clock signal input part and the 3rd clock signal input terminal; Carry signal produces circuit and is provided with low level carry signal input; Addend literal computing signal input part; Summand literal computing signal input part; High-order carry signal output and complementary high-order carry signal output; One's own department or unit and signal generating circuit are provided with addend literal computing signal input part; Summand literal computing signal input part; Low level carry signal input; Complementary low level carry signal input and one's own department or unit and signal output part; The signal input part of the first tri-valued, thermal-insulating domino literal computing circuit is used to insert the addend input signal; The signal output part of the first tri-valued, thermal-insulating domino literal computing circuit produces the addend literal computing signal input part of circuit with carry signal respectively and the addend literal computing signal input part of one's own department or unit and signal generating circuit is connected; The signal input part of the second tri-valued, thermal-insulating domino literal computing circuit is used to insert the summand input signal; The signal output part of the second tri-valued, thermal-insulating domino literal computing circuit produces the summand literal computing signal input part of circuit with carry signal respectively and the summand literal computing signal input part of one's own department or unit and signal generating circuit is connected; The low level carry signal input that carry signal produces circuit is connected with the low level carry signal input of one's own department or unit and signal generating circuit; The first tri-valued, thermal-insulating domino literal computing circuit; The second tri-valued, thermal-insulating domino literal computing circuit and carry signal produce circuit and are connected with the second clock signal input part with first clock signal input terminal respectively, one's own department or unit and signal generating circuit respectively with first clock signal input terminal; The second clock signal input part is connected with the 3rd clock signal input terminal.The output signal of the signal output part of the first tri-valued, thermal-insulating domino literal computing circuit is three the corresponding addend literal computing signals of addend input signal that insert with its signal input part; Be respectively the three addend literal computing signal of first addend literal computing signal, second addend literal computing signal when addend be logical one and the addend of addend when being logical zero when being logic 2; Wherein the addend literal computing signal input part of carry signal generation circuit inserts the second addend literal computing signal and the 3rd addend literal computing signal; The addend literal computing signal input part of one's own department or unit and signal generating circuit inserts the first addend literal computing signal, the second addend literal computing signal and the 3rd addend literal computing signal; The output signal of the signal output part of the second tri-valued, thermal-insulating domino literal computing circuit is three the corresponding summand literal computing signals of summand input signal that insert with its signal input part; Be respectively the three summand literal computing signal of first summand literal computing signal, second summand literal computing signal when summand be logical one and the summand of summand when being logical zero when being logic 2; Wherein the summand literal computing signal input part of carry signal generation circuit inserts the second summand literal computing signal and the 3rd summand literal computing signal; The summand literal computing signal input part of one's own department or unit and signal generating circuit inserts the first summand literal computing signal, the second summand literal computing signal and the 3rd summand literal computing signal, and the circuit symbol of tri-valued, thermal-insulating domino adder unit is shown in Fig. 2 (b).
The design principle of tri-valued, thermal-insulating domino adder unit is: the insertion switch signal theory; Insertion switch variable and signal variable reach corresponding switch algebraically and signal algebraically with it in MULTI-VALUED LOGIC CIRCUIT; For the design of multivalued circuit provides reliable theoretical foundation; Can know that by the switching signal theory voltage switch in the cmos circuit can be used for controlling to the ground short circuit of output voltage signal or connects the source short circuit, and can directly control transmission output voltage signal.Three value adder truth tables are as shown in table 1, wherein
ABe the addend input signal,
BBe the summand input signal,
C InBe low level carry signal from low level,
SBe one's own department or unit and output signal,
C OutFor flowing to high-order high-order carry signal.
Table 1 three value adder truth tables
Owing to generally have only NMOS pipe or PMOS pipe in the evaluation circuit of domino circuit; Can't directly differentiate the logical one signal; So we at first need obtain tri-valued, thermal-insulating domino literal computing circuit, the input signal that makes three value adders is at first through exporting the signal that obtains needs behind the tri-valued, thermal-insulating domino literal computing circuit; Theoretical and three truth tables that are worth adders based on switching signal obtain carry signal and produce circuit and one's own department or unit and signal generating circuit then.
In the present embodiment, the first tri-valued, thermal-insulating domino literal computing circuit comprises literal computing module and waveform transformation module.Shown in Fig. 3 (a); The literal computing module is by PMOS pipe P1; The 2nd PMOS manages P2; The 3rd PMOS manages P3; The 4th PMOS manages P4; The 5th PMOS manages P5; The 6th PMOS manages P6; The one NMOS manages N1; The 2nd NMOS manages N2; The 3rd NMOS manages N3; The 4th NMOS manages N4; The 5th NMOS manages N5; The 6th NMOS pipe N6 and the 7th NMOS pipe N7 form; The grid of the grid of the one NMOS pipe N1 and the 4th NMOS pipe N4 and connect and itself and connect end and be signal input part; The drain electrode of the one NMOS pipe N1; The grid of the source electrode of the one PMOS pipe P1 and the 3rd PMOS pipe P3 also connects; The source electrode of the one NMOS pipe N1 is connected with the drain electrode of the 2nd NMOS pipe N2; The source electrode of the 2nd PMOS pipe P2 is connected with the drain electrode of the 3rd PMOS pipe P3; The source electrode of the 3rd PMOS pipe P3; The drain electrode of the drain electrode of the 3rd NMOS pipe N3 and the 7th NMOS pipe N7 also connects; The source electrode of the 4th PMOS pipe P4; The drain electrode of the 4th NMOS pipe N4; The grid of the grid of the 6th PMOS pipe P6 and the 7th NMOS pipe N7 also connects; The source electrode of the 4th NMOS pipe N4 is connected with the drain electrode of the 5th NMOS pipe N5; The source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 6th PMOS pipe P6; The drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe N6 also connects; The grid of the one PMOS pipe P1; The drain electrode of the 2nd PMOS pipe P2; The grid of the 4th PMOS pipe P4; The drain electrode of the 5th PMOS pipe P5; The grid of the 2nd NMOS pipe N2; The source electrode of the 3rd NMOS pipe N3; The source electrode of the grid of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to first clock signal input terminal; Insert the first clock signal clk; The drain electrode of the one PMOS pipe P1; The grid of the 2nd PMOS pipe P2; The drain electrode of the 4th PMOS pipe P4; The grid of the 5th PMOS pipe P5; The source electrode of the 2nd NMOS pipe N2; The grid of the 3rd NMOS pipe N3; The grid of the source electrode of the 5th NMOS pipe N5 and the 6th NMOS pipe N6 is connected to the second clock signal input part, inserts the second clock signal
Shown in Fig. 3 (b); The waveform transformation module is by the 8th NMOS pipe N8; The 9th NMOS manages N9; The tenth NMOS manages N10; The 11 NMOS manages N11; The 12 NMOS pipe N12 and the 13 NMOS pipe N13 form; The drain electrode of the 8th NMOS pipe N8 is connected with the drain electrode of NMOS pipe N1; The source electrode of the 8th NMOS pipe N8 is connected with the grid of the 9th NMOS pipe N9; The drain electrode of the tenth NMOS pipe N10 is connected with the source electrode of the 7th NMOS pipe N7; The source electrode of the tenth NMOS pipe N10 is connected with the grid of the 11 NMOS pipe N11; The drain electrode of the 12 NMOS pipe N12 is connected with the source electrode of the 6th PMOS pipe P6; The source electrode of the 12 NMOS pipe N12 is connected with the grid of the 13 NMOS pipe N13; The grid of the 8th NMOS pipe N8; The grid of the grid of the tenth NMOS pipe N10 and the 12 NMOS pipe N12 is connected to first clock signal input terminal; Insert the first clock signal clk; The source electrode of the 9th NMOS pipe N9; The source electrode of the source electrode of the 11 NMOS pipe N11 and the 13 NMOS pipe N13 is connected to the second clock signal input part, inserts the second clock signal
The drain electrode of the 9th NMOS pipe N9 is first signal output part, and the drain electrode of the 11 NMOS pipe N11 is the secondary signal output, and the drain electrode of the 13 NMOS pipe N13 is the 3rd signal output part; The circuit symbol of the first tri-valued, thermal-insulating domino literal computing circuit is shown in Fig. 3 (c); The circuit structure of the second tri-valued, thermal-insulating domino literal computing circuit is identical with the first tri-valued, thermal-insulating domino literal computing circuit; Both differences are that the signal input part of the first tri-valued, thermal-insulating domino literal computing circuit inserts addend input signal A, the first addend literal computing signal when first signal output part output addend of the first tri-valued, thermal-insulating domino literal computing circuit is logical zero
0A
0, the second addend literal computing signal when the secondary signal output output addend of the first tri-valued, thermal-insulating domino literal computing circuit is logical one
1A
1, the 3rd addend literal computing signal when the 3rd signal output part output addend of the first tri-valued, thermal-insulating domino literal computing circuit is logic 2
2A
2, the signal input part of the second tri-valued, thermal-insulating domino literal computing circuit inserts summand input signal B, the first summand literal computing signal when first signal output part output summand of the second tri-valued, thermal-insulating domino literal computing circuit is logical zero
0B
0, the second summand literal computing signal when the secondary signal output output summand of the second tri-valued, thermal-insulating domino literal computing circuit is logical one
1B
1, the 3rd summand literal computing signal when the 3rd signal output part output summand of the second tri-valued, thermal-insulating domino literal computing circuit is logic 2
2B
2
Shown in Fig. 4 (a); In the present embodiment; Carry signal produces circuit by the 7th PMOS pipe P7; The 8th PMOS manages P8; The 14 NMOS manages N14; The 15 NMOS manages N15; The 16 NMOS manages N16; The 17 NMOS manages N17; The 18 NMOS manages N18; The 19 NMOS manages N19; The 20 NMOS manages N20; The 21 NMOS manages N21; The 22 NMOS manages N22; The 23 NMOS manages N23; The 24 NMOS manages N24; The 25 NMOS pipe N25 and the 26 NMOS pipe N26 form; The source electrode of the 7th PMOS pipe P7; The grid of the 8th PMOS pipe P8; The drain electrode of the 14 NMOS pipe N14; The drain electrode of the 21 NMOS pipe N21; The drain electrode of the drain electrode of the 23 NMOS pipe N23 and the 24 NMOS pipe N24 is connected to the complementary high-order carry signal output that carry signal produces circuit; The complementary high-order carry signal output of carry signal generation circuit is the complementary high-order carry signal output of tri-valued, thermal-insulating domino adder unit, exports complementary high-order carry signal
The source electrode of the 14 NMOS pipe N14; The drain electrode of the 15 NMOS pipe N15; The drain electrode of the 17 NMOS pipe N17 is connected with the drain electrode of the 18 NMOS pipe N18; The source electrode of the 15 NMOS pipe N15; The drain electrode of the 16 NMOS pipe N16; The source electrode of the 17 NMOS pipe N17; The source electrode of the 19 NMOS pipe N19; The source electrode of the 20 NMOS pipe N20; The source electrode of the 22 NMOS pipe N22 is connected with the source electrode of the 25 NMOS pipe N25; The source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 19 NMOS pipe N19; The source electrode of the 21 NMOS pipe N21 is connected with the drain electrode of the 20 NMOS pipe N20; The source electrode of the 23 NMOS pipe N23 is connected with the drain electrode of the 22 NMOS pipe N22; The source electrode of the 24 NMOS pipe N24 is connected with the drain electrode of the 25 NMOS pipe N25; The drain electrode of the source electrode of the 8th PMOS pipe P8 and the 26 NMOS pipe N26 is connected to the high-order carry signal output that carry signal produces circuit; The high-order carry signal output of carry signal generation circuit is the high-order carry signal output of tri-valued, thermal-insulating domino adder unit, exports high-order carry signal C
Out, the grid of the 14 NMOS pipe N14 is the low level carry signal input that carry signal produces circuit, inserts low level carry signal C
In, it is 1 the second addend literal computing signal that the grid of the grid of the 18 NMOS pipe N18 and the 20 NMOS pipe N20 all inserts logical value
1A
1, it is 2 the 3rd addend literal computing signal that the grid of the grid of the 15 NMOS pipe N15, the 23 NMOS pipe N23 and the grid of the 24 NMOS pipe N24 all insert logical value
2A
2, it is 1 the second summand literal computing signal that the grid of the grid of the 19 NMOS pipe N19 and the 22 NMOS pipe N22 all inserts logical value
1B
1, it is 2 the 3rd summand literal computing signal that the grid of the grid of the 17 NMOS pipe N17, the 21 NMOS pipe N21 and the grid of the 25 NMOS pipe N25 all insert logical value
2B
2The grid of the source electrode of the drain electrode of the 7th PMOS pipe P7, the 16 NMOS pipe N16 and the 26 NMOS pipe N26 is connected to first clock signal input terminal; The source electrode of the drain electrode of the grid of the grid of the 7th PMOS pipe P7, the 16 NMOS pipe N16, the 8th PMOS pipe P8 and the 26 NMOS pipe N26 is connected to the second clock signal input part, and carry signal produces the circuit symbol of circuit shown in Fig. 4 (b).
In the present embodiment, one's own department or unit and signal generating circuit comprise the first control circuit that is used for control logic 1 and produces, second control circuit and one's own department or unit and the signal output apparatus that is used for control logic 2 generations.Shown in Fig. 5 (a); First control circuit is by the 9th PMOS pipe P9; The 27 NMOS manages N27; The 28 NMOS manages N28; The 29 NMOS manages N29; The 30 NMOS manages N30; The 31 NMOS manages N31; The 32 NMOS manages N32; The 33 NMOS manages N33; The 34 NMOS manages N34; The 35 NMOS manages N35; The 36 NMOS manages N36; The 37 NMOS manages N37; The 38 NMOS manages N38; The 39 NMOS manages N39; The 40 NMOS pipe N40 and the 41 NMOS pipe N41 form; The source electrode of the 9th PMOS pipe P9; The drain electrode of the 27 NMOS pipe N27; The drain electrode of the 30 NMOS pipe N30; The drain electrode of the 32 NMOS pipe N32; The drain electrode of the 34 NMOS pipe N34; The drain electrode of the drain electrode of the 37 NMOS pipe N37 and the 39 NMOS pipe N39 is connected to first control signal output ends, the control signal Y of the first control signal output ends output logic, 1 signal
1The source electrode of the 27 NMOS pipe N27 is connected with the drain electrode of the 28 NMOS pipe N28; The source electrode of the 28 NMOS pipe N28; The drain electrode of the 29 NMOS pipe N29; The source electrode of the 31 NMOS pipe N31 is connected with the source electrode of the 33 NMOS pipe N33; The source electrode of the 29 NMOS pipe N29; The source electrode of the 36 NMOS pipe N36 is connected with the drain electrode of the 41 NMOS pipe N41; The source electrode of the 30 NMOS pipe N30 is connected with the drain electrode of the 31 NMOS pipe N31; The source electrode of the 32 NMOS pipe N32 is connected with the drain electrode of the 33 NMOS pipe N33; The source electrode of the 34 NMOS pipe N34 is connected with the drain electrode of the 35 NMOS pipe N35; The source electrode of the 37 NMOS pipe N37 is connected with the drain electrode of the 38 NMOS pipe N38; The source electrode of the 39 NMOS pipe N39 is connected with the drain electrode of the 40 NMOS pipe N40; The source electrode of the 35 NMOS pipe N35; The drain electrode of the 36 NMOS pipe N36; The source electrode of the source electrode of the 38 NMOS pipe N38 and the 40 NMOS pipe N40 is connected, and it is 0 the first addend literal computing signal that the grid that the grid of the 27 NMOS pipe N27 and the 34 NMOS manage N34 all inserts logical value
0A
0, it is 1 the second addend literal computing signal that the grid of the grid of the 30 NMOS pipe N30 and the 37 NMOS pipe N37 all inserts logical value
1A
1, it is 2 the second addend literal computing signal that the grid of the grid of the 32 NMOS pipe N32 and the 39 NMOS pipe N39 all inserts logical value
2A
2, it is 1 the second summand literal computing signal that the grid of the grid of the 28 NMOS pipe N28 and the 40 NMOS pipe N40 all inserts logical value
1B
1, it is 0 the first summand literal computing signal that the grid of the grid of the 31 NMOS pipe N31 and the 35 NMOS pipe N35 all inserts logical value
0B
0It is 2 the 3rd summand literal computing signal that the grid of the grid of the 33 NMOS pipe N33 and the 38 NMOS pipe N38 all inserts logical value
2B
2Shown in Fig. 5 (b); Second control circuit is by the tenth PMOS pipe P10; The 42 NMOS manages N42; The 43 NMOS manages N43; The 44 NMOS manages N44; The 45 NMOS manages N45; The 46 NMOS manages N46; The 47 NMOS manages N47; The 48 NMOS manages N48; The 49 NMOS manages N49; The 50 NMOS manages N50; The 51 NMOS manages N51; The 52 NMOS manages N52; The 53 NMOS manages N53; The 54 NMOS manages N54; The 55 NMOS pipe N55 and the 56 NMOS pipe N56 form; The source electrode of the tenth PMOS pipe P10; The drain electrode of the 42 NMOS pipe N42; The drain electrode of the 46 NMOS pipe N46; The drain electrode of the 48 NMOS pipe N48; The drain electrode of the 50 NMOS pipe N50; The drain electrode of the drain electrode of the 53 NMOS pipe N53 and the 55 NMOS pipe N55 is connected to second control signal output ends, the control signal Y of the second control signal output ends output logic, 2 signals
2The source electrode of the 42 NMOS pipe N42 is connected with the drain electrode of the 43 NMOS pipe N43; The source electrode of the 43 NMOS pipe N43; The drain electrode of the 44 NMOS pipe N44; The source electrode of the 47 NMOS pipe N47 is connected with the source electrode of the 49 NMOS pipe N49; The source electrode of the 44 NMOS pipe N44; The source electrode of the 52 NMOS pipe N52 is connected with the drain electrode of the 45 NMOS pipe N45; The source electrode of the 46 NMOS pipe N46 is connected with the drain electrode of the 47 NMOS pipe N47; The source electrode of the 48 NMOS pipe N48 is connected with the drain electrode of the 49 NMOS pipe N49; The source electrode of the 50 NMOS pipe N50 is connected with the drain electrode of the 51 NMOS pipe N51; The source electrode of the 53 NMOS pipe N53 is connected with the drain electrode of the 54 NMOS pipe N54; The source electrode of the 55 NMOS pipe N55 is connected with the drain electrode of the 56 NMOS pipe N56; The source electrode of the 51 NMOS pipe N51; The drain electrode of the 52 NMOS pipe N52; The source electrode of the source electrode of the 54 NMOS pipe N54 and the 56 NMOS pipe N56 is connected, and it is 0 the first addend literal computing signal that the grid that the grid of the 42 NMOS pipe N42 and the 50 NMOS manage N50 all inserts logical value
0A
0, it is 1 the second addend literal computing signal that the grid that the grid of the 46 NMOS pipe N46 and the 53 NMOS manage N53 all inserts logical value
1A
1, it is 2 the 3rd addend literal computing signal that the grid of the grid of the 48 NMOS pipe N48 and the 55 NMOS pipe N55 all inserts logical value
2A
2, it is 1 the second summand literal computing signal that the grid of the grid of the 43 NMOS pipe N43 and the 56 NMOS pipe N56 all inserts logical value
1B
1, it is 0 the first summand literal computing signal that the grid of the grid of the 47 NMOS pipe N47 and the 51 NMOS pipe N51 all inserts logical value
0B
0, it is 2 the 3rd summand literal computing signal that the grid that the grid of the 49 NMOS pipe N49 and the 54 NMOS manage N54 all inserts logical value
2B
2Shown in Fig. 5 (c); One's own department or unit and signal output apparatus are by the 11 PMOS pipe P11; The 12 PMOS pipe P12 and the 57 NMOS pipe N57 form; The grid of the 11 PMOS pipe P11 is connected with first control signal output ends; The grid of the 12 PMOS pipe P12 is connected with second control signal output ends; The source electrode of the 11 PMOS pipe P11; The drain electrode of the source electrode of the 12 PMOS pipe P12 and the 57 NMOS pipe N57 and connect and itself and connect one's own department or unit and the signal output part of end for one's own department or unit and signal generating circuit; One's own department or unit of one's own department or unit and signal generating circuit and signal output part are the one's own department or unit and the signal output part of tri-valued, thermal-insulating domino adder unit; Output one's own department or unit and output signal S; The grid of the 9th PMOS pipe P9; The grid of the tenth PMOS pipe P10; The drain electrode of the 12 PMOS pipe P12; The grid of the 41 NMOS pipe N41; The source electrode of the grid of the 45 NMOS pipe N45 and the 57 NMOS pipe N57 is connected to the second clock signal input part; The drain electrode of the 9th PMOS pipe P9; The drain electrode of the tenth PMOS pipe P10; The source electrode of the 41 NMOS pipe N41; The grid of the source electrode of the 45 NMOS pipe N45 and the 57 NMOS pipe N57 is connected to first clock signal input terminal; Insert the first clock signal clk; The drain electrode of the 11 PMOS pipe P11 is connected with the 3rd clock signal input terminal, inserts the 3rd clock signal
The grid of the grid of the 29 NMOS pipe N29 and the 44 NMOS pipe N44 and connect and itself and connect the complementary low level carry signal input of end for one's own department or unit and signal generating circuit; The complementary low level carry signal input of one's own department or unit and signal generating circuit is the complementary low level carry signal input of tri-valued, thermal-insulating domino adder unit, inserts complementary low level carry signal
The grid of the grid of the 36 NMOS pipe N36 and the 52 NMOS pipe N52 and connect and itself and connect the low level carry signal input of end for one's own department or unit and signal generating circuit; The low level carry signal input of one's own department or unit and signal generating circuit is the low level carry signal input of tri-valued, thermal-insulating domino adder unit, inserts low level carry signal C
InThe circuit symbol of one's own department or unit and signal generating circuit is shown in Fig. 5 (d).
In the present embodiment, the design principle of adiabatic domino buffer is identical with the first tri-valued, thermal-insulating domino literal computing circuit.The output signal of wherein adiabatic domino buffer is identical with its input signal, and its input signal of the output signal ratio of adiabatic domino buffer postpones the clock cycle half, thereby guarantees the orderly output of each tri-valued, thermal-insulating domino adder unit.
In the present embodiment; After all changing by the waveform transformation module, each output signal of each output signal of the first tri-valued, thermal-insulating domino literal computing circuit Chinese words computing module and the second tri-valued, thermal-insulating domino literal computing circuit Chinese words computing module is transported to the respective end that carry signal produces circuit and one's own department or unit and signal generating circuit; The waveform transformation module is carried out waveform optimization to each output signal of literal computing module; Obtain being applicable to the gradual trapezoidal wave signal of adiabatic circuits; This gradual trapezoidal wave signal and clock phase error are minimum; Can reduce the extra power consumption that level adiabatic domino circuit in back produces because of the phase difference of signal and clock when discharging and recharging; Guarantee that circuit has correct logic, for the design of tri-valued, thermal-insulating domino complicated circuit is laid a good foundation.
Utilize Spice software, under TSMC 0.25 μ m CMOS technological parameter, four three value low-power consumption domino adders are simulated, its analog waveform figure as shown in Figure 7.Wherein logical value 0,1, and 2 corresponding level are respectively 0V, 1.25V, 2.5V; Clk
1,
Clk,
Amplitude be respectively 1.25V, 1.25V, 2.5V, 2.5V, frequency all is 20MHz; The NMOS breadth length ratio is all got 0.36 μ m/0.24 μ m, and the PMOS breadth length ratio is all got 0.72 μ m/0.24 μ m; Load capacitance is 10fF; A
3A
2A
1A
0With B
3B
2B
1B
0Be respectively addend and summand; S
3S
2S
1S
0Be four output signals, C
OutBe high-order carry signal.Analysis chart 7 can know, the logic function of this circuit and three value adder truth tables are consistent, prove to design the circuit logic function correct.
Under identical parameters, three value low-power consumption domino adders and the routine three value domino adders that adopt DC power supply are carried out the transient state energy consumption relatively, its energy consumption comparison diagram is as shown in Figure 8.The concave bottom of three value low-power consumption domino adder transient state energy consumption curves representes that energy is recovered to power clock among Fig. 8, thereby reduces circuit power consumption effectively.Through analyzing, these thermal insulation three value adders are compared Power Cutback with the routine three value domino adders of employing DC power supply about 61%, prove to design circuit low-power consumption characteristic obvious.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210248455.6A CN102832926B (en) | 2012-07-17 | 2012-07-17 | Low power consumption multiposition three-valued Domino adder |
Applications Claiming Priority (1)
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| CN201210248455.6A CN102832926B (en) | 2012-07-17 | 2012-07-17 | Low power consumption multiposition three-valued Domino adder |
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| CN102832926B CN102832926B (en) | 2015-02-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106547513A (en) * | 2016-10-13 | 2017-03-29 | 宁波大学 | Using the defence differential power consumption analysis adder of sensitive scale-up version logic |
| CN109828743A (en) * | 2019-02-01 | 2019-05-31 | 杭州嘉楠耘智信息科技有限公司 | adder carry output calculation circuit |
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| US5406506A (en) * | 1993-11-09 | 1995-04-11 | United Microelectronics Corp. | Domino adder circuit having MOS transistors in the carry evaluating paths |
| CN101241482A (en) * | 2007-09-19 | 2008-08-13 | 威盛电子股份有限公司 | Data bus inversion device and method for performing data bus inversion |
| CN101833432A (en) * | 2010-04-21 | 2010-09-15 | 宁波大学 | Tri-valued, thermal-insulating and low-power adder unit and adder |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5406506A (en) * | 1993-11-09 | 1995-04-11 | United Microelectronics Corp. | Domino adder circuit having MOS transistors in the carry evaluating paths |
| CN101241482A (en) * | 2007-09-19 | 2008-08-13 | 威盛电子股份有限公司 | Data bus inversion device and method for performing data bus inversion |
| CN101833432A (en) * | 2010-04-21 | 2010-09-15 | 宁波大学 | Tri-valued, thermal-insulating and low-power adder unit and adder |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106547513A (en) * | 2016-10-13 | 2017-03-29 | 宁波大学 | Using the defence differential power consumption analysis adder of sensitive scale-up version logic |
| CN106547513B (en) * | 2016-10-13 | 2018-11-30 | 宁波大学 | Utilize the defence differential power consumption analysis adder of sensitive scale-up version logic |
| CN109828743A (en) * | 2019-02-01 | 2019-05-31 | 杭州嘉楠耘智信息科技有限公司 | adder carry output calculation circuit |
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| CN102832926B (en) | 2015-02-04 |
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