Sharma et al., 2014 - Google Patents
Design and analysis of area and power efficient 1-bit Full Subtractor using 120nm technologySharma et al., 2014
View PDF- Document ID
- 13477173228390811919
- Author
- Sharma P
- Sharma A
- Singh R
- Publication year
- Publication venue
- International Journal of Computer Applications
External Links
Snippet
In this paper an area and power efficient 14T 1-bit Full Subtractor design has been presented by using GDI techniques. The proposed 1-bit Subtractor design consist of 7 NMOS and 7 PMOS. For difference output of 1-bit full Subtractor GDI XOR-XNOR module …
- 238000005516 engineering process 0 title abstract description 11
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Alioto et al. | Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies | |
| Raghunandan et al. | Design of high-speed hybrid full adders using FinFET 18nm technology | |
| Sharma et al. | Area efficient 1-bit comparator design by using hybridized full adder module based on PTL and GDI logic | |
| Mahendran | CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications | |
| Bisdounis et al. | A comparative study of CMOS circuit design styles for low-power high-speed VLSI circuits | |
| Sharma et al. | A novel design of voltage and temperature resilient 9-T domino logic XOR/XNOR cell | |
| Kumar et al. | Comparative analysis of D flip-flops in terms of delay and its variability | |
| Rabe et al. | Short circuit power consumption of glitches | |
| Bisdounis et al. | Short-circuit energy dissipation modeling for submicrometer CMOS gates | |
| Sharma et al. | Design and analysis of area and power efficient 1-bit Full Subtractor using 120nm technology | |
| Kukreti et al. | Performance analysis of full adder based on domino logic technique | |
| Reddy | Power comparison of CMOS and adiabatic full adder circuit | |
| Maheshwari et al. | Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach | |
| Maheshwari et al. | VHDL-based modelling approach for the digital simulation of 4-phase adiabatic logic design | |
| Khandekar et al. | LOW POWER DIGITAL DESIGN USING ENERGY RECOVERY ADIABATIC LOGIC | |
| Samanta | Power efficient VLSI inverter design using adiabatic logic and estimation of power dissipation using VLSI-EDA tool | |
| Fatemi et al. | A current-based method for short circuit power calculation under noisy input waveforms | |
| Sharma et al. | Design and analysis of power efficient PTL half subtractor using 120nm technology | |
| Ramireddy et al. | A novel power-aware and high performance full adder cell for ultra-low power designs | |
| Jain et al. | EmpowerSoC: An Open-Source Power Analysis Engine based on Qflow | |
| Mishra et al. | Design and analysis of conventional cmos and energy efficient adiabatic logic for low power VLSI application | |
| Theja et al. | Energy efficient low power high speed full adder design using hybrid logic | |
| Gavaskar et al. | Design of barrel shift registers with enhanced performance analysis for modern processors | |
| Amelifard et al. | Enhancing the efficiency of cluster voltage scaling technique for low-power application | |
| Sathe et al. | Boost logic: a high speed energy recovery circuit family |