CN102760410A - Scanning driving device and driving signal generating method thereof - Google Patents

Abstract

A scanning driving device and a driving signal generating method thereof. The scan driving device includes a multi-level scan driving unit, wherein each scan driving unit further includes a shift register and a control circuit. The shift register is used to receive the first input signal, the clock signal and the inverted signal of the clock signal, and generate the scanning signal and the first control signal accordingly. The control circuit is used to receive the second input signal, the clock signal, the inverted signal of the clock signal and the first control signal, and generate the second control signal according to the second input signal, the clock signal and the inverted signal of the clock signal.

Description

Scanning drive device and method for generating drive signal thereof

【Technical field】

The present invention relates to the technical field of organic light emitting diode displays, and in particular to a scan driving device for organic light emitting diode displays and a method for generating driving signals thereof.

【Background technique】

The pixel circuit structure of the traditional OLED display has residual charges in the dielectric layer of the driving transistor, which causes the problem of image retention (Image Retention) when the OLED display changes images. The threshold voltage compensation circuit will cause the pixel Resetting the gate voltage of the driving transistor can improve the afterimage phenomenon, but it cannot completely solve it.

【Content of invention】

The invention provides a scan driving device for improving the image sticking problem.

The invention further provides a method for generating a driving signal of a scan driving device.

The present invention provides a scan driving device, which includes a multi-level scan driving unit, wherein each scan driving unit further includes a shift register and a control circuit. The shift register is used for receiving the first input signal, the clock signal and the inversion signal of the clock signal, and generates the scan signal and the first control signal accordingly. The control circuit is used to receive the second input signal, the clock signal, the inversion signal of the clock signal and the first control signal, and generate the second control signal according to the second input signal, the clock signal and the inversion signal of the clock signal.

The present invention also proposes a method for generating a driving signal for a scanning driving device. The method for generating a driving signal includes: providing a multi-level scanning driving unit, each level of scanning driving unit includes a shift register and a control circuit; providing a clock signal and a clock signal The inversion signal of each shift register and each control circuit; provide the first input signal of each shift register, and make each shift register according to the clock signal, the inversion of the clock signal signal and the received first input signal to generate the scan signal and the first control signal; and provide the second input signal of each control circuit, and make each control circuit according to the clock signal, the inversion signal of the clock signal and the The received second input signal is used to generate a second control signal.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

【Description of drawings】

Figure 1 shows a pixel circuit of one of the pixels.

FIG. 2(A) is a pixel circuit of another pixel.

FIG. 2(B) shows another pixel circuit of another pixel.

FIG. 3 is a schematic diagram of a scan driving device according to an embodiment of the invention.

FIG. 4 illustrates one timing sequence of some signals of the scan driving device shown in FIG. 3 .

FIG. 5 is a flowchart of a method for generating a driving signal according to an embodiment of the invention.

[Description of main component symbols]

10, 20, 30: pixels

102: Drive transistor

104, 204: switching transistor

106: storage capacitor

108, 206: organic light-emitting diodes

202: Compensation circuit

300: scan drive

310, 320: scanning drive unit

312, 322: shift register

314, 324: control circuit

314-1, 324-1: Transmission Gate

314-2, 324-2: NAND gate

314-3, 324-3: first inverter

314-4, 324-4: second inverter

IN: input signal receiving end

CKA, CKB: clock receiver

SOUT: scan signal output terminal

EMOUT: control signal output terminal

401~409: Pulse

CK: clock signal

EM: control signal

EM[1], EM[2]: the first control signal

EMOUT[1], EMOUT[2]: the second control signal

E[1], E[2]: Inversion signals of the second control signal

EMOUT[1]', EMOUT[2]': the inversion signal of the inversion signal of the second control signal

OVDD: supply voltage

OVSS: reference voltage

SCAN, SCAN[1], SCAN[2]: scan signal

VDATA: data voltage

VST1: first start scan signal

VST2: second start scan signal

XCK: the inversion signal of the clock signal

S502~S508: steps

【Detailed ways】

Figure 1 shows a pixel circuit of one of the pixels. As shown in FIG. 1 , the pixel circuit of the pixel 10 includes a driving transistor 102 , a switching transistor 104 , a storage capacitor 106 and an organic light emitting diode 108 . The first end of the driving transistor 102 is electrically connected to the power supply voltage OVDD, and the second end of the driving transistor 102 is electrically connected to the reference voltage OVSS through the organic light emitting diode 108 . The storage capacitor 106 is electrically connected to the gate terminal of the driving transistor 102 and the first terminal of the driving transistor 102 . The gate terminal of the switching transistor 104 is used for receiving the scan signal SCAN, the first terminal of the switching transistor 104 is used for receiving the data voltage VDATA, and the second terminal of the switching transistor 104 is electrically connected to the gate terminal of the driving transistor 102 .

FIG. 2(A) shows a pixel circuit of another pixel. As shown in FIG. 2(A), the pixel circuit of the pixel 20 includes a compensation circuit 202 , a switch transistor 204 and an organic light emitting diode 206 . The interior of the compensation circuit 202 includes not only the driving transistor 102, the switching transistor 104 and the storage capacitor 106 of the pixel 10, but also at least one electronic element (not shown) for compensating the threshold voltage of the driving transistor 102. . The first end of the switching transistor 204 is electrically connected to the power supply voltage OVDD through the compensation circuit 202, the second end of the switching transistor 204 is electrically connected to the reference voltage OVSS through the organic light emitting diode 206, and the gate end is used to receive the control signal EM. .

The control signal EM is used to control the turn-off time of the switching transistor 204 to determine whether to allow current to pass through the driving transistor 102 in the compensation circuit 202 . When the switching transistor 204 is turned off, the driving transistor 102 in the compensation circuit 202 will not have current flow. In this way, the residual charge of the dielectric layer of the driving transistor 102 can be released, thereby improving the image sticking problem of the image.

FIG. 2(B) shows another pixel circuit of another pixel. In FIG. 2(B), the same symbols as those in FIG. 2(A) represent the same objects or signals. The pixel 30 shown in FIG. 2(B) differs from the pixel 20 shown in FIG. 2(A) in that the positions of the compensation circuit 202 and the switching transistor 204 are interchanged.

FIG. 3 is a schematic diagram of a scan driving device according to an embodiment of the invention. The scan driving device is used to drive the pixel 20 shown in FIG. 2 or the pixel 30 shown in FIG. 3 (details will be described later). Please refer to FIG. 3 , the scan driving device 300 includes a multi-level scan driving unit (shown as marks 310 and 320 ), and each scan driving unit includes a shift register (shown as marks 312 and 322 ) and A control circuit (shown as 314 and 324). Each shift register has an input signal receiving terminal IN, a clock receiving terminal CKA, a clock receiving terminal CKB, a scan signal output terminal SOUT and a control signal output terminal EMOUT. Each shift register receives the first input signal, the clock signal CK and the inversion signal XCK of the clock signal CK through its input signal receiving terminal IN, the clock receiving terminal CKA and the clock receiving terminal CKB, or through its input The signal receiving end IN, the clock receiving end CKA and the clock receiving end CKB respectively receive the first input signal, the inversion signal XCK of the clock signal CK, and the clock signal CK.

After receiving the above three signals, each shift register generates a scan signal (as indicated by SCAN[1] and SCAN[2]) and a first control signal (as indicated by EM[1]) accordingly. ] and EM[2]), and output these two signals from the scanning signal output terminal SOUT and the control signal output terminal EMOUT respectively. Each scan signal is used to provide to the compensation circuit 202 in a pixel 20 , or to the compensation circuit 202 in a pixel 30 . And each first control signal is originally used to provide to the gate terminal of the switch transistor 204 in a pixel 20, or to provide to the gate terminal of the switch transistor 204 in a pixel 30, to control the turn-off time of the corresponding switch transistor 204 .

In addition, each control circuit is used to receive the second input signal, the clock signal CK, the inversion signal XCK of the clock signal CK, and the first control signal output by the corresponding shift register, and according to the received first control signal Two input signals, the clock signal CK and the inversion signal XCK of the clock signal CK, delay the phase of the received first control signal and prolong the pulse enabling time of the received first control signal to form a second control signal. signal (as indicated by EMOUT[1] and EMOUT[2]), and accordingly generate the inversion signal of the second control signal (as indicated by E[1] and E[2]).

In this example, the scan driving unit 310 is a first-stage scan driving unit, so the first input signal received by its shift register 312 may be a first initial signal provided by a timing controller. The scan signal VST1, and the second input signal received by the control circuit 314 may be a second start scan signal VST2. The second start scan signal can also be provided by the same timing controller. In addition, the scanning driving unit 320 is a second-level scanning driving unit, and in the second-level scanning driving unit to the last-level scanning driving unit (not shown), the first input received by each shift register The signal includes the scan signal output by the previous scan driving unit, and the second input signal received by each control circuit includes an inverted signal of the second control signal output by the previous scan drive unit. In addition, it should be noted that in the scan driving device 300, the shift registers in the odd-numbered-stage scan drive units are electrically connected to the clock signal CK and the inversion signal XCK of the clock signal CK, and the shift registers in the even-numbered-stage scan drive units are electrically connected to each other. The electrical connection mode adopted by the shift register is opposite.

In addition, in this example, each control circuit includes a transmission gate (shown as 314-1 and 324-1), a NAND gate (shown as 314-2 and 324-2), a first Inverters (shown as 314-3 and 324-3) and a second inverter (shown as 314-4 and 324-4). The input terminal of each transmission gate is used to receive the corresponding second input signal, and the two control terminals of each transmission gate are respectively used to receive the clock signal CK and the inversion signal XCK of the clock signal CK, so as to obtain the clock signal according to the clock signal. CK and the inverted signal XCK of the clock signal CK determine whether to output the received second input signal. One of the input terminals of each NAND gate is used to receive the corresponding first control signal, and the other input terminal is electrically connected to the output terminal of the corresponding transmission gate to receive the output signal of the corresponding transmission gate, and accordingly to generate the corresponding second control signal. control signal. The input end of each first inverter is electrically connected to the output end of the corresponding NAND gate to receive the corresponding second control signal, and accordingly generate the corresponding inversion signal of the second control signal. The input end of each second inverter is electrically connected to the output end of the corresponding first inverter to receive the corresponding inverted signal of the second control signal, and accordingly generate the corresponding inverted signal of the second control signal. The inverse signal of the phase signal (as indicated by the labels EMOUT[1]' and EMOUT[2]'). In this example, the inverted signal of the inverted signal of each second control signal is provided to the gate of the switching transistor 204 in a pixel 20, or to the gate of the switching transistor 204 in a pixel 30. grid.

In addition, it should be noted that in the scan driving device 300, the transfer gates in the odd-numbered scan drive units are electrically connected to the clock signal CK and the inversion signal XCK of the clock signal CK in the same manner as the transmission gates in the even-number scan drive units. The electrical connection method adopted is opposite.

FIG. 4 illustrates one timing sequence of some signals of the scan driving device shown in FIG. 3 . In FIG. 4 , the same symbols as those in FIG. 3 represent the same signals. In addition, in FIG. 4, one of the pulses of the first start scanning signal VST1 is represented by a mark 401; one of the pulses of the second start scan signal VST2 is represented by a mark 402; one of the pulses of the clock signal CK is represented by a mark 403 One of the pulses; one of the pulses of the inversion signal XCK of the clock signal CK is represented by a mark 404; one of the pulses of the scanning signal SCAN[1] is represented by a mark 405; the first control signal EM[1] is represented by a mark 406 ]; one of the pulses of the first control signal EM[2] is represented by 407; one of the pulses of the second control signal EMOUT[1] is represented by 408; and the second is represented by 409 One of the pulses of the control signal EMOUT[2].

It can be seen from the sequence shown in FIG. 4 that the scan driving device 300 can delay the phase of the first control signal EM[1] output by the shift register 312 through the control circuit 314, and extend the first control signal EM[1] The pulse enabling time of is used to form the second control signal EMOUT[1]. Similarly, the scan driving device 300 can delay the phase of the first control signal EM[2] output by the shift register 322 through the control circuit 324, and prolong the pulse enabling time of the first control signal EM[2]. to form the second control signal EMOUT[2]. Since the enable time of the pulses of the second control signals EMOUT[1] and EMOUT[2] are both extended, the turn-off time of the switch transistor 204 in the corresponding pixel 20 or pixel 30 is also extended. In this way, the no-current time of the driving transistor 102 in the compensation circuit 202 corresponding to the pixel 20 or the pixel 30 can be extended, thereby prolonging the release time of the residual charge of the dielectric layer of the driving transistor 102 . In this way, the image sticking problem of the organic light emitting diode display when switching images can be improved.

In addition, it can also be known from the timing sequence shown in FIG. 4 that the pulse enable time length of the second control signals EMOUT[1] and EMOUT[2] is related to the pulse enable time length of the second start scan signal VST2. Therefore, the pulse enabling time length of both the second control signals EMOUT[1] and EMOUT[2] can be changed by adjusting the pulse enabling time length of the second start scan signal VST2.

Please refer to FIG. 3 again. Since the second control signal EMOUT[1] and its inverted signal EMOUT[1]' are in phase, either of them can be provided to the switching transistor in the corresponding pixel 20 or pixel 30. 204 gate. Similarly, since the second control signal EMOUT[2] and its inverted signal EMOUT[2]' are in the same phase, either of them can be provided to the gate of the switching transistor 204 in the corresponding pixel 20 or pixel 30 pole.

Although the above description is based on the example of the pixel circuit shown in FIG. pixel circuit, the present invention can be applied.

According to the teachings of the above-mentioned embodiments, those skilled in the art can summarize some basic steps of the driving signal generating method of the scanning driving device of the present invention, as shown in FIG. 5 . FIG. 5 is a flowchart of a method for generating a driving signal according to an embodiment of the invention. Please refer to FIG. 5, the steps of the driving signal generation method include: providing a multi-level scanning driving unit, each level of scanning driving unit includes a shift register and a control circuit (as shown in step S502); providing a clock signal and a clock signal The inverted signal of each shift register and each control circuit (as shown in step S504); provide the first input signal of each shift register, and make each shift register according to the clock signal, the inversion signal of the clock signal and the received first input signal to generate the scan signal and the first control signal (as shown in step S506); and provide the second input signal of each control circuit, and make each The control circuit generates a second control signal according to the clock signal, the inversion signal of the clock signal and the received second input signal (as shown in step S508 ).

To sum up, the main method of the present invention to solve the aforementioned problems is to use the shift register in the scan driving device of the present invention to generate the first control signal, and use the control circuit in the scan driving device to delay the first control signal. The phase of a control signal and the pulse enabling time of the first control signal are extended to form the second control signal. The first control signal is originally used to determine the no-current time of the driving transistor in the pixel. After the second control signal is obtained through the above means, the second control signal can be used instead to extend the no-current time of the driving transistor, so as to drive The discharge time of the residual charge of the dielectric layer of the transistor is prolonged. In this way, the afterimage problem of the organic light emitting diode display when switching images can be improved.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the scope of the appended patent application.

Claims (9)

1. A scan driving device comprising multi-level scan drive units, wherein each of these scan drive units further comprises: a shift register, used to receive a first input signal, a clock signal and an inverted signal of the clock signal, and generate a scan signal and a first control signal accordingly; and A control circuit for receiving a second input signal, the clock signal, the inversion signal of the clock signal and the first control signal, and according to the second input signal, the clock signal and the inversion signal of the clock signal to generate a second control signal. 2. The scanning driving device according to claim 1, wherein in the first-stage scanning driving unit, the first input signal received by the shift register includes a first start scanning signal, and The second input signal received by the control circuit includes a second start scan signal. 3 . The scan driving device according to claim 2 , wherein both the first start scan signal and the second start scan signal are provided by a timing controller. 4 . 4. The scan driving device according to claim 1, wherein the first input signal received by each shift register in the second-stage scan drive unit to the last-stage scan drive unit includes The scan signal output by the previous scan driving unit, and the second input signal received by each control circuit includes an inverted signal of the second control signal output by the previous scan drive unit. 5. The scan driving device according to claim 1, wherein each control circuit comprises: A transmission gate, the input terminal of the transmission gate is used to receive the second input signal, and the two control terminals of the transmission gate are respectively used to receive the clock signal and the inversion signal of the clock signal, so as to The inversion signal with the clock signal determines whether to output the received second input signal; A NAND gate, one of the input terminals of the NAND gate is used to receive the first control signal, and the other input terminal is electrically connected to the output terminal of the transmission gate to receive the output signal of the transmission gate, so as to generate the first control signal. 2. Control signals; a first inverter, the input end of which is electrically connected to the output end of the NAND gate to receive the second control signal, and accordingly generate an inverted signal of the second control signal; and A second inverter, the input terminal of which is electrically connected to the output terminal of the first inverter to receive the inverted signal of the second control signal, and accordingly generate the inverted signal of the inverted signal of the second control signal Signal. 6. A method for generating a driving signal for a scan driving device, the method for generating a driving signal comprising: Provide a multi-level scan drive unit, each scan drive unit includes a shift register and a control circuit; providing a clock signal and an inverted signal of the clock signal to each shift register and each control circuit; providing each shift register with a first input signal, and causing each shift register to generate a scan according to the clock signal, the inversion signal of the clock signal and the received first input signal signal and a first control signal; and A second input signal is provided to each control circuit, and each control circuit is made to generate a second control signal according to the clock signal, the inversion signal of the clock signal and the received second input signal. 7. The driving signal generation method according to claim 6, characterized in that, a first start scanning signal is used as the first input signal received by the first-level scanning drive unit, and a second start signal is used The scanning signal is used as the second input signal received by the first-level scanning driving unit. 8 . The driving signal generating method according to claim 7 , wherein both the first scan start signal and the second scan start signal are provided by a timing controller. 9. The driving signal generation method according to claim 6, wherein, from the second level of scanning driving unit to the last level of scanning driving unit, the scanning signal output by the previous level of scanning driving unit is used as the next The first input signal received by the scan driving unit of the next stage and the inversion signal of the second control signal output by the scan driving unit of the previous stage are used as the second input signal received by the scan driving unit of the next stage.

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