CN103559913A - a shift register - Google Patents

Abstract

The present invention provides a shift register, including a control signal generating circuit, and the control signal generating circuit includes: a first transistor; a second transistor, a first end of which is electrically coupled to the second end of the first transistor to form a first node, and the first node is also electrically connected to the current shift signal output end; a third transistor; a fourth transistor, a first end of which is electrically coupled to the second end of the third transistor to form a second node, and the second node is also electrically connected to a control signal; a fifth transistor; and a sixth transistor. A feedback capacitor is also included between the current shift signal output end and the shift signal output end of the next stage. The falling edge of the pulse of the next stage shift signal pulls the potential of the first node down to below the difference between the second preset voltage and a threshold voltage through the feedback capacitor. Compared with the prior art, the present invention can keep the low potential of the emission signal stable and reduce the risk of controlling the pixel switch.

Description

a shift register

technical field

The invention relates to a shift register, in particular to a shift register used for a pixel compensation circuit of an active matrix organic light emitting diode display.

Background technique

Organic light emitting diodes (Organic Light Emitting Diode, OLED) can be divided into passive matrix driving (Passive Matrix OLED, PMOLED) and active matrix driving (Active Matrix OLED, AMOLED) according to the driving method. For AMOLED, each pixel has a capacitor to store data, so that each pixel maintains a light-emitting state. Since the power consumption of AMOLED is significantly lower than that of PMOLED, and its driving method is suitable for the development of large-size and high-resolution displays, AMOLED will become the main direction of future development.

The shift register is a widely used electronic component, and it can be seen in many electronic products. To put it simply, a plurality of shift registers are generally cascaded together to form a shift register group, and an electronic signal is transmitted from the shift register of the previous stage to the shift register of the next stage. In this way, through the delay time of signal transmission in the shift register group, it is possible to make an electronic signal play a correct function at different times and different positions. In the prior art, when the AMOLED display operates the emission signal required by P-type MOS (Metal Oxide Semiconductor, Metal Oxide Semiconductor), the inverter under the P-type driving structure cannot provide a stable output at a low voltage level. This in turn increases the risk of controlling the P-type MOS. For example, the ideal voltage potential of the emission signal driving the P-type MOS is the low threshold voltage V _GL , but the actual output voltage potential may be (V _GL +V _TH ), which is one transistor higher than the above low threshold voltage Voltage, which will undoubtedly aggravate the uncertain factors of pixel control, and then affect the picture quality of the display.

In view of this, how to design a novel shift register or improve the existing shift register to ensure that the voltage potential of the transmitted signal reaches the low threshold voltage V _GL . To reduce or eliminate the phenomenon of signal potential instability is an urgent task to be solved by relevant technical personnel in the industry.

Contents of the invention

Aiming at the above-mentioned defects of the shift register used for AMOLED in the prior art, the present invention provides a novel shift register which can reduce the instability of the signal potential.

According to one aspect of the present invention, a shift register is provided, suitable for Active Matrix Organic Light Emitting Diode (AMOLED, Active Matrix Organic Light Emitting Diode) display, the shift register includes a control signal generating circuit, and the control The signal generation circuit includes:

A first transistor has a control terminal, a first terminal and a second terminal, the control terminal of the first transistor receives a previous signal, and the first terminal of the first transistor is electrically coupled to a first preset Voltage;

A second transistor has a control terminal, a first terminal and a second terminal, the control terminal of the second transistor receives a first clock signal, and the first terminal of the second transistor is electrically coupled to the first The second terminal of the transistor thus forms a first node, the second terminal of the second transistor is electrically coupled to a second predetermined voltage, wherein the second predetermined voltage is smaller than the first predetermined voltage, The first node is also electrically connected to the current shift signal output terminal;

A third transistor has a control terminal, a first terminal and a second terminal, the control terminal of the third transistor is electrically connected to the first node, and the first terminal of the third transistor is electrically coupled to the the first preset voltage;

A fourth transistor has a control terminal, a first terminal and a second terminal, the control terminal of the fourth transistor receives the previous stage signal, and the first terminal of the fourth transistor is electrically coupled to the third The second terminal of the transistor thus forms a second node, the second terminal of the fourth transistor is electrically coupled to the second predetermined voltage, wherein the second node is also electrically connected to a control signal;

A fifth transistor has a control terminal, a first terminal and a second terminal, the control terminal of the fifth transistor is electrically connected to the first node, and the first terminal of the fifth transistor is electrically coupled to the the first preset voltage, the second end of the fifth transistor is electrically connected to a subsequent signal associated with the previous signal; and

A sixth transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the sixth transistor is electrically connected to the second node, and the first terminal of the sixth transistor is electrically coupled to the The second terminal of the fifth transistor, the second terminal of the sixth transistor receives a second clock signal, a first capacitor exists between the first terminal of the sixth transistor and the second node,

A feedback capacitor is also included between the current shift signal output terminal and the next-stage shift signal output terminal, and the pulse falling edge of the next-stage shift signal passes through the feedback capacitor to transfer the first The potential of the node is pulled down to be below the difference between the second predetermined voltage and a threshold voltage, and the threshold voltage is a threshold voltage of the transistor.

In one of the embodiments, the shift register further includes a driving circuit, and the driving circuit includes: a first input terminal electrically connected to the second node for receiving the control signal; a second The input end is electrically connected to the first node, and is used to receive the current shift signal; and an output end, according to the logic operation between the control signal and the current shift signal, outputs a transmission signal to drive Organic Light Emitting Diodes.

In one embodiment, the driving circuit includes: a seventh transistor having a control terminal, a first terminal and a second terminal, the control terminal of the seventh transistor is electrically connected to the second node, the The first terminal of the seventh transistor is electrically coupled to the first preset voltage; and an eighth transistor has a control terminal, a first terminal and a second terminal, and the control terminal of the eighth transistor is electrically connected to The first node, the first terminal of the eighth transistor and the second terminal of the seventh transistor are both electrically connected to the output terminal of the driving circuit, and the second terminal of the eighth transistor is electrically coupled connected to the second preset voltage.

In one embodiment, both the seventh transistor and the eighth transistor are P-type metal oxide semiconductor transistors.

In one of the embodiments, when the second node is at a high potential and the potential of the first node is less than the difference between the second preset voltage and a threshold voltage, the seventh transistor is turned off, The eighth transistor is turned on, and the potential of the transmitting signal is equal to the second preset voltage.

In one of the embodiments, when the second node is at a low potential and the potential of the first node is equal to the first preset voltage, the seventh transistor is turned on, and the eighth transistor is turned off , the potential of the transmitting signal is equal to the first preset voltage.

In one of the embodiments, the second clock signal sequentially includes a first pulse signal, a second pulse signal and a third pulse signal, and the first clock signal sequentially includes the second pulse signal, the The third pulse signal and the first pulse signal.

In one embodiment, the first transistor to the sixth transistor are all P-type metal oxide semiconductor transistors.

According to yet another aspect of the present invention, a shift register is provided, which is suitable for an Active Matrix Organic Light Emitting Diode (AMOLED, Active Matrix Organic Light Emitting Diode) display, the shift register includes a control signal generating circuit, and the The control signal generating circuit includes:

A first transistor has a control terminal, a first terminal and a second terminal, the control terminal of the first transistor receives a previous signal, and the first terminal of the first transistor is electrically coupled to a first preset Voltage;

A second transistor has a control terminal, a first terminal and a second terminal, the control terminal of the second transistor receives a current stage signal associated with the previous stage signal, and the first terminal of the second transistor is connected to coupled to the first preset voltage, the second terminal of the second transistor is electrically connected to the second terminal of the first transistor to form a first node, and the first node is also electrically connected To the current shift signal output terminal;

A third transistor has a control terminal, a first terminal and a second terminal, the control terminal of the third transistor is electrically connected to a subsequent signal associated with the previous signal, and the first terminal of the third transistor One terminal is electrically coupled to the second terminal of the second transistor, and the second terminal of the third transistor is electrically coupled to a second preset voltage, wherein the second preset voltage is lower than the a first preset voltage;

A fourth transistor has a control terminal, a first terminal and a second terminal, the control terminal of the fourth transistor receives the previous stage signal, and the first terminal of the fourth transistor is electrically connected to a control signal, so The second end of the fourth transistor is electrically coupled to the second predetermined voltage;

A fifth transistor has a control terminal, a first terminal and a second terminal, the control terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor to form a second node, the fifth transistor The first end of the fifth transistor is electrically coupled to the control end of the second transistor, and the second end of the fifth transistor is electrically connected to a clock signal;

A sixth transistor, having a control terminal, a first terminal and a second terminal, the control terminal of the sixth transistor is electrically connected to the first node, and the first terminal of the sixth transistor is electrically coupled to the the first preset voltage, the second end of the sixth transistor is electrically connected to the first end of the fourth transistor;

A seventh transistor having a control terminal, a first terminal and a second terminal, the control terminal of the seventh transistor is electrically connected to the first node, and the first terminal of the seventh transistor is electrically coupled to the the first preset voltage, the second end of the seventh transistor is electrically connected to the first end of the fifth transistor, wherein the second end of the seventh transistor is connected to the second end of the sixth transistor A first capacitor is also included between the terminals; and

An eighth transistor has a control terminal, a first terminal and a second terminal, the control terminal of the eighth transistor is electrically connected to an inverted clock signal, and the first terminal of the eighth transistor is electrically connected to the a first preset voltage, the second end of the eighth transistor is electrically connected to the first end of the fifth transistor,

A feedback capacitor is also included between the current shift signal output terminal and the next-stage shift signal output terminal, and the pulse falling edge of the next-stage shift signal passes through the feedback capacitor to transfer the first The potential of the node is pulled down to be below the difference between the second predetermined voltage and a threshold voltage, and the threshold voltage is a threshold voltage of the transistor.

In one of the embodiments, the shift register further includes a driving circuit, and the driving circuit includes: a ninth transistor having a control terminal, a first terminal and a second terminal, and the control terminal of the ninth transistor is electrically connected to the second node to receive the control signal, the first terminal of the ninth transistor is electrically coupled to the first preset voltage; and a tenth transistor has a control terminal, a first terminal and The second end, the control end of the tenth transistor is electrically connected to the first node to receive the current shift signal, the first end of the tenth transistor is electrically equal to the second end of the ninth transistor connected to the output terminal of the driving circuit, the second terminal of the tenth transistor is electrically coupled to the second preset voltage, wherein the output terminal of the driving circuit is based on the control signal and the current shift The logical operation between the bit signals outputs an emission signal to drive the organic light emitting diode.

Using the shift register of the present invention, the first end of the second transistor is electrically coupled to the second end of the first transistor to form a first node, and the first node is electrically connected to the current shift signal output end, The first end of the fourth transistor is electrically coupled to the second end of the third transistor to form a second node, the second node is electrically connected to a control signal, and the output end of the current shift signal is connected to the next stage A feedback capacitor is also arranged between the output terminals of the shift signal. Compared with the prior art, the shift register of the present invention can couple the falling edge pulse of the shift signal of the next stage to the first node through the feedback capacitor, thereby pulling its potential down to the second preset voltage and transistor The difference between the threshold voltages is lower than the threshold voltage, so that the voltage level of the transmission signal can indeed reach the second preset voltage, so that the low potential of the transmission signal can be kept stable.

Description of drawings

Readers will have a clearer understanding of various aspects of the present invention after reading the detailed description of the present invention with reference to the accompanying drawings. in,

Fig. 1 shows the circuit structure diagram of a kind of shift register in the prior art;

Fig. 2 shows the timing waveform diagram of the main signals of the shift register of Fig. 1;

FIG. 3 shows a schematic diagram of a circuit structure of a shift register according to an embodiment of the present invention;

Fig. 4 shows the timing waveform diagram of the main signals of the shift register of Fig. 3;

Fig. 5 shows the turn-on and turn-off state diagrams of each switch tube when the shift register of Fig. 3 is on the falling edge pulse of the shift signal of the next stage; and

FIG. 6 shows a schematic diagram of a circuit structure of a shift register according to another embodiment of the present invention.

Detailed ways

In order to make the technical content disclosed in this application more detailed and complete, reference may be made to the drawings and the following various specific embodiments of the present invention, and the same symbols in the drawings represent the same or similar components. However, those skilled in the art should understand that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for schematic illustration and are not drawn according to their original scale.

The specific implementation manners of various aspects of the present invention will be further described in detail below with reference to the accompanying drawings.

FIG. 1 shows a circuit structure diagram of a shift register in the prior art, and FIG. 2 shows a timing waveform diagram of main signals of the shift register in FIG. 1 .

Referring to FIG. 1 and FIG. 2 , the existing shift register can obtain the output signal N through the input signal (N-1), CK and XCK. Wherein, N−1 represents a previous stage signal, CK represents a clock signal, and XCK represents an inverted clock signal. Those skilled in the art should understand that when taking a P-type metal oxide semiconductor transistor as an example, the control terminal of the transistor is the gate, the first terminal of the transistor may correspond to the source (or drain), and the second terminal of the transistor May correspond to drain (or source).

The control terminal of the first transistor T1 receives a previous signal (N-1). A first end of the first transistor T1 is coupled to a first preset voltage VGH. The second terminal of the first transistor T1 is connected to the first terminal of the fourth transistor T4 and the control terminal of the fifth transistor T5. The control terminal of the second transistor T2 receives the preceding signal (N−1). The first terminal of the second transistor T2 is electrically coupled to the control terminal of the third transistor T3 and the second terminal of the fifth transistor T5.

The first end of the third transistor T3 is electrically coupled to the second end of the sixth transistor T6, and the second end of the third transistor T3 is electrically connected to a clock signal CK. The control terminal of the third transistor T3 is electrically connected to the first terminal of the second transistor T2 and the second terminal of the fifth transistor T5. The control terminal of the fourth transistor T4 receives an inverted clock signal XCK. The first terminal of the fourth transistor T4 is electrically coupled to the second terminal of the first transistor T1, and the first terminal of the fourth transistor T4, the second terminal of the first transistor T1, the control terminal of the fifth transistor T5, the The control terminals of the six transistors T6 are electrically connected to the output terminal Q of the current shift signal. The second end of the fourth transistor T4 is electrically coupled to the second preset voltage VGL. For example, the first predetermined voltage VGH corresponds to a high voltage level, and the second predetermined voltage VGL corresponds to a low voltage level.

The control terminal of the fifth transistor T5 is electrically connected to the second terminal of the first transistor T1 and the first terminal of the fourth transistor T4. The second terminal of the fifth transistor T5 is electrically connected to the first terminal of the second transistor T2. Moreover, the second terminal of the fifth transistor T5, the first terminal of the second transistor T2, and the control terminal of the third transistor T3 are all electrically connected to the control signal output terminal BT. The control terminal of the sixth transistor T6 is also electrically connected to the second terminal of the first transistor T1. The first end of the sixth transistor T6 is electrically coupled to the first preset voltage VGH. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the third transistor T3. In addition, a capacitor C1 is included between the second terminal of the sixth transistor T6 and the second terminal of the fifth transistor T5. A capacitor C2 is included between the second terminal of the first transistor T1 and the second preset voltage VGL.

Combining Figure 1 and Figure 2, when the first pulse signal CLK1 and the second pulse signal CLK2 continue to be at a high level and the third pulse signal CLK3 is a negative pulse, the previous signal (N-1) controls the voltage potential of the signal output terminal BT Showing a step-wise decline. Afterwards, when the first pulse signal CLK1 is a negative pulse and the second pulse signal CLK2 and the third pulse signal CLK3 are at a high level, the voltage level of the control signal output terminal BT further drops. However, when the AMOLED display operates the emission signal required by the P-type MOS, the inverter under the P-type driving structure cannot provide a stable output at a low voltage level, thereby increasing the risk of controlling the P-type MOS. For example, the ideal voltage potential of the emission signal driving the P-type MOS is the low threshold voltage V _GL , but the actual output voltage potential may be (V _GL +V _TH ), which is one transistor higher than the above low threshold voltage Voltage, which will undoubtedly aggravate the uncertain factors of pixel control, and then affect the picture quality of the display.

In order to effectively improve or eliminate the above defects, FIG. 3 shows a schematic circuit structure diagram of a shift register according to an embodiment of the present invention, and FIG. 4 shows a timing waveform diagram of main signals of the shift register in FIG. 3 .

Referring to FIG. 3 , the shift register of the present invention includes a control signal generating circuit 10 . The control signal generating circuit 10 includes six transistors (ie, transistors T1 - T6 ) and two capacitors (ie, capacitors C1 and Cf). For example, the first transistor T1 to the sixth transistor T6 are P-type metal oxide semiconductor transistors. Certainly, in other embodiments, the first transistor T1 to the sixth transistor T6 may also be N-type MOS transistors.

Similarly, the control terminal of the first transistor T1 receives a previous signal (N−1). The first end of the first transistor T1 is electrically coupled to a first preset voltage VGH. The control end of the second transistor T2 receives a first clock signal XCK. The first terminal of the second transistor T2 is electrically coupled to the second terminal of the first transistor T1 to form a first node P1. The second end of the second transistor T2 is electrically coupled to a second preset voltage VGL. Wherein, the second preset voltage VGL is smaller than the first preset voltage VGH. The first node P1 is also electrically connected to the output terminal Q of the current shift signal.

The control end of the third transistor T3 is electrically connected to the first node P1. The first terminal of the third transistor T3 is electrically coupled to the first predetermined voltage VGH. The control terminal of the fourth transistor T4 receives the preceding signal (N−1). The first terminal of the fourth transistor T4 is electrically coupled to the second terminal of the third transistor T3 to form a second node P2. The second end of the fourth transistor T4 is electrically coupled to the second preset voltage VGL. The second node P2 is also electrically connected to a control signal output terminal BT.

The control terminal of the fifth transistor T5 is electrically connected to the first node P1. The first terminal of the fifth transistor T5 is electrically coupled to the first predetermined voltage VGH. The second end of the fifth transistor T5 is electrically connected to a subsequent signal N associated with the previous signal (N−1). The control terminal of the sixth transistor T6 is electrically connected to the second node P2. The first terminal of the sixth transistor T6 is electrically coupled to the second terminal of the fifth transistor T5. The second terminal of the sixth transistor T6 receives a second clock signal CK. There is a first capacitor C1 between the first terminal of the sixth transistor T6 and the second node P2.

It should be pointed out that, compared with the prior art, in the circuit architecture of the shift register of the present invention, there is also a connection between the current shift signal output terminal Q and the next stage shift signal output terminal (Q+1). A feedback capacitor Cf. The falling edge of the pulse of the next shift signal (Q+1) pulls down the potential of the first node P1 to the second preset voltage VGL and a threshold voltage Vth (eg, the threshold voltage of the transistor) through the feedback capacitor Cf. The difference is lower than the value, so that the voltage potential of the emission signal EM output by the driving circuit 20 can indeed reach the second preset voltage VGL, that is, the low potential of the emission signal remains stable, and avoids increasing the control risk of the pixel switch.

In a specific embodiment, the second clock signal CK sequentially includes a first pulse signal CLK1 , a second pulse signal CLK2 and a third pulse signal CLK3 . The first clock signal XCK sequentially includes a second pulse signal CLK2 , a third pulse signal CLK3 and a first pulse signal CLK1 . As shown in Figure 4, when the first pulse signal CLK1 and the second pulse signal CLK2 of the previous stage signal (N-1) are at a high level and the third pulse signal CLK3 is a negative pulse, the voltage potential of the control signal output terminal BT presents Step-type descent, as shown in Figure 2. Afterwards, when the first pulse signal CLK1 is a negative pulse and the second pulse signal CLK2 and the third pulse signal CLK3 continue to be at a high level, the voltage potential of the control signal output terminal BT further drops, and at this time the voltage of the current shift signal output terminal Q continues to Maintained at high voltage potential VGH. Next, when the second pulse signal CLK2 is a negative pulse and the first pulse signal CLK1 and the third pulse signal CLK3 continue to be at a high level, the voltage potential of the control signal output terminal BT rises stepwise, while the voltage of the current shift signal output terminal Q increases from The high voltage potential VGH drops to VGL+|Vth| in a stepwise manner. Since the feedback capacitance Cf is included between the current shift signal output terminal Q and the next stage shift signal output terminal (Q+1), when the third pulse signal CLK3 is a negative pulse and the second pulse signal CLK2 and the first pulse signal When CLK1 remains at a high level, the falling edge of the pulse of the next shift signal (Q+1) pulls down the potential of the first node P1 to the second preset voltage VGL and a threshold voltage Vth through the coupling effect of the feedback capacitor Cf The difference is below, that is, the voltage value of the first node P1 at this time is less than.

In a specific embodiment, the shift register further includes a driving circuit 20 . The driving circuit 20 includes a first input terminal, a second input terminal and an output terminal. Wherein, the first input terminal is electrically connected to the second node P2 for receiving the control signal BT. The second input terminal is electrically connected to the first node P1 for receiving the current shift signal Q. According to the logical operation between the control signal BT and the current shift signal Q, the output terminal outputs an emission signal EM to drive an organic light emitting diode (OLED). FIG. 3 also schematically draws a circuit implementation architecture of the driving circuit 20 . Specifically, the driving circuit 20 includes a seventh transistor T7 and an eighth transistor T8. The control terminal of the seventh transistor T7 is electrically connected to the second node P2 (ie, the control signal terminal BT), and the first terminal of the seventh transistor T7 is electrically coupled to the first preset voltage VGH. The control terminal of the eighth transistor T8 is electrically connected to the first node P1 (ie, the current shift signal terminal Q), and the first terminal of the eighth transistor T8 and the second terminal of the seventh transistor T7 are both electrically connected to the driving circuit 20 The output terminal of the eighth transistor T8 is electrically coupled to the second preset voltage VGL.

In actual operation, when the potential of the second node P2 is high and the potential of the first node P1 is less than the difference between the second preset voltage VGL and a threshold voltage Vth, the seventh transistor T7 is turned off, and the eighth transistor T8 is turned on , the potential of the emission signal EM is equal to the second preset voltage VGL. When the second node P2 is at a low potential and the potential of the first node P1 is equal to the first preset voltage VGH, the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, and the potential of the emission signal EM is equal to the first preset voltage VGH .

FIG. 5 is a diagram showing the on and off states of each switch tube when the shift register in FIG. 3 is on the falling edge pulse of the shift signal of the next stage.

Referring to FIG. 5 and FIG. 4, if the previous stage signal (N-1) is a high voltage potential, both transistors T1 and T4 are turned off. At this time, since the clock signals CK and XCK are also at a high voltage potential, the transistors T2 and T6 are also in an off state. In addition, when the shift signal (Q+1) of the next stage is at the falling edge of the pulse, due to the coupling effect of the feedback capacitor Cf, the first node P1 is at a low level potential, and the transistors T3 and T5 are turned on.

FIG. 6 shows a schematic diagram of a circuit structure of a shift register according to another embodiment of the present invention. Referring to FIG. 6 , the shift register includes a control signal generating circuit 30 . The control signal generating circuit 30 includes eight transistors (ie, transistors T1 - T8 ) and two capacitors (ie, capacitors C1 and Cf). For example, the first transistor T1 to the eighth transistor T8 are P-type metal oxide semiconductor transistors. Certainly, in other embodiments, the first transistor T1 to the eighth transistor T8 may also be N-type MOS transistors.

Specifically, the control terminal of the first transistor T1 receives a previous signal (N−1). A first end of the first transistor T1 is electrically coupled to a first preset voltage VGH. The control terminal of the second transistor T2 receives a current stage signal N associated with the previous stage signal (N−1). The first end of the second transistor T2 is electrically coupled to the first predetermined voltage VGH. The second terminal of the second transistor T2 is electrically connected to the second terminal of the first transistor T1 to form a first node P1, and the node P1 is also electrically connected to the output terminal Q of the current shift signal.

The control end of the third transistor T3 is electrically connected to a subsequent signal (N+1) associated with the previous signal (N−1). The first terminal of the third transistor T3 is electrically coupled to the second terminal of the second transistor T2, and the second terminal of the third transistor T3 is electrically coupled to a second preset voltage VGL. The control end of the fourth transistor T4 receives the preceding signal (N-1), the first end of the fourth transistor T4 is electrically connected to a second node P2, and the second end of the fourth transistor T4 is electrically coupled to the second node P2. Preset voltage VGL.

The control terminal of the fifth transistor T5 is electrically connected to the first terminal of the fourth transistor T4 to form a second node P2. The first terminal of the fifth transistor T5 is electrically coupled to the control terminal of the second transistor T2. The second end of the transistor T5 is electrically connected to a clock signal CK. The control end of the sixth transistor T6 is electrically connected to the first node P1, the first end of the sixth transistor T6 is electrically coupled to the first preset voltage VGH, and the second end of the sixth transistor T6 is electrically connected to the fourth The first terminal of transistor T4.

The control end of the seventh transistor T7 is electrically connected to the first node P1, the first end of the seventh transistor T7 is electrically coupled to the first preset voltage VGH, and the second end of the seventh transistor T7 is electrically connected to the fifth first terminal of transistor T5. A first capacitor C1 is further included between the second terminal of the seventh transistor T7 and the second terminal of the sixth transistor T6. The control end of the eighth transistor T8 is electrically connected to an inverted clock signal XCK, the first end of the eighth transistor T8 is electrically connected to the first preset voltage VGH, and the second end of the eighth transistor T8 is electrically connected to the first preset voltage VGH. The first terminal of five transistors T5.

Similar to Fig. 3, in this embodiment, a feedback capacitor Cf is also included between the current shift signal output terminal Q of the shift register and the next stage shift signal output terminal (Q+1), and the next stage The falling edge of the pulse of the shift signal pulls the potential of the first node P1 down to below the difference between the second preset voltage VGL and a threshold voltage Vth through the feedback capacitor Cf, so that the voltage of the emission signal EM output by the driving circuit The potential can indeed reach the second preset voltage VGL, that is, to keep the low potential of the emission signal stable, and avoid increasing the control risk of the pixel switch. Since the architecture of the driving circuit is the same as that of the driving circuit 20 in FIG. 3 , it will not be repeated here.

Using the shift register of the present invention, the first end of the second transistor is electrically coupled to the second end of the first transistor to form a first node, and the first node is electrically connected to the current shift signal output end, The first end of the fourth transistor is electrically coupled to the second end of the third transistor to form a second node, the second node is electrically connected to a control signal, and the output end of the current shift signal is connected to the next stage A feedback capacitor is also arranged between the output terminals of the shift signal. Compared with the prior art, the shift register of the present invention can couple the falling edge pulse of the shift signal of the next stage to the first node through the feedback capacitor, thereby pulling its potential down to the second preset voltage and transistor The difference between the threshold voltages is lower than the threshold voltage, so that the voltage level of the transmission signal can indeed reach the second preset voltage, so that the low potential of the transmission signal can be kept stable.

Hereinbefore, specific embodiments of the present invention have been described with reference to the accompanying drawings. However, those skilled in the art can understand that without departing from the spirit and scope of the present invention, various changes and substitutions can be made to the specific embodiments of the present invention. These changes and substitutions all fall within the scope defined by the claims of the present invention.

Claims (10)

1. A shift register suitable for an active matrix organic light emitting diode display, wherein the shift register comprises a control signal generating circuit, and the control signal generating circuit comprises:

the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor receives a preceding-stage signal, and the first end of the first transistor is electrically coupled to a first preset voltage;

a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor receives a first clock signal, the first terminal of the second transistor is electrically coupled to the second terminal of the first transistor to form a first node, the second terminal of the second transistor is electrically coupled to a second predetermined voltage, wherein the second predetermined voltage is smaller than the first predetermined voltage, and the first node is further electrically connected to the current shift signal output terminal;

a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically connected to the first node, and the first terminal of the third transistor is electrically coupled to the first predetermined voltage;

a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor receives the previous-stage signal, the first terminal of the fourth transistor is electrically coupled to the second terminal of the third transistor to form a second node, the second terminal of the fourth transistor is electrically coupled to the second predetermined voltage, and the second node is further electrically connected to a control signal;

a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is electrically coupled to the first predetermined voltage, and the second terminal of the fifth transistor is electrically connected to a post signal associated with the pre signal; and

a sixth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the sixth transistor being electrically connected to the second node, the first terminal of the sixth transistor being electrically coupled to the second terminal of the fifth transistor, the second terminal of the sixth transistor receiving a second clock signal, a first capacitor being present between the first terminal of the sixth transistor and the second node,

a feedback capacitor is further included between the current shift signal output terminal and the next shift signal output terminal, and a pulse falling edge of the next shift signal pulls down the potential of the first node to be less than a difference between the second preset voltage and a threshold voltage through the feedback capacitor, where the threshold voltage is a threshold voltage of the transistor.

2. The shift register of claim 1, further comprising a driving circuit, the driving circuit comprising:

a first input end electrically connected to the second node for receiving the control signal;

a second input end electrically connected to the first node for receiving the current shift signal; and

and the output end outputs an emission signal to drive the organic light-emitting diode according to the logic operation between the control signal and the current shift signal.

3. The shift register according to claim 2, wherein the driving circuit comprises:

a seventh transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh transistor is electrically connected to the second node, and the first terminal of the seventh transistor is electrically coupled to the first predetermined voltage;

an eighth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the eighth transistor is electrically connected to the first node, the first terminal of the eighth transistor and the second terminal of the seventh transistor are both electrically connected to the output terminal of the driving circuit, and the second terminal of the eighth transistor is electrically coupled to the second preset voltage.

4. The shift register according to claim 3, wherein the seventh transistor and the eighth transistor are both P-type metal oxide semiconductor transistors.

5. The shift register of claim 4, wherein when the second node is high and the potential of the first node is less than a difference between the second predetermined voltage and a threshold voltage, the seventh transistor is turned off, the eighth transistor is turned on, and the potential of the emission signal is equal to the second predetermined voltage.

6. The shift register according to claim 4, wherein when the second node is at a low potential and the potential of the first node is equal to the first predetermined voltage, the seventh transistor is turned on, the eighth transistor is turned off, and the potential of the emission signal is equal to the first predetermined voltage.

7. The shift register according to claim 1, wherein the second clock signal sequentially includes a first pulse signal, a second pulse signal, and a third pulse signal, and the first clock signal sequentially includes the second pulse signal, the third pulse signal, and the first pulse signal.

8. The shift register according to claim 1, wherein the first to sixth transistors are all P-type metal oxide semiconductor transistors.

9. A shift register suitable for an active matrix organic light emitting diode display, wherein the shift register comprises a control signal generating circuit, and the control signal generating circuit comprises:

the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor receives a preceding-stage signal, and the first end of the first transistor is electrically coupled to a first preset voltage;

a second transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the second transistor receives a current stage signal associated with the previous stage signal, the first terminal of the second transistor is electrically coupled to the first predetermined voltage, the second terminal of the second transistor is electrically connected to the second terminal of the first transistor to form a first node, and the first node is further electrically connected to the current shift signal output terminal;

a third transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the third transistor is electrically connected to a post signal associated with the pre signal, the first terminal of the third transistor is electrically coupled to the second terminal of the second transistor, the second terminal of the third transistor is electrically coupled to a second predetermined voltage, and the second predetermined voltage is less than the first predetermined voltage;

a fourth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fourth transistor receives the previous stage signal, the first terminal of the fourth transistor is electrically connected to a control signal, and the second terminal of the fourth transistor is electrically coupled to the second preset voltage;

a fifth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the fifth transistor is electrically connected to the first terminal of the fourth transistor to form a second node, the first terminal of the fifth transistor is electrically coupled to the control terminal of the second transistor, and the second terminal of the fifth transistor is electrically connected to a clock signal;

a sixth transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the sixth transistor is electrically connected to the first node, the first terminal of the sixth transistor is electrically coupled to the first predetermined voltage, and the second terminal of the sixth transistor is electrically connected to the first terminal of the fourth transistor;

a seventh transistor having a control terminal, a first terminal and a second terminal, wherein the control terminal of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is electrically coupled to the first predetermined voltage, the second terminal of the seventh transistor is electrically connected to the first terminal of the fifth transistor, and a first capacitor is further included between the second terminal of the seventh transistor and the second terminal of the sixth transistor; and

an eighth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the eighth transistor being electrically connected to an inverted clock signal, the first terminal of the eighth transistor being electrically connected to the first predetermined voltage, the second terminal of the eighth transistor being electrically connected to the first terminal of the fifth transistor,

a feedback capacitor is further included between the current shift signal output terminal and the next shift signal output terminal, and a pulse falling edge of the next shift signal pulls down the potential of the first node to be less than a difference between the second preset voltage and a threshold voltage through the feedback capacitor, where the threshold voltage is a threshold voltage of the transistor.

10. The shift register of claim 9, further comprising a driver circuit, the driver circuit comprising:

a ninth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the ninth transistor being electrically connected to the second node for receiving the control signal, the first terminal of the ninth transistor being electrically coupled to the first predetermined voltage; and

a tenth transistor having a control terminal, a first terminal and a second terminal, the control terminal of the tenth transistor being electrically connected to the first node for receiving the current shift signal, the first terminal of the tenth transistor and the second terminal of the ninth transistor being electrically connected to the output terminal of the driving circuit, the second terminal of the tenth transistor being electrically coupled to the second predetermined voltage,

the output end of the driving circuit outputs an emission signal according to the logical operation between the control signal and the current shift signal so as to drive the organic light-emitting diode.

Images