CN101364446B

CN101364446B - shift register

Info

Publication number: CN101364446B
Application number: CN2008101612565A
Authority: CN
Inventors: 陈文彬; 张立勋; 许哲豪
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2008-09-24
Filing date: 2008-09-24
Publication date: 2010-08-18
Anticipated expiration: 2028-09-24
Also published as: CN101364446A

Abstract

The invention discloses a shift register, which comprises a plurality of serially connected shift register units. Each shift register unit comprises a lifting circuit for providing an output signal, a lifting driving circuit and a pull-down circuit. The lifting driving circuit comprises a control circuit and a first transistor. The grid electrode of the control circuit is coupled with an input node of the lifting circuit of an earlier stage shift register, and the drain electrode of the control circuit is coupled with a second frequency signal. The grid electrode of the first transistor is coupled with the source electrode of the control circuit, the drain electrode of the first transistor is coupled with the driving signal end of the earlier stage shift register, and the source electrode of the first transistor is coupled with the input node. The pull-down circuit is used for providing the voltage at the input node of the lifting circuit to a power supply voltage. The shift register can improve the characteristic shift resistance of the transistor.

Description

Offset buffer

Technical field

The present invention relates to a kind of offset buffer, refer in particular to a kind of offset buffer that can increase transistor characteristic drift resistivity.

Background technology

Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and wherein LCD has become the display that various electronic equipments such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or the widespread use of mobile computer screen institute have the high-resolution color screen gradually.

See also Fig. 1, Fig. 1 is the functional block diagram of the LCD 10 of prior art.LCD 10 comprises a display panels 12, a gate drivers (gate driver) 14 and source electrode driver (source driver) 16.Display panels 12 comprises a plurality of pixels (pixel), and each pixel comprises three and represents the trichromatic pixel cell of RGB (RGB) 20 to constitute respectively.With the display panels 12 of one 1024 * 768 resolution, need 1024 * 768 * 3 pixel cells 20 to combine altogether.Gate drivers 14 output scanning signals make the transistor 22 of each row open in regular turn, and the pixel cell 20 of data-signal to a permutation that 16 outputs of source electrode driver simultaneously are corresponding makes it be charged to required separately voltage, to show different GTGs.After the charging of same row finished, the sweep signal that gate drivers 14 just will be listed as was closed, then gate drivers 14 again the output scanning signal transistor 22 of next column is opened, the pixel cell 20 by 16 pairs of next columns of source electrode driver discharges and recharges again.So go down in regular turn, all charge up to all pixel cells 20 of display panels 12 and finish, again since the first row charging.

In the design of present display panels, gate drivers 14 equivalences are offset buffer (shiftregister), its purpose promptly every a fixed intervals output scanning signal to display panels 12.With the display panels 12 of one 1024 * 768 resolution and the renewal frequency of 60Hz is example, and the demonstration time of each picture is about 1/60=16.67ms.So the pulse of each sweep signal is about 16.67ms/768=21.7 μ s.Source electrode driver 16 then in the time of this 21.7 μ s, discharges and recharges required voltage with pixel cell 20, to demonstrate corresponding GTG.

Yet, for the gate drivers 14 that adopts the amorphous silicon membrane technology, after lighting display panels 12, usually can cause the performance of display panels 12 to take place unusual because of bias voltage (stress) problem.See also Fig. 2, Fig. 2 announces the 5th, 410 for United States Patent (USP), the circuit diagram of No. 583 described offset buffers.Offset buffer shown in Figure 2 comprises a plurality of shift cache units, and shift cache unit is used for according to frequency signal C1, C3, input signal INPUT is postponed to export output terminal to and be output signal OUTPUT, the shift cache unit of next stage then with the output signal OUTPUT of upper level shift cache unit as input signal INPUT, postponing output again becomes output signal OUTPUT.The output signal OUTPUT of each shift cache unit is the delay output of input signal INPUT.Yet the grid and the drain electrode of the transistor 18 of shift cache unit couple, and promptly are equivalent to diode.Thus, when transistor characteristic generation drift (shift), because the grid of transistor 18-source electrode pressure reduction Vgs is fixed as zero uncontrollable its voltage-current characteristic, may cause transistor 18 leakage currents excessive and influence the electric charge preservation of node P1, cause circuit erroneous action.This can influence transistorized effective running, and is last even can cause shorten the serviceable life of offset buffer.

Summary of the invention

A purpose of the present invention is to provide a kind of offset buffer, can increase the resistivity of transistor characteristic drift.

According to above-mentioned purpose of the present invention, the invention provides a kind of offset buffer and comprise a plurality of shift cache units, these a plurality of shift cache units connect in the mode of series connection.Each shift cache unit comprises one and promotes circuit, a lifting driving circuit and a pull-down circuit.This lifting circuit is coupled to a first frequency signal, is used to provide an output signal.This lifting driving circuit is coupled to this lifting circuit, and it comprises a control circuit and a first transistor.The grid of this control circuit be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this control circuit is coupled to a second frequency signal.The grid of this first transistor is coupled to the source electrode of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit.This pull-down circuit is used to provide voltage to one supply voltage of the input node of this lifting circuit.

Another object of the present invention promotes circuit, a lifting driving circuit and a pull-down circuit for providing a kind of shift cache unit to comprise one.This lifting circuit is coupled to a first frequency signal, is used to provide an output signal.This lifting driving circuit is coupled to this lifting circuit, and it comprises a control circuit and a first transistor.The grid of this control circuit be coupled to previous stage shift cache unit the lifting circuit one the input node, the drain electrode of this control circuit is coupled to a second frequency signal.The grid of this first transistor is coupled to the source electrode of this control circuit, the drain electrode of this first transistor is coupled to a drive signal end of the previous stage shift cache unit of this each shift cache unit, and the source electrode of this first transistor is coupled to an input node of this lifting circuit.This pull-down circuit is used to provide voltage to one supply voltage of the input node of this lifting circuit.

According to the present invention, this lifting driving circuit comprises one the 3rd transistor in addition, the 3rd transistorized grid is coupled to this first frequency signal, the 3rd transistor drain is coupled to the source electrode of this control circuit, and the 3rd transistorized source electrode is coupled to a drive signal end of the next stage shift cache unit of this each shift cache unit.

According to the present invention, this lifting circuit comprises one the 4th transistor and one the 5th transistor, the 4th transistor drain is coupled to this first frequency signal, and the 4th transistorized grid is coupled to the input node of this lifting circuit, and the 4th transistorized source electrode is coupled to an output node.The 5th transistor drain is coupled to this first frequency signal, and the 5th transistorized grid is coupled to this input node, and the 5th transistorized source electrode is coupled to a drive signal end.

According to the present invention, this pull-down circuit comprises one the 6th transistor, and its drain electrode, grid and source electrode are respectively coupled to this drive signal end and this supply voltage of next stage shift cache unit of this input node, this each shift cache unit of this lifting circuit.

Description of drawings

Fig. 1 is the functional block diagram of the LCD of prior art;

Fig. 2 announces the 5th, 410 for United States Patent (USP), the circuit diagram of No. 583 described offset buffers;

Fig. 3 is the calcspar of the shift cache unit of offset buffer of the present invention;

Fig. 4 A is the circuit diagram of the shift cache unit of first embodiment of the present invention;

The circuit diagram of the shift cache unit 200 (n) of the offset buffer of second embodiment that Fig. 4 B is;

Fig. 5 is each signal of Fig. 4 A and the sequential chart of node;

Fig. 6 A is the circuit diagram of shift cache unit of the offset buffer of the third embodiment of the present invention;

Fig. 6 B is the circuit diagram of shift cache unit of the offset buffer of the fourth embodiment of the present invention.

Wherein, description of drawings:

10 LCD, 12 display panels

14 gate drivers, 16 source electrode drivers

20 pixel cells, 22 transistors

100 (n) shift cache unit T1-T6 transistor

102 promote circuit 104,204 promotes driving circuit

106 pull-down circuit CK first frequency signals

XCK second frequency signal P, Q node

OUT (n) output terminal 108 control circuits

200 (n) shift cache unit 300 (n) shift cache unit

400 (n) shift cache unit, 1081 first input ends

1,082 second output terminals 1083 the 3rd output terminal

ST (n), ST (n-1), ST (n+1) drive signal end

Embodiment

See also Fig. 3, Fig. 3 is the calcspar of the shift cache unit 100 (n) of offset buffer of the present invention.The offset buffer of present embodiment is applicable to LCD.Offset buffer comprises the shift cache unit 100 (n) of a plurality of serial connections (cascade-connected).Shift cache unit 100 (n) is used for exporting according to a drive signal impulse of the previous stage shift cache unit 100 (n-1) of a first frequency signal CK, a second frequency signal XCK4 and each shift cache unit 100 (n) sweep signal of each shift cache unit 100 (n).After first order shift cache unit 100 (1) receives (the start pulse) of a triggering initial pulse from input end ST (O), shift cache unit 100 (1) will produce output signal pulses ST (1) every a standard frequency (clockcycle) output, next, each shift cache unit 100 (n) is according to first frequency signal CK, the previous stage shift cache unit 100 (n-1) of second frequency signal XCK and each shift cache unit 100 (n) is in the drive signal impulse of drive signal end ST (n-1) output, to export this each shift cache unit 100 (n) every the mode of a standard frequency in output terminal OUT (n) output one output signal, this output signal promptly scans signal pulse, is used for exporting and opening the transistor of corresponding pixel.First frequency signal CK spends with the phasic difference mutually 180 of second frequency signal XCK.

Each shift cache unit 100 (n) comprises one and promotes circuit (pull-up circuit) 102, one lifting driving circuit (pull-up driving circuit) 104 and one pull-down circuit (pull-downcircuit) 106.Promote circuit 102 and be coupled to first frequency signal CK, be used for providing output signal in output terminal OUT (n).Promote driving circuit 104 and be used for conducting when the drive signal impulse of the shift cache unit 100 (n-1) that receives previous stage and second frequency signal XCK.Pull-down circuit 106 is used to provide a supply voltage Vss.

Promote driving circuit 104 and be coupled to node Q (n) with lifting circuit 102.As shown in Figure 3, promote driving circuit 104 and comprise a control circuit 108, a first transistor T1 and one the 3rd transistor T 3.The first input end 1081 of control circuit 108 is coupled to the input node Q (n-1) of the shift cache unit 100 (n-1) of previous stage, and second input end 1082 of control circuit 108 is coupled to second frequency signal XCK.The grid of the first transistor T1 is coupled to the 3rd output terminal 1083 of control circuit 108, and the drain electrode of the first transistor T1 is coupled to the drive signal end ST (n-1) of previous stage shift cache unit 100 (n-1), and the source electrode of the first transistor T1 is coupled to node Q (n).

See also Fig. 4 A, Fig. 4 A is the circuit diagram of the shift cache unit of the first embodiment of the present invention.Promote driving circuit 104 and be coupled to node Q (n) with lifting circuit 102.In the present embodiment, control circuit 108 comprises transistor seconds T2.The grid of transistor seconds T2 is coupled to the input node Q (n-1) of the shift cache unit 100 (n-1) of previous stage, and the drain electrode of transistor seconds T2 is coupled to second frequency signal XCK.The grid of the first transistor T1 is coupled to the source electrode of transistor seconds T2, and the drain electrode of the first transistor T1 is coupled to the drive signal end ST (n-1) of previous stage shift cache unit 100 (n-1), and the source electrode of the first transistor T1 is coupled to node Q (n).The grid of the 3rd transistor T 3 is coupled to first frequency signal CK, and the drain electrode of the 3rd transistor T 3 is coupled to the source electrode of this transistor seconds T2, and the source electrode of the 3rd transistor T 3 is coupled to the drive signal end ST (n+1) of next stage shift cache unit 100 (n+1).

Promote circuit 102 and comprise one the 4th transistor T 4 and one the 5th transistor T 5.The drain electrode of the 4th transistor T 4 is coupled to first frequency signal CK, and the grid of the 4th transistor T 4 is coupled to input node Q (n), and the source electrode of the 4th transistor T 4 is coupled to output node OUT (n).The drain electrode of the 5th transistor T 5 is coupled to first frequency signal CK, and the grid of the 5th transistor T 5 is coupled to input node Q (n), and the source electrode of the 5th transistor T 5 is coupled to drive signal end ST (n).

Pull-down circuit 106 comprises one the 6th transistor T 6, is used to provide to import the voltage of node Q (n) to supply voltage Vss.The drain electrode of the 6th transistor T 6, grid and source electrode are respectively coupled to the drive signal end ST (n+1) and the supply voltage V of input node Q (n), next stage shift cache unit 100 (n+1) _Ss

Please also refer to Fig. 3 and Fig. 5, Fig. 5 is each signal of Fig. 3 and the sequential chart of node.During period t0-t1, first frequency signal CK is in the accurate position of low-voltage V _L, make transistor T 3 close.Simultaneously, the drive signal of the drive signal end ST (n-1) of second frequency signal XCK and previous stage shift cache unit 100 (n-1) is in the accurate position of high voltage V _H, the signal potential V of the input node Q (n-1) of previous stage shift cache unit 100 (n-1) ₂Also be in the accurate position of high voltage, make transistor T 2 open (turn on) with conducting second frequency signal XCK to node P.Because the signal potential V of node Q (n-1) ₂The current potential V that can be higher than second frequency signal XCK _HSo, the current potential meeting of transistor T 1 grid (that is node P) and the current potential V of second frequency signal XCK _HApproaching.That is to say the grid of transistor T 1 and the pressure reduction V between source electrode _GSBigger, so the charging current that produces can be higher.And the drive signal of the transistor T 1 meeting conducting drive signal end ST (n-1) that is unlocked allows the current potential of node Q (n) begin to draw high gradually to voltage quasi position V because of being recharged ₂

During period t1-t2, first frequency signal CK is in the accurate position of high voltage V _H, make transistor T 3 open.Simultaneously, the drive signal of the drive signal end ST (n-1) of second frequency signal XCK and previous stage shift cache unit 100 (n-1) is in the accurate position of low-voltage, the input node Q (n-1) of previous stage shift cache unit 100 (n-1) is in the accurate position of low-voltage, make transistor T 2 close and the drive signal of the drive signal end ST (n+1) of conducting next stage shift cache unit 100 (n+1) to node P.Because this moment, the current potential of node P was in the accurate position of low-voltage, so transistor T 1, T6 are closed not conducting.But the current potential of node Q (n) can be because float (floating) be, because of transistorized capacity effect along with the rising of first frequency signal CK by accurate position V ₂Jump to accurate position V ₁When the current potential of Q (n) jumps to accurate position V ₁Afterwards, transistor T 4 and the T5 conducting first frequency signal CK that can be unlocked causes the accurate position of output terminal OUT (n) and drive signal end ST (n) output HIGH voltage.Note that at time point t1 when the drive signal of drive signal end ST (n-1) was transformed into the accurate position of low-voltage by the accurate position of high voltage, second frequency signal XCK also was transformed into the accurate position of low-voltage V simultaneously _L, the grid-source electrode pressure reduction Vgs of transistor T 1 is near 0V (this state only exists first frequency signal CK and second frequency signal XCK to be all the extremely short moment of the accurate position of low-voltage) at this moment.When the drive signal of drive signal end ST (n-1) was pulled low to Vss, the grid voltage of transistor T 1 maintained the accurate position of low-voltage V _L, and the grid voltage of transistor T 1 can that is to say that the leakage current of transistor T 1 can improve via the bulk potential adjustment via the external circuit adjustment.

After period t3, first frequency signal CK is in the accurate position of high voltage V _H, make transistor T 3 open.Simultaneously, the drive signal of the drive signal end ST (n+1) of next stage shift cache unit 100 (n+1) is in the accurate position of low-voltage, and the current potential of node P is pulled down to the accurate position of low-voltage.That is to say that another function of transistor T 3 is when shift cache unit 100 (n) when not exporting, for increasing transistor T 1 stability, so the current potential of transistor T 1 grid is left behind to reach the purpose of voltage stabilizing.

See also Fig. 4 B, Fig. 4 B is the circuit diagram of shift cache unit 300 (n) of the offset buffer of second embodiment.In first embodiment, the grid of transistor T 3 and source electrode are respectively coupled to the drive signal end ST (n+1) of first frequency signal CK and next stage shift cache unit 100 (n+1).In second embodiment shown in Fig. 4 B, the grid of transistor T 3 can be coupled to node Q, first frequency signal CK or direct supply voltage V _DDOne of them, and the source electrode of transistor T 3 can receive the drive signal end ST (n+1) of second frequency signal XCK, next stage shift cache unit 100 (n+1) or the output terminal OUT (n+1) of next stage shift cache unit 100 (n+1) one of them.

See also Fig. 6 A, the circuit diagram of the shift cache unit 300 (n) of the offset buffer of Fig. 6 A third embodiment of the present invention.The lifting driving circuit 204 of the shift cache unit 300 (n) of Fig. 6 A has lacked the 3rd transistor T 3 than the lifting driving circuit 104 of the shift cache unit 100 (n) of Fig. 4 A, and this moment, the P point voltage still can be pulled low to V via T1 _L, to reach the purpose of control T2 electric leakage.In the above-described embodiments, the grid of transistor T 2 and drain electrode are respectively coupled to the node Q (n-1) and the second frequency signal XCK of previous stage shift cache unit 100 (n-1).

See also Fig. 6 B, Fig. 6 B is the circuit diagram of shift cache unit 400 (n) of the offset buffer of the fourth embodiment of the present invention.In the present embodiment, the grid of transistor T 2 can be coupled to direct supply voltage V _DDOr the node Q (n-1) of previous stage shift cache unit 100 (n-1) one of them, and the drain electrode of transistor T 2 can be coupled to the drive signal end ST (n-1) of upper level shift cache unit 100 (n-1) or second frequency signal XCK one of them.No matter take any combination, the output of shift cache unit 400 (n) still is equivalent to the shift cache unit 300 (n) of Fig. 6 A.

The offset buffer of present embodiment can be applicable to the gate drivers of LCD.Offset buffer of the present invention uses transistor T 1 and T3 in shift cache unit, the voltage that can change transistor T 1 grid via T1 and T3 can change charging/leakage current, with the resistivity of the transistor T 1 characteristic drift that increases each shift cache unit.

The above person only is a better embodiment of the present invention, and equivalent modifications or variation that all those skilled in the art do according to spirit of the present invention all are covered by in the accompanying Claim book.

Claims

1. A shift register, characterized in that, comprising:

A plurality of shift register units, the plurality of shift register units are connected in series, each shift register unit includes:

a boosting circuit coupled to a first frequency signal for providing an output signal;

A boosting drive circuit, coupled to the boosting circuit, includes:

A control circuit, the control circuit includes a first input terminal, a second input terminal and a third output terminal, the first input terminal of the control circuit is coupled to the lifting circuit of the shift register unit of the previous stage an input node, the second input terminal of the control circuit is coupled to a second frequency signal; and

A first transistor, the gate of the first transistor is coupled to the third output terminal of the control circuit, and the drain of the first transistor is coupled to the previous stage shift register unit of each shift register unit a driving signal terminal of the first transistor, the source of the first transistor is coupled to an input node of the boosting circuit; and

A pull-down circuit is used to provide the voltage of the input node of the boost circuit to a power supply voltage.

2. The shift register according to claim 1, wherein the control circuit comprises a second transistor, the gate of the second transistor is coupled to the first input terminal of the control circuit, and the second transistor The drain of the second transistor is coupled to the second input terminal of the control circuit, and the source of the second transistor is coupled to the third output terminal of the control circuit.

3. The shift register according to claim 2, wherein the gate of the second transistor is coupled to an input node of the boost circuit of the shift register unit of the previous stage, and the drain of the second transistor The pole is coupled to a second frequency signal, and the source of the second transistor is coupled to the gate of the first transistor.

4. The shift register as claimed in claim 3, wherein the boost driving circuit further comprises a third transistor, the gate of the third transistor is coupled to the first frequency signal, and the gate of the third transistor is coupled to the first frequency signal. The drain is coupled to the source of the second transistor, and the source of the third transistor is coupled to a driving signal terminal of a next-stage shift register unit of each shift register unit.

5. The shift register as claimed in claim 3, wherein the lifting circuit comprises:

A fourth transistor, the drain of the fourth transistor is coupled to the first frequency signal, the gate of the fourth transistor is coupled to the input node of the boost circuit, and the source of the fourth transistor is coupled to an output node; and

A fifth transistor, the drain of the fifth transistor is coupled to the first frequency signal, the gate of the fifth transistor is coupled to the input node, and the source of the fifth transistor is coupled to a driving signal terminal.

6. The shift register as claimed in claim 3, wherein the phase difference between the first frequency signal and the second frequency signal is 180 degrees.

7. The shift register as claimed in claim 3, wherein the pull-down circuit comprises a sixth transistor, the drain, the gate and the source of which are respectively coupled to the input node of the boost circuit, each of the The driving signal terminal of the next stage shift register unit of a shift register unit and the power supply voltage.

8. The shift register as claimed in claim 3, wherein it is applied to a liquid crystal display.

9. A shift buffer unit, characterized in that it comprises:

a boosting circuit, coupled to a first frequency signal, for providing an output signal;

A boosting drive circuit, coupled to the boosting circuit, includes:

10. The shift register unit according to claim 9, wherein the control circuit comprises a second transistor, the gate of the second transistor is coupled to the first input terminal of the control circuit, and the second transistor The drain of the second transistor is coupled to the second input terminal of the control circuit, and the source of the second transistor is coupled to the third output terminal of the control circuit.

11. The shift register unit according to claim 10, wherein the gate of the second transistor is coupled to an input node of the boost circuit of the shift register unit of the previous stage, and the drain of the second transistor The pole is coupled to a second frequency signal, and the source of the second transistor is coupled to the gate of the first transistor.

12. The shift register unit as claimed in claim 11, wherein the boost driving circuit further comprises a third transistor, the gate of the third transistor is coupled to the first frequency signal, and the gate of the third transistor is coupled to the first frequency signal. The drain is coupled to the source of the second transistor, and the source of the third transistor is coupled to a driving signal terminal of a next-stage shift register unit of each shift register unit.

13. The shift register unit according to claim 11, wherein the lifting circuit comprises:

14. The shift register unit according to claim 11, wherein the pull-down circuit comprises a sixth transistor, the drain, the gate and the source of which are respectively coupled to the input node of the boost circuit, each of the The driving signal terminal of the next stage shift register unit of a shift register unit and the power supply voltage.

15. The shift register unit as claimed in claim 11, wherein the phase difference between the first frequency signal and the second frequency signal is 180 degrees.

16. A shift register, characterized in that, comprising:

A boosting drive circuit, coupled to the boosting circuit, includes:

A control circuit, the control circuit includes a first input terminal, a second input terminal and a third output terminal, the first input terminal of the control circuit is coupled to a first signal terminal, the first input terminal of the control circuit The two input terminals are coupled to a second signal terminal; and

A pull-down circuit is used for providing the voltage of the input node of the boost circuit to a first power supply voltage.

17. The shift register according to claim 16, wherein the control circuit comprises a second transistor, the gate of the second transistor is coupled to the first input terminal of the control circuit, and the second transistor The drain of the second transistor is coupled to the second input terminal of the control circuit, and the source of the second transistor is coupled to the third output terminal of the control circuit.

18. The shift register according to claim 17, wherein the gate of the second transistor is coupled to an input node of the boost circuit of the shift register unit of the previous stage, and the drain of the second transistor The pole is coupled to a second frequency signal, and the source of the second transistor is coupled to the gate of the first transistor.

19. The shift register according to claim 17, wherein the gate of the second transistor is coupled to an input node of the boost circuit of the previous stage of the shift register unit or a second power supply voltage .

20. The shift register as claimed in claim 19, wherein the drain of the second transistor is coupled to the drive signal terminal of the preceding shift register unit of each shift register unit, or is an output terminal coupled to the previous stage of the shift register unit of each shift register unit.

21. The shift register as claimed in claim 17, wherein the boosting drive circuit further comprises a third transistor, the gate of the third transistor is coupled to a third signal terminal, and the gate of the third transistor The drain is coupled to the source of the second transistor, and the source of the third transistor is coupled to a fourth signal terminal.

22. The shift register according to claim 21, wherein the drain of the third transistor is coupled to the third output terminal of the control circuit, and the gate of the third transistor is coupled to the first The frequency signal is either the input node of the boost circuit or the second power supply voltage.

23. The shift register as claimed in claim 22, wherein the source of the third transistor is coupled to a driving signal terminal of a next-stage shift register unit of each shift register unit, or It is a second frequency signal, or the output terminal of the next-stage shift register unit of each shift register unit.

24. The shift register as claimed in claim 16, wherein the lifting circuit comprises:

25. The shift register as claimed in claim 23, wherein the phase difference between the first frequency signal and the second frequency signal is 180 degrees.

26. The shift register as claimed in claim 23, wherein the pull-down circuit comprises a sixth transistor, the drain, the gate and the source of which are respectively coupled to the input node of the boost circuit, each of the The driving signal terminal of a next-stage shift register unit of a shift register unit and the first power supply voltage.