CN102739250B - Current Corrected Digital-to-Analog Converter - Google Patents

Abstract

The invention relates to a current correction digital-to-analog converter, which comprises a signal sending set, a digital-to-analog conversion circuit, a current compensation circuit and a voltage output end, the signal transmitting set has a plurality of control signal terminals, the digital-to-analog converting circuit has a first inverter set, a first transistor set and a resistor, the first inverter set is electrically connected to the signal transmitting set, the first transistor set is electrically connected to the first inverter set, the resistor is electrically connected to the first transistor set, the current compensation circuit has an AND gate set, a second inverter set and a second transistor set, the AND gate set is electrically connected to the control signal terminals of the signal transmission set, the second inverter set is electrically connected to the AND gate set, the second transistor set is electrically connected with the second inverter set, and the first transistor, the second transistor and the resistor are electrically connected with the voltage output end.

Description

Current Corrected Digital-to-Analog Converter

technical field

The invention relates to a digital-to-analog converter, in particular to a current-correcting digital-to-analog converter.

Background technique

The digital-to-analog converter is a conversion device that converts one or more sets of digital signals into analog signals. The analog output signal of the digital-to-analog converter is easily affected by the external environment, process drift and circuit design, resulting in signal deviation. , which will greatly affect the linearity of the analog output signal. Therefore, the differential digital-to-analog converter disclosed in US Patent No. 7242338B2 is used to improve this phenomenon. Please refer to FIG. 4. The differential digital-to-analog converter 20 has A first signal input buffer 21, a second signal input buffer 22, a plurality of bit switches 23, at least one thermometer code switch 24, a plurality of R-2R resistance structures 25, a first output terminal 26 and a first Two output terminals 27, wherein the bit switches 23 and the thermometer code switch 24 are electrically connected to the first signal input buffer 21 and the second signal input buffer 22, and each of the R-2R resistance structures 25 is electrically connected Each of the bit switch 23 and the thermometer code switch 24, the first output end 26 and the second output end 27 are electrically connected to the R-2R resistance structures 25, and the differential digital-to-analog converter 20 uses the These bit switches 23 are used to determine whether the first signal input buffer 21 and the second signal input buffer 22 respectively input a first reference signal and a second reference signal to compensate the first output terminal 26 and the second The terminal voltage of the output terminal 27, however, these R-2R resistance structures 25 are easily affected by process drift, so that the resistance value varies between R and 2R, and the mismatch between the R-2R resistance structures 25 The linearity of the differential DAC 20 will be greatly degraded.

It can be seen that the above-mentioned existing digital-to-analog converter obviously still has inconvenience and defects in structure and use, and needs to be further improved urgently. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and the general products do not have a suitable structure to solve the above-mentioned problems. This is obviously the relevant industry. urgent problem to be solved. Therefore, how to create a new type of digital-to-analog converter is one of the current important research and development topics, and it has also become a goal that the industry needs to improve.

Contents of the invention

The main purpose of the present invention is to provide a current correction digital-to-analog converter. The current compensation circuit performs current compensation on the digital-to-analog conversion circuit, and uses the first control signal terminal, the second control signal terminal, The third control signal terminal, the fourth control signal terminal and the fifth control signal terminal are used as the current compensation input terminals of the current compensation circuit, and the electric current compensation circuit and the gate group are connected by these control signal terminals. The linear connection design can effectively improve the current linearity of the digital-to-analog conversion circuit, and enable the digital-to-analog converter to achieve high-precision effects.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A current correction digital-to-analog converter proposed according to the present invention includes: a signal sending group, which has a first control signal terminal, a second control signal terminal, a third control signal terminal, and a fourth control signal terminal terminal and a fifth control signal terminal; a digital-to-analog conversion circuit, which has a first inverter group, a first transistor group and a resistor, the first inverter group is electrically connected to the signal sending group, the The first transistor group is electrically connected to the first inverter group, the resistor is electrically connected to the first transistor group; a current compensation circuit has an AND gate group, a second inverter group and a second transistor group, the AND gate group is electrically connected to the first control signal terminal, the second control signal terminal, the third control signal terminal, the fourth control signal terminal and the fifth control signal terminal of the signal sending group, the The second inverter group is electrically connected to the AND gate group, the second transistor group is electrically connected to the second inverter group; and a voltage output terminal, the first transistor group, the resistor and the second The transistor group is electrically connected to the voltage output end.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned current correction digital-to-analog converter, the AND gate group of the current compensation circuit has a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, and a fifth AND gate. gate, a sixth gate, a seventh gate, an eighth gate, a ninth gate, and a tenth gate, wherein the first gate is electrically connected to the first control signal terminal and the first gate Two control signal terminals, the second gate is electrically connected to the first control signal terminal and the third control signal terminal, the third gate is electrically connected to the fourth control signal terminal, and the fourth gate is electrically connected to The fourth control signal terminal and the fifth control signal terminal, the fifth gate is electrically connected to the third control signal terminal and the fifth control signal terminal, the sixth gate is electrically connected to the third control signal terminal and The fourth control signal end, the first AND gate has an output end, and the output end is electrically connected to the third AND gate, the seventh AND gate, the eighth AND gate, the ninth AND gate, and the tenth AND gate.

The aforementioned current correction digital-to-analog converter, wherein the second inverter group of the current compensation circuit has a first inverter, a second inverter, a third inverter, and a fourth inverter phase, a fifth inverter, a sixth inverter and a seventh inverter, the first inverter is electrically connected to the first AND gate, and the second inverter is electrically connected to the first the second AND gate, the third inverter is electrically connected to the third AND gate, the fourth inverter is electrically connected to the seventh AND gate, the fifth inverter is electrically connected to the eighth AND gate, the The sixth inverter is electrically connected to the ninth AND gate, and the seventh inverter is electrically connected to the tenth AND gate.

The aforementioned current correction digital-to-analog converter, wherein the second transistor group of the current compensation circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first Six transistors, one seventh transistor, one eighth transistor, one ninth transistor, one tenth transistor, one eleventh transistor, one twelfth transistor, one thirteenth transistor and one fourteenth transistor, the first The inverter is electrically connected to the first transistor, the second inverter is electrically connected to the second transistor, the third inverter is electrically connected to the third transistor, and the fourth inverter is electrically connected to the first transistor. Four transistors, the fifth inverter is electrically connected to the fifth transistor, the sixth inverter is electrically connected to the sixth transistor, the seventh inverter is electrically connected to the seventh transistor, and the eighth transistor is electrically connected to the seventh transistor. is electrically connected to the first transistor, the ninth transistor is electrically connected to the second transistor, the tenth transistor is electrically connected to the third transistor, the eleventh transistor is electrically connected to the fourth transistor, and the twelfth transistor is electrically connected to the fourth transistor. The fifth transistor is electrically connected, the thirteenth transistor is electrically connected to the sixth transistor, and the fourteenth transistor is electrically connected to the seventh transistor.

The aforementioned current correction digital-to-analog converter, wherein the first transistor group of the digital-to-analog conversion circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a A sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, the first transistor is electrically connected to the ninth transistor, the second transistor is electrically connected to the tenth transistor, and the first transistor is electrically connected to the tenth transistor. The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are electrically connected to the resistor and the voltage output end.

The aforementioned current correction digital-to-analog converter further has a bias voltage input terminal, and the bias voltage input terminal is electrically connected to the first transistor group and the second transistor group.

In the aforementioned current correction digital-to-analog converter, the signal sending group further has a sixth control signal terminal, a seventh control signal terminal and an eighth control signal terminal, and the inverter group is electrically connected to the sixth The control signal terminal, the seventh control signal terminal and the eighth control signal terminal.

Compared with the prior art, the present invention has obvious advantages and beneficial effects.

By means of the above-mentioned technical solution, the current correction digital-analog converter of the present invention has at least the following advantages and beneficial effects: the present invention uses the current compensation circuit to perform a current compensation operation on the digital-analog conversion circuit, and uses the first control signal terminal, The second control signal terminal, the third control signal terminal, the fourth control signal terminal and the fifth control signal terminal are used as the current compensation input terminals of the current compensation circuit, and the current compensation circuit is connected by these control signal terminals The electrical connection design of the AND gate group can effectively improve the current linearity of the digital-to-analog conversion circuit, and enable the digital-to-analog converter to achieve high-precision functions.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a circuit block diagram of a current correction digital-to-analog converter according to a preferred embodiment of the present invention.

FIG. 2 is a circuit diagram of a digital-to-analog conversion circuit of the current correction digital-to-analog converter according to a preferred embodiment of the present invention.

FIG. 3 is a circuit diagram of a current compensation circuit of the current correction digital-to-analog converter according to a preferred embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional digital-to-analog converter.

10: Current Correction Digital-to-Analog Converter

11: Signal sending group

111: The first control signal terminal 112: The second control signal terminal

113: The third control signal terminal 114: The fourth control signal terminal

115: Fifth control signal terminal 116: Sixth control signal terminal

117: The seventh control signal terminal 118: The eighth control signal terminal

12: Digital to analog conversion circuit

121: The first inverter group

1211: the first inverter 1212: the second inverter

1213: The third inverter 1214: The fourth inverter

1215: fifth inverter 1216: sixth inverter

1217: Seventh inverter 1218: Eighth inverter

122: first transistor group

122a: first transistor 122b: second transistor

122c: the third transistor 122d: the fourth transistor

122e: fifth transistor 122f: sixth transistor

122g: Seventh transistor 122h: Eighth transistor

122i: ninth transistor 122j: tenth transistor

122k: Eleventh transistor 122l: Twelfth transistor

122m: the thirteenth transistor 122n: the fourteenth transistor

122o: the fifteenth transistor 122p: the sixteenth transistor

122q: the seventeenth transistor 122r: the eighteenth transistor

123: Resistance

13: Current compensation circuit

131: And gate group

1311: first and gate 1311a: output terminal

1312: Second and Gate 1313: Third and Gate

1314: Fourth and gate 1315: Fifth and gate

1316: Sixth and Gate 1317: Seventh and Gate

1318: Eighth and gate 1319: Ninth and gate

131a: Tenth gate

132: Second inverter group

1321: the first inverter 1322 the second inverter

1323: The third inverter 1324 The fourth inverter

1325: fifth inverter 1326: sixth inverter

1327: seventh inverter

133: second transistor group

133a: first transistor 133b: second transistor

133c: the third transistor 133d: the fourth transistor

133e: fifth transistor 133f: sixth transistor

133g: the seventh transistor 133h: the eighth transistor

133i: ninth transistor 133j: tenth transistor

133k: Eleventh transistor 133l: Twelfth transistor

133m: the thirteenth transistor 133n: the fourteenth transistor

14: Voltage output terminal

15: Bias input terminal

20: Differential digital-to-analog converter

21: The first signal input buffer

22: Second signal input buffer

23: bit switch 24 thermometer code switch

25: R-2R resistor structure 26: The first output terminal

27: Second output terminal

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure, characteristics and characteristics of the current correction digital-to-analog converter proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. Its effect is described in detail below.

Please refer to Fig. 1, Fig. 2 and shown in Fig. 3, it is a preferred embodiment of the present invention, and a kind of electric current correction digital analog converter 10 comprises a signal sending group 11, a digital analog conversion circuit 12, a current compensation circuit 13 and a voltage output terminal 14, the signal sending group 11 has a first control signal terminal 111, a second control signal terminal 112, a third control signal terminal 113, a fourth control signal terminal 114 and a fifth Control signal terminal 115, the digital-to-analog conversion circuit 12 has a first inverter group 121, a first transistor group 122 and a resistor 123, the first inverter group 121 is electrically connected to the signal sending group 11, the The first transistor group 122 is electrically connected to the first inverter group 121, the resistor 123 is electrically connected to the first transistor group 122, and the current compensation circuit 13 has an AND gate group 131, a second inverter group 132 and a second transistor group 133, the AND gate group 131 is electrically connected to the first control signal terminal 111, the second control signal terminal 112, the third control signal terminal 113, the fourth control signal terminal 114 and the first control signal terminal 114 Five control signal terminals 115, the second inverter group 132 is electrically connected to the AND gate group 131, the second transistor group 133 is electrically connected to the second inverter group 132, the first transistor group 122, the first transistor group 122 The second transistor group 133 and the resistor 123 are electrically connected to the voltage output terminal 14. In this embodiment, the first transistor group 122 and the second transistor group 133 are composed of a plurality of metal-oxide-semiconductor field-effect transistors (metal-oxide- semiconductor field-effecttransistor, MOSFET).

Please refer to FIG. 2 again. In this embodiment, the signal sending group 11 further has a sixth control signal terminal 116, a seventh control signal terminal 117, and an eighth control signal terminal 118. The first inverter The group 121 is electrically connected to the sixth control signal terminal 116, the seventh control signal terminal 117 and the eighth control signal terminal 118, and each of the sending terminals can provide a digital control signal, and the first inverter group 121 has A first inverter 1211 electrically connected to the first control signal terminal 111, a second inverter 1212 electrically connected to the second control signal terminal 112, a second inverter 1212 electrically connected to the third control signal terminal 113 A third inverter 1213, a fourth inverter 1214 electrically connected to the fourth control signal terminal 114, a fifth inverter 1215 electrically connected to the fifth control signal terminal 115, a fifth inverter 1215 electrically connected to the The sixth inverter 1216 of the sixth control signal terminal 116, a seventh inverter 1217 electrically connected to the seventh control signal terminal 117, and an eighth inverter electrically connected to the eighth control signal terminal 118 1218, please refer to FIG. 2 again, the first transistor group 122 of the digital-to-analog conversion circuit 12 has a first transistor 122a, a second transistor 122b, a third transistor 122c, a fourth transistor 122d, and a fifth transistor 122e, a sixth transistor 122f, a seventh transistor 122g, an eighth transistor 122h, a ninth transistor 122i and a tenth transistor 122j, each of the inverters is electrically connected to each of the transistors, preferably, the first A transistor 122a is electrically connected to the ninth transistor 122i, the second transistor 122b is electrically connected to the tenth transistor 122j, the third transistor 122c, the fourth transistor 122d, the fifth transistor 122e, the sixth transistor 122f, and the seventh transistor 122g, the eighth transistor 122h, the ninth transistor 122i, and the tenth transistor 122j are electrically connected to the resistor 123 and the voltage output terminal 14. In this embodiment, the ninth transistor 122i and the tenth transistor 122j are used to increase Output impedance, to reduce the current fluctuation caused by the first control signal terminal 111 and the second control signal terminal 112 when the signal is switched, and reduce noise interference. In addition, the drain terminal of the ninth transistor 122i is the most significant bit (Most Significant Bit, MSB) end, the drain end of the eighth transistor 122h is the least significant bit (Least Significant Bit, LSB) end, please refer to FIG. An eleventh transistor 122k of a transistor 122a, a twelfth transistor 122l electrically connected to the second transistor 122b, a thirteenth transistor 122m electrically connected to the third transistor 122c, a thirteenth transistor 122m electrically connected to the fourth transistor The fourteenth transistor 122n of 122d is electrically connected to the fifth transistor 122e The fifteenth transistor 122o, a sixteenth transistor 122p electrically connected to the sixth transistor 122f, a seventeenth transistor 122q electrically connected to the seventh transistor 122g, and a tenth transistor electrically connected to the eighth transistor 122h Eight transistors 122r. In this embodiment, the current correction digital-to-analog converter 10 further has a bias voltage input terminal 15, and the bias voltage input terminal 15 is electrically connected to the first transistor group 122 and the second transistor group 133, The bias voltage input terminal 15 is used to generate a plurality of current sources, and the size of these current sources increases from the least significant bit end to the most significant bit end by the power of 2. In addition, these transistors can be regarded as a switches, and the switches are used to determine whether the current sources flow or not.

Please refer to FIG. 3 again, since the signal deviation of the sixth control signal terminal 116, the seventh control signal terminal 117 and the eighth control signal terminal 118 in the control signal time interval is not obvious, so this embodiment selects the The first control signal terminal 111 , the second control signal terminal 112 , the third control signal terminal 113 , the fourth control signal terminal 114 and the fifth control signal terminal 115 serve as current compensation input terminals of the current compensation circuit 13 , In this embodiment, the AND gate group 131 of the current compensation circuit 13 has a first AND gate 1311, a second AND gate 1312, a third AND gate 1313, a fourth AND gate 1314, a fifth and gate 1315, a sixth gate 1316, a seventh gate 1317, an eighth gate 1318, a ninth gate 1319 and a tenth gate 131a, wherein the first gate 1311 is electrically connected to the first A control signal terminal 111 and the second control signal terminal 112, the second AND gate 1312 is electrically connected to the first control signal terminal 111 and the third control signal terminal 113, and the third AND gate 1313 is electrically connected to the first control signal terminal 1313 Four control signal terminals 114, the fourth AND gate 1314 is electrically connected to the fourth control signal terminal 114 and the fifth control signal terminal 115, and the fifth AND gate 1315 is electrically connected to the third control signal terminal 113 and the fifth The control signal terminal 115, the sixth AND gate 1316 is electrically connected to the third control signal terminal 113 and the fourth control signal terminal 114, the first AND gate 1311 has an output terminal 1311a, and the output terminal 1311a is electrically connected to the The third sum gate 1313, the seventh sum gate 1317, the eighth sum gate 1318, the ninth sum gate 1319 and the tenth sum gate 131a, please refer to FIG. 3 again, the second inverter group 132 of the current compensation circuit 13 It has a first inverter 1321, a second inverter 1322, a third inverter 1323, a fourth inverter 1324, a fifth inverter 1325, a sixth inverter 1326 and a The seventh inverter 1327, the first inverter 1321 is electrically connected to the first AND gate 1311, the second inverter 1322 is electrically connected to the second AND gate 1312, and the third inverter 1323 is electrically connected to The third AND gate 1313 is connected, the fourth inverter 1324 is electrically connected to the seventh AND gate 1317, the fifth inverter 1325 is electrically connected to the eighth AND gate 1318, and the sixth inverter 1326 is electrically connected to the eighth AND gate 1318. The ninth AND gate 1319 is electrically connected, and the seventh inverter 1327 is electrically connected to the tenth AND gate 131a. Please refer to FIG. 3 again, the second transistor group 133 of the current compensation circuit 13 has a first transistor 133a , a second transistor 133b, a third transistor 133c, a fourth transistor 133d, a fifth transistor 133e, a sixth transistor 133f, a seventh transistor 133g, an eighth transistor 133h, a ninth transistor 133i, a Tenth transistor 133j, one eleventh transistor 133k, one twelfth transistor 133l, a thirteenth transistor 133m and a fourteenth transistor 133n, the first inverter 1321 is electrically connected to the first transistor 133a, the second inverter 1322 is electrically connected to the second transistor 133b, the first Three inverters 1323 are electrically connected to the third transistor 133c, the fourth inverter 1324 is electrically connected to the fourth transistor 133d, the fifth inverter 1325 is electrically connected to the fifth transistor 133e, and the sixth inverter The inverter 1326 is electrically connected to the sixth transistor 133f, the seventh inverter 1327 is electrically connected to the seventh transistor 133g, the eighth transistor 133h is electrically connected to the first transistor 133a, and the ninth transistor 133i is electrically connected The second transistor 133b, the tenth transistor 133j is electrically connected to the third transistor 133c, the eleventh transistor 133k is electrically connected to the fourth transistor 133d, the twelfth transistor 133l is electrically connected to the fifth transistor 133e, The thirteenth transistor 133m is electrically connected to the sixth transistor 133f, and the fourteenth transistor 133n is electrically connected to the seventh transistor 133g. After the current compensation of the current compensation circuit 13, the current correction digital-analog converter 10 outputs The integrated non-linearity (Integrated Non-linearity, INL) and differential non-linearity (Differential Non-linearity, DNL) of the bit can both be lower than 0.5LSB.

The present invention uses the first control signal terminal 111, the second control signal terminal 112, the third control signal terminal 113, the fourth control signal terminal 114 and the fifth control signal terminal 115 as the current of the current compensation circuit 13 The compensation input terminal is designed to electrically connect the control signal terminals with the AND gate group 131 of the current compensation circuit 13, so that the integrated non-linearity (Integrated Non-linearity, INL) generated by the digital-to-analog conversion circuit 12 ) and differential non-linearity (Differential Non-linearity, DNL) can be lower than 0.5LSB, to meet the high precision, high linearity of the current correction digital analog converter 10 requirements.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solution of the present invention.

Claims (3)

1. A current correction digital-to-analog converter, characterized in that it comprises: A signal sending group, which has a first control signal terminal, a second control signal terminal, a third control signal terminal, a fourth control signal terminal and a fifth control signal terminal; A digital-to-analog conversion circuit, which has a first inverter group, a first transistor group and a resistor, the first inverter group is electrically connected to the signal sending group, and the first transistor group is electrically connected to the first transistor group an inverter group, the resistor is electrically connected to the first transistor group; A current compensation circuit, which has an AND gate group, a second inverter group, and a second transistor group, and the AND gate group is electrically connected to the first control signal terminal and the second control signal terminal of the signal sending group terminal, the third control signal terminal, the fourth control signal terminal and the fifth control signal terminal, the second inverter group is electrically connected to the AND gate group, and the second transistor group is electrically connected to the second inverter banks; and a voltage output terminal, the first transistor group, the resistor and the second transistor group are electrically connected to the voltage output terminal; Wherein, the AND gate group has a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, a An eighth and gate, a ninth and a tenth and gate, wherein the first and gate are electrically connected to the first control signal terminal and the second control signal terminal, and the second and gate are electrically connected to the first A control signal terminal and the third control signal terminal, the third gate is electrically connected to the fourth control signal terminal, the fourth gate is electrically connected to the fourth control signal terminal and the fifth control signal terminal, the first The fifth AND gate is electrically connected to the third control signal end and the fifth control signal end, the sixth AND gate is electrically connected to the third control signal end and the fourth control signal end, and the first AND gate has an output The output terminal is electrically connected to the third and gate, the seventh and gate, the eighth and gate, the ninth and gate and the tenth and gate; The second inverter group has a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and A seventh inverter, the first inverter is electrically connected to the first AND gate, the second inverter is electrically connected to the second AND gate, and the third inverter is electrically connected to the third AND gate gate, the fourth inverter is electrically connected to the seventh AND gate, the fifth inverter is electrically connected to the eighth AND gate, the sixth inverter is electrically connected to the ninth AND gate, and the seventh The inverter is electrically connected to the tenth gate; The second transistor group has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor , a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, the first inverter is electrically connected to the first transistor, and the second inverter electrically connected to the second transistor, the third inverter electrically connected to the third transistor, the fourth inverter electrically connected to the fourth transistor, the fifth inverter electrically connected to the fifth transistor, The sixth inverter is electrically connected to the sixth transistor, the seventh inverter is electrically connected to the seventh transistor, the eighth transistor is electrically connected to the first transistor, and the ninth transistor is electrically connected to the second transistor. Transistors, the tenth transistor is electrically connected to the third transistor, the eleventh transistor is electrically connected to the fourth transistor, the twelfth transistor is electrically connected to the fifth transistor, and the thirteenth transistor is electrically connected to the thirteenth transistor six transistors, the fourteenth transistor is electrically connected to the seventh transistor; The first transistor group has a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor and a tenth transistor, the first transistor is electrically connected to the ninth transistor, the second transistor is electrically connected to the tenth transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor , the eighth transistor, the ninth transistor and the tenth transistor are electrically connected to the resistor and the voltage output terminal. 2 . The current correction digital-to-analog converter according to claim 1 , further comprising a bias input terminal electrically connected to the first transistor group and the second transistor group. 3 . 3. The current correction digital-to-analog converter according to claim 1, wherein the signal sending group further has a sixth control signal terminal, a seventh control signal terminal and an eighth control signal terminal, the The first inverter group is electrically connected to the sixth control signal terminal, the seventh control signal terminal and the eighth control signal terminal.