CN102738094B - Semiconductor packaging structure for stacking and manufacturing method thereof - Google Patents
Semiconductor packaging structure for stacking and manufacturing method thereof Download PDFInfo
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- CN102738094B CN102738094B CN201210167921.8A CN201210167921A CN102738094B CN 102738094 B CN102738094 B CN 102738094B CN 201210167921 A CN201210167921 A CN 201210167921A CN 102738094 B CN102738094 B CN 102738094B
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Abstract
Description
技术领域 technical field
本发明是有关于一种用于堆叠的半导体封装构造及其制造方法，特别是有关于一种利用环形转接基板减少翘曲缺陷的用于堆叠的半导体封装构造及其制造方法。The present invention relates to a semiconductor package structure for stacking and a manufacturing method thereof, in particular to a semiconductor package structure for stacking and a manufacturing method thereof which utilizes a ring-shaped transfer substrate to reduce warpage defects.
背景技术 Background technique
现今，半导体封装产业为了满足各种高密度封装的需求，逐渐发展出各种不同型式的封装设计，其中各种不同的系统封装(system in package，SIP)设计概念常用于架构高密度封装产品。一般而言，系统封装可分为多芯片模块(multi chip module，MCM)、堆叠式封装体(POP)及封装体内堆叠封装体(package in package，PIP)等。所述多芯片模块(MCM)是指在同一基板上布设数个芯片，在设置芯片后，再利用同一封装胶体包埋所有芯片，且依芯片排列方式又可细分为堆叠芯片(stacked die)封装或并列芯片(side-by-side)封装。再者，所述堆叠式封装体(POP)，其构造是指先完成一具有基板的第一封装体，接着再于第一封装体的上表面堆叠另一完整的第二封装体，第二封装体透过适当转接组件(如锡球)电性连接至第一封装体的基板上，因而成为一复合封装构造。相较之下，所述封装体内堆叠封装体(PIP)的构造则是利用另一封装胶体将第二封装体、转接组件及第一封装体的元件等一起包埋固定在第一封装体的基板上，因而成为一复合封装构造。Nowadays, in order to meet various high-density packaging requirements, the semiconductor packaging industry has gradually developed various types of packaging designs, among which various system in package (SIP) design concepts are often used to structure high-density packaging products. Generally speaking, the system package can be divided into multi chip module (multi chip module, MCM), stacked package (POP), and package in package (package in package, PIP). The multi-chip module (MCM) refers to arranging several chips on the same substrate. After the chips are set, all the chips are embedded with the same encapsulation gel, and can be subdivided into stacked die according to the arrangement of the chips. package or side-by-side package. Furthermore, the structure of the stacked package (POP) refers to first completing a first package with a substrate, and then stacking another complete second package on the upper surface of the first package, the second package The body is electrically connected to the substrate of the first package body through appropriate transition components (such as solder balls), thus forming a composite package structure. In contrast, the structure of the package-in-package (PIP) is to use another encapsulant to embed and fix the second package, the adapter assembly, and the components of the first package together in the first package. on the substrate, thus becoming a composite package structure.
在现有的堆叠式封装体(POP)的结构中，其底部的第一封装体(下封装体)的基板一般为印刷电路基板，及其封装胶体一般是掺杂有固态填充物的环氧树脂基材，且是利用移转注模成型(transfer molding)工艺来制作。近年来，为了满足电子产品的轻薄化要求，现有堆叠式封装体(POP)封装结构的下封装体的厚度逐渐被薄型化至350微米(μm)以下。然而，在下封装体的厚度逐渐减少的情形下，下封装体的整体结构强度亦会被逐渐减弱，且更容易因为印刷电路基板与封装胶体之间的热膨胀系数(coefficient of thermal expansion，CTE)存在差异而有热应力作用拉扯，因而产生翘曲(warpage)的现象。上述翘曲现象通常是由封装胶体朝向印刷电路基板在周缘形成翘曲。同时，由于下封装体的整体厚度变薄也会使得芯片的散热性变差，因此当芯片的热能无法及时有效的向外部导出时，上述翘曲现象会变得更明显，严重时甚至会导致封装胶体或印刷电路基板产生裂痕(crack)，进而大幅影响堆叠式封装体(POP)的下封装体的产品可靠度及使用寿命。In the existing package-on-package (POP) structure, the substrate of the first package (lower package) at the bottom is generally a printed circuit substrate, and its encapsulant is generally epoxy doped with solid fillers. The resin base material is made by transfer molding (transfer molding) process. In recent years, in order to meet the thinning requirements of electronic products, the thickness of the lower package of the existing package-on-package (POP) package structure has gradually been reduced to less than 350 micrometers (μm). However, when the thickness of the lower package gradually decreases, the overall structural strength of the lower package will also be gradually weakened, and it is more likely to be due to the existence of the coefficient of thermal expansion (CTE) between the printed circuit board and the encapsulant. Due to the difference, there is thermal stress and pulling, thus producing warpage. The above-mentioned warping phenomenon is usually caused by the encapsulant warping toward the periphery of the printed circuit board. At the same time, since the overall thickness of the lower package becomes thinner, the heat dissipation of the chip will also deteriorate. Therefore, when the heat energy of the chip cannot be exported to the outside in a timely and effective manner, the above-mentioned warping phenomenon will become more obvious, and even lead to Cracks are generated on the encapsulant or the printed circuit board, which greatly affects the product reliability and service life of the bottom package of the package-on-package (POP).
故，有必要提供一种用于堆叠的半导体封装构造，以解决现有技术所存在的问题。Therefore, it is necessary to provide a semiconductor package structure for stacking to solve the problems existing in the prior art.
发明内容 Contents of the invention
有鉴于此，本发明提供一种用于堆叠的半导体封装构造及其制造方法，以解决现有堆叠式封装体(POP)技术所存在的翘曲与散热问题。In view of this, the present invention provides a semiconductor package structure for stacking and a manufacturing method thereof, so as to solve the problems of warpage and heat dissipation in the existing package-on-package (POP) technology.
本发明的主要目的在于提供一种用于堆叠的半导体封装构造及其制造方法，其是在堆叠式封装体(POP)的下封装体增设一环形转接基板，并在底基板与环形转接基板之间填充封装胶体，以便在减少整体厚度时尽可能保持下封装体的上下侧具有较小的热膨胀系数差异，以相对减少产生翘曲的机率，进而提高下封装体的产品可靠度及使用寿命。The main purpose of the present invention is to provide a semiconductor package structure for stacking and its manufacturing method, which is to add a ring-shaped transfer substrate to the lower package of the stacked package (POP), and connect the bottom substrate and the ring-shaped transfer substrate. The encapsulant is filled between the substrates to keep the difference in thermal expansion coefficient between the upper and lower sides of the lower package as small as possible while reducing the overall thickness, so as to relatively reduce the probability of warping, thereby improving the product reliability and use of the lower package. life.
本发明的次要目的在于提供一种用于堆叠的半导体封装构造及其制造方法，其中环形转接基板的开口处可增设一散热片，散热片热性接触芯片的顶面，且所述散热片也可具有数根支撑肋，由环形转接基板的开口处延伸到数个角隅位置，因此可以迅速的将芯片产生的热能向上及向外导出，进而有利于提高下封装体的散热效率及增加环形转接基板的结构强度，以相对减少因高温而产生翘曲的机率。A secondary object of the present invention is to provide a stacked semiconductor package structure and its manufacturing method, wherein a heat sink can be added to the opening of the ring-shaped transfer substrate, and the heat sink thermally contacts the top surface of the chip, and the heat dissipation The chip can also have several supporting ribs, extending from the opening of the annular transfer substrate to several corner positions, so the heat energy generated by the chip can be quickly exported upwards and outwards, which is beneficial to improve the heat dissipation efficiency of the lower package And increase the structural strength of the annular transfer substrate to relatively reduce the probability of warping due to high temperature.
为达成本发明的前述目的，本发明一实施例提供一种用于堆叠的半导体封装构造，其包含：一底基板、一芯片、一环形转接基板及一封装胶体。所述底基板具有一上表面及一下表面，所述上表面具有数个焊垫及一芯片承载区。所述芯片固设于所述底基板的芯片承载区。所述环形转接基板具有数个转接组件、数个接垫及一开口，所述转接组件设于所述环形转接基板的一下表面，所述接垫设于所述环形转接基板的一上表面，所述开口贯穿所述环形转接基板，所述转接组件围绕在所述开口的周围并电性连接所述底基板的焊垫。所述封装胶体填充在所述底基板与环形转接基板之间形成的一间隙内，以及填充在所述环形转接基板的开口内，且包覆所述芯片及转接组件，其中所述开口内的封装胶体曝露出所述芯片的一顶面。To achieve the aforementioned object of the present invention, an embodiment of the present invention provides a semiconductor package structure for stacking, which includes: a base substrate, a chip, a ring-shaped interposer substrate and an encapsulant. The base substrate has an upper surface and a lower surface, and the upper surface has several welding pads and a chip carrying area. The chip is fixed on the chip carrying area of the base substrate. The ring-shaped transfer substrate has several transfer components, several pads and an opening, the transfer components are arranged on the lower surface of the ring-shaped transfer substrate, and the pads are arranged on the ring-shaped transfer substrate The opening penetrates through the annular interposer substrate, and the interposer assembly surrounds the opening and electrically connects the pads of the base substrate. The encapsulant is filled in a gap formed between the base substrate and the ring-shaped transfer substrate, and is filled in the opening of the ring-shaped transfer substrate, and covers the chip and the transfer assembly, wherein the The encapsulant in the opening exposes a top surface of the chip.
再者，本发明一实施例提供一种用于堆叠的半导体封装构造的制造方法。首先，提供一底基板，所述底基板具有一上表面及一下表面，所述上表面具有数个焊垫及一芯片承载区。然后，将一芯片固设于所述底基板的芯片承载区。接着，提供一环形转接基板，并通过所述环形转接基板的一下表面的数个转接组件电性连接所述底基板的焊垫，其中所述环形转接基板开设有一开口，所述转接组件围绕在所述开口的周围，及所述环形转接基板的一上表面设有数个接垫。以及，将一封装胶体填入所述底基板与环形转接基板之间形成的一间隙内及所述环形转接基板的开口内，所述封装胶体包覆所述芯片及转接组件，且所述开口内的封装胶体曝露出所述芯片的一顶面。Furthermore, an embodiment of the present invention provides a method for manufacturing a stacked semiconductor package structure. First, a base substrate is provided, the base substrate has an upper surface and a lower surface, and the upper surface has several welding pads and a chip carrying area. Then, a chip is fixed on the chip carrying area of the base substrate. Next, provide a ring-shaped transfer substrate, and electrically connect the welding pads of the base substrate through several transfer components on the lower surface of the ring-shaped transfer substrate, wherein the ring-shaped transfer substrate has an opening, the The transfer assembly surrounds the opening, and a plurality of pads are provided on an upper surface of the annular transfer substrate. And, filling an encapsulant into a gap formed between the base substrate and the ring-shaped interposer substrate and an opening of the annular interposer substrate, the encapsulant envelops the chip and the interposer assembly, and The encapsulant in the opening exposes a top surface of the chip.
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：In order to make the above content of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:
附图说明 Description of drawings
图1是本发明一实施例堆叠式封装体的上、下封装体的剖视图。FIG. 1 is a cross-sectional view of upper and lower packages of a stacked package according to an embodiment of the present invention.
图2是本发明另一实施例堆叠式封装体的上、下封装体的剖视图。2 is a cross-sectional view of the upper and lower packages of the stacked package according to another embodiment of the present invention.
图3是本发明又一实施例堆叠式封装体的上、下封装体的剖视图。3 is a cross-sectional view of the upper and lower packages of the stacked package according to another embodiment of the present invention.
图3A是本发明图3的下封装体的上视图。FIG. 3A is a top view of the lower package in FIG. 3 of the present invention.
图4是本发明再一实施例堆叠式封装体的上、下封装体的剖视图。4 is a cross-sectional view of the upper and lower packages of the stacked package according to another embodiment of the present invention.
图5A、5B及5C是本发明图1用于堆叠的半导体封装构造(下封装体)的制造方法的流程示意图。5A, 5B and 5C are schematic flowcharts of the manufacturing method of the semiconductor package structure (lower package) for stacking shown in FIG. 1 of the present invention.
图6A及6B是本发明图3用于堆叠的半导体封装构造(下封装体)的制造方法的流程示意图。6A and 6B are schematic flowcharts of the manufacturing method of the semiconductor package structure (lower package) for stacking shown in FIG. 3 of the present invention.
具体实施方式 Detailed ways
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」或「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. Furthermore, the directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside" or "side", etc., It is only for orientation with reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.
请参照图1所示，本发明第一实施例的用于堆叠的半导体封装构造主要应用于做为一堆叠式封装体(POP)的一下封装体100，并用以结合一上封装体200，在下文中，所述用于堆叠的半导体封装构造即直接称为下封装体100。在本实施例中，所述下封装体100包含：一底基板10、一芯片11、一环形转接基板12及一封装胶体13。本发明将于下文逐一详细说明本实施例上述各元件的细部构造、组装关系及其运作原理。Please refer to FIG. 1, the semiconductor package structure for stacking according to the first embodiment of the present invention is mainly applied to the lower package 100 as a package-on-package (POP), and is used to combine an upper package 200, the lower package Herein, the stacked semiconductor package structure is directly referred to as the lower package 100 . In this embodiment, the lower package body 100 includes: a base substrate 10 , a chip 11 , a ring-shaped interposer substrate 12 and an encapsulant 13 . The present invention will describe in detail the detail structure, assembly relationship and operation principle of the above-mentioned components of this embodiment below one by one.
请参照图1所示，本发明一实施例的底基板10可选自厚度在50至200μm(微米)之间的无核芯层(coreless)的印刷电路基板或者选自可挠性薄膜基板(flexible tape substrate)，例如选自厚度为150或180μm的无核芯层的增层式(build-up)印刷电路基板(包含4层电路层)或者是厚度为64μm的可挠性薄膜基板，但并不限于此。所述底基板10不具核芯层将有利于相对减少其基板厚度。所述底基板10具有一上表面及一下表面，所述上表面的表面电路裸露有数个焊垫101及一芯片承载区102。所述焊垫101通常呈矩阵(array)状排列在所述上表面上。所述芯片承载区102是指所述上表面的一个中央区域，在所述芯片承载区102内通常也分布有数个焊垫101。所述下表面的表面电路也裸露有数个焊垫(未标示)，并由这些下表面的焊垫焊接结合有数个金属球103，以做为所述底基板10输入/输出用的电性端子。Please refer to FIG. 1, the base substrate 10 of an embodiment of the present invention can be selected from a coreless printed circuit substrate with a thickness between 50 and 200 μm (micrometer) or a flexible film substrate ( flexible tape substrate), such as a build-up printed circuit substrate (including 4 circuit layers) with a thickness of 150 or 180 μm without a core layer or a flexible film substrate with a thickness of 64 μm, but It is not limited to this. The absence of the core layer of the base substrate 10 is beneficial to relatively reduce its substrate thickness. The base substrate 10 has an upper surface and a lower surface, and the surface circuit on the upper surface exposes a plurality of pads 101 and a chip carrying area 102 . The pads 101 are generally arranged on the upper surface in a matrix. The chip carrying area 102 refers to a central area of the upper surface, and several welding pads 101 are usually distributed in the chip carrying area 102 . The surface circuit on the lower surface is also exposed with several welding pads (not marked), and several metal balls 103 are welded and combined by these welding pads on the lower surface to serve as electrical terminals for input/output of the base substrate 10 .
请参照图1所示，本发明一实施例的芯片11可以是各种半导体芯片，例如高频芯片、中央处理单元(CPU)芯片或记忆体芯片(如DRAM或FLASH)等，但并不加以限制。所述芯片11可以是倒装芯片(flip chip)的形式或打线芯片(wire bonding chip)的形式。以倒装芯片为例，所述芯片11的有源表面朝下，并通过数个凸块111焊接结合及固设于所述底基板10的芯片承载区102的焊垫101上。所述芯片11与所述底基板10的上表面之间可填充有一底部填充胶(underfill)112，但亦可予以省略。所述芯片11的厚度可介于0.1至0.04mm之间，例如为0.1、0.08、0.06、0.05或0.04等。所述凸块111可选自锡凸块(bumps)、金凸块或铜柱凸块(Cu pillar bumps)等，所述凸块111的高度约为30至50μm，例如为40μm。Please refer to shown in Fig. 1, the chip 11 of one embodiment of the present invention can be various semiconductor chips, for example high-frequency chip, central processing unit (CPU) chip or memory chip (such as DRAM or FLASH) etc., but do not add limit. The chip 11 may be in the form of a flip chip or a wire bonding chip. Taking flip chip as an example, the active surface of the chip 11 faces down, and is soldered and fixed on the pads 101 of the chip carrying area 102 of the base substrate 10 through several bumps 111 . An underfill 112 can be filled between the chip 11 and the upper surface of the base substrate 10 , but it can also be omitted. The thickness of the chip 11 can be between 0.1 mm and 0.04 mm, such as 0.1, 0.08, 0.06, 0.05 or 0.04 mm. The bumps 111 can be selected from tin bumps, gold bumps or copper pillar bumps, etc., and the height of the bumps 111 is about 30 to 50 μm, for example, 40 μm.
请参照图1所示，本发明一实施例的环形转接基板12可选自厚度在100至150μm之间且具核芯层的印刷电路基板，例如选自厚度为140μm的无核芯层的印刷电路基板(包含2层电路层)，但并不限于此。所述环形转接基板12具有核芯层将有利于在较小的基板厚度下确保其具有足够结构强度。所述环形转接基板12的一下表面的表面电路裸露有数个焊垫(未标示)，并由这些下表面的焊垫焊接结合有数个转接组件121，所述转接组件121例如为锡凸块、金凸块或铜柱凸块等，所述转接组件121的高度约为15至25μm，例如为20μm。Please refer to FIG. 1, the annular interposer substrate 12 of an embodiment of the present invention can be selected from a printed circuit substrate with a thickness of 100 to 150 μm and a core layer, for example, a core-free layer with a thickness of 140 μm. A printed circuit board (including 2 circuit layers), but not limited thereto. The ring-shaped interposer substrate 12 having a core layer is beneficial to ensure sufficient structural strength with a small substrate thickness. The surface circuit on the lower surface of the ring-shaped transfer substrate 12 is exposed with several welding pads (not marked), and these welding pads on the lower surface are welded and combined with several transfer components 121, and the transfer components 121 are, for example, tin bumps. Blocks, gold bumps or copper pillar bumps, etc., the height of the transition component 121 is about 15 to 25 μm, for example, 20 μm.
再者，所述环形转接基板12开设有一开口122，所述开口122贯穿所述环形转接基板12，并对应于所述芯片承载区102及芯片11，且所述开口122的长宽尺寸(例如11×11mm)明显大于所述芯片承载区102或所述芯片11的长宽尺寸(例如10×10mm)。所述转接组件121围绕在所述开口122的周围并电性连接所述底基板10的焊垫101。所述环形转接基板12的一上表面的表面电路另裸露有数个接垫123，所述接垫123的开口直径约为0.2mm，及其间距介于0.3至0.085mm之间，例如为0.3、0.2、0.15、0.1或0.085mm等。Furthermore, the ring-shaped transfer substrate 12 defines an opening 122, the opening 122 runs through the ring-shaped transfer substrate 12, and corresponds to the chip carrying area 102 and the chip 11, and the length and width of the opening 122 (for example, 11×11 mm) are significantly larger than the length and width dimensions (for example, 10×10 mm) of the chip carrying area 102 or the chip 11 . The transition component 121 surrounds the opening 122 and is electrically connected to the pad 101 of the base substrate 10 . The surface circuit on an upper surface of the annular interposer substrate 12 is exposed to several pads 123. The opening diameter of the pads 123 is about 0.2 mm, and the distance between them is between 0.3 and 0.085 mm, for example, 0.3 mm. , 0.2, 0.15, 0.1 or 0.085mm, etc.
请参照图1所示，本发明一实施例的封装胶体13填充在所述底基板10与环形转接基板12之间形成的一间隙14内，以及填充在所述环形转接基板12的开口122内，且包覆所述芯片11及转接组件121。所述间隙14的高度约为15至25μm，例如为20μm。位于所述开口122内的封装胶体13的一上表面并曝露出所述芯片11的一顶面(背面)。所述封装胶体13一般是掺杂有固态填充物的环氧树脂基材，所述固态填充物可以是二氧化硅颗粒或氧化铝颗粒等。位于所述开口122内的封装胶体13的一上表面的高度可以些微低于或大致等于所述环形转接基板12的上表面的高度。Please refer to FIG. 1 , the encapsulant 13 according to an embodiment of the present invention is filled in a gap 14 formed between the base substrate 10 and the annular interposer substrate 12 , and filled in the opening of the annular interposer substrate 12 122 , and covers the chip 11 and the adapter assembly 121 . The height of the gap 14 is about 15 to 25 μm, for example 20 μm. An upper surface of the encapsulant 13 located in the opening 122 exposes a top surface (back surface) of the chip 11 . The encapsulant 13 is generally an epoxy resin substrate doped with a solid filler, and the solid filler may be silica particles or alumina particles. The height of an upper surface of the encapsulant 13 located in the opening 122 may be slightly lower than or approximately equal to the height of the upper surface of the annular interposer substrate 12 .
请参照图1所示，本发明一实施例的上封装体200可以是各种形式的封装体，本发明并不加以限制，例如所述上封装体200选自一具有堆叠芯片的封装体，其基板的下表面设有数个金属球21，可供焊接结合在所述环形转接基板12的上表面的接垫123上，以便间接的与所述底基板10及芯片11形成电性连接关系，如此所述下封装体100及上封装体200即可共同构成一堆叠式封装体(POP)的架构。Please refer to FIG. 1 , the upper package 200 of an embodiment of the present invention may be various forms of packages, the present invention is not limited, for example, the upper package 200 is selected from a package with stacked chips, The lower surface of the substrate is provided with several metal balls 21, which can be soldered and bonded to the pads 123 on the upper surface of the annular transfer substrate 12, so as to indirectly form an electrical connection with the bottom substrate 10 and the chip 11. In this way, the lower package body 100 and the upper package body 200 can jointly form a package-on-package (POP) structure.
根据本实施例，由于堆叠式封装体(POP)的下封装体100增设所述环形转接基板12，并在所述底基板10与环形转接基板12之间填充所述封装胶体13，同时适当选择所述底基板10与环形转接基板12的基板种类，因此可以使所述封装胶体13的上下两侧具有相似的基板特性，以便在减少所述下封装体100整体厚度时，尽可能保持所述下封装体100的上下两侧具有较小的热膨胀系数差异，以相对减少所述下封装体100产生翘曲的机率，进而提高所述下封装体100的产品可靠度及使用寿命。According to this embodiment, since the lower package 100 of the package-on-package (POP) is provided with the annular interposer substrate 12, and the encapsulant 13 is filled between the base substrate 10 and the annular interposer substrate 12, at the same time Appropriate selection of the substrate types of the base substrate 10 and the ring-shaped interposer substrate 12 can make the upper and lower sides of the encapsulant 13 have similar substrate characteristics, so that when reducing the overall thickness of the lower package body 100, the Keeping the upper and lower sides of the lower package 100 with a small difference in thermal expansion coefficients relatively reduces the probability of warping of the lower package 100 , thereby improving product reliability and service life of the lower package 100 .
请参照图2所示，本发明另一实施例的用于堆叠的半导体封装构造相似于本发明图1实施例，并大致沿用相同元件名称及图号，但本实施例的差异特征在于：本实施例的下封装体100进一步增设一散热片15，所述散热片15嵌设在所述环形转接基板12的开口122内。位于所述开口122内的封装胶体13的上表面些微低于所述环形转接基板12的上表面，以便嵌设所述散热片15，所述散热片15的厚度大致等于所述封装胶体13的上表面与所述环形转接基板12的上表面之间形成的高度差。所述散热片15的下表面直接贴接于所述开口122处的封装胶体13上，且所述散热片15的下表面也热性接触所述芯片11的顶面(背面)。Please refer to FIG. 2, another embodiment of the present invention is similar to the semiconductor package structure for stacking in the embodiment of FIG. The lower package body 100 of the embodiment further adds a heat sink 15 , and the heat sink 15 is embedded in the opening 122 of the annular interposer substrate 12 . The upper surface of the encapsulant 13 located in the opening 122 is slightly lower than the upper surface of the ring-shaped interposer substrate 12, so as to embed the heat sink 15, and the thickness of the heat sink 15 is approximately equal to that of the encapsulant 13. The height difference formed between the upper surface of the ring-shaped interposer substrate 12 and the upper surface of the ring-shaped interposer substrate 12 . The lower surface of the heat sink 15 is directly attached to the encapsulant 13 at the opening 122 , and the lower surface of the heat sink 15 is also in thermal contact with the top surface (back surface) of the chip 11 .
在本实施例中，所述散热片15也可选择对应所述开口122设置至少一个填胶孔151。在进行移转注模成型(transfer molding)工艺时，所述填胶孔151可以方便一封胶注射器插入到所述开口122内的空间，以将所述封装胶体13填到所述开口122内的空间以及所述底基板10与环形转接基板12之间的间隙14内。再者，所述散热片15的一下表面与所述芯片11的顶面之间具有一导热层16，所述导热层16可以选自导热银胶涂层、铟层或铟锡层。所述导热层16用以确保所述散热片15与芯片11的热性连接关系。In this embodiment, the heat sink 15 may optionally be provided with at least one glue filling hole 151 corresponding to the opening 122 . When performing transfer molding (transfer molding) process, the filling hole 151 can facilitate the insertion of a sealing syringe into the space in the opening 122, so as to fill the encapsulation compound 13 into the opening 122. space and the gap 14 between the base substrate 10 and the annular interposer substrate 12 . Furthermore, there is a heat conduction layer 16 between the lower surface of the heat sink 15 and the top surface of the chip 11 , and the heat conduction layer 16 can be selected from heat conduction silver glue coating, indium layer or indium tin layer. The heat conduction layer 16 is used to ensure the thermal connection between the heat sink 15 and the chip 11 .
根据本实施例，所述下封装体100同样可利用所述环形转接基板12使所述封装胶体13的上下两侧具有相似的基板特性，以便在减少所述下封装体100整体厚度时，尽可能保持所述下封装体100的上下两侧具有较小的热膨胀系数差异，以相对减少所述下封装体100产生翘曲的机率，进而提高所述下封装体100的产品可靠度及使用寿命。更进一步的，在本实施例中，所述环形转接基板12的开口122处更增设所述散热片15，所述散热片15热性接触所述芯片11的顶面，因此可以迅速的将所述芯片11产生的热能向上导出，进而有利于提高所述下封装体100的散热效率，并相对减少所述下封装体100因高温而产生翘曲的机率。According to this embodiment, the lower package body 100 can also use the ring-shaped interposer substrate 12 to make the upper and lower sides of the molding compound 13 have similar substrate characteristics, so that when the overall thickness of the lower package body 100 is reduced, Keep the upper and lower sides of the lower package 100 with a small difference in thermal expansion coefficient as much as possible, so as to relatively reduce the probability of warping of the lower package 100, thereby improving the product reliability and use of the lower package 100. life. Furthermore, in this embodiment, the heat sink 15 is added at the opening 122 of the annular interposer substrate 12, and the heat sink 15 thermally contacts the top surface of the chip 11, so that the The heat energy generated by the chip 11 is exported upwards, thereby improving the heat dissipation efficiency of the lower package 100 and relatively reducing the probability of warping of the lower package 100 due to high temperature.
请参照图3及3A所示，本发明又一实施例的用于堆叠的半导体封装构造相似于本发明图2实施例，并大致沿用相同元件名称及图号，但本实施例的差异特征在于：本实施例的下封装体100的散热片15是位于所述环形转接基板12的开口122的上唇缘上，同时所述散热片15更具有数根支撑肋152(如图3A所示)，所述支撑肋152由所述开口122处延伸到所述环形转接基板12的一上表面的数个角隅位置或其邻近区域。位于所述开口122内的封装胶体13的上表面大致等于所述环形转接基板12的上表面，因此所述散热片15的下表面仍可贴接于所述开口122处的封装胶体13上，且所述散热片15的下表面也可热性接触所述芯片11的顶面(背面)。所述支撑肋152及所述环形转接基板12的角隅的数量例如皆为4个，但并不限于此。所述散热片15的厚度基本上小于所述环形转接基板12的厚度，例如为所述环形转接基板12的厚度的1/2、1/3、1/4或1/5等。Please refer to Figures 3 and 3A, the stacked semiconductor package structure of another embodiment of the present invention is similar to the embodiment of the present invention in Figure 2, and generally uses the same component names and figure numbers, but the difference of this embodiment is that : the heat sink 15 of the lower package body 100 of the present embodiment is located on the upper lip of the opening 122 of the annular interposer substrate 12, and the heat sink 15 has several supporting ribs 152 (as shown in FIG. 3A ) , the supporting ribs 152 extend from the opening 122 to several corner positions on an upper surface of the annular interposer substrate 12 or adjacent areas thereof. The upper surface of the encapsulant 13 located in the opening 122 is approximately equal to the upper surface of the annular interposer substrate 12, so the lower surface of the heat sink 15 can still be attached to the encapsulant 13 at the opening 122. , and the lower surface of the heat sink 15 can also thermally contact the top surface (back surface) of the chip 11 . The numbers of the supporting ribs 152 and the corners of the annular interposer substrate 12 are, for example, four, but not limited thereto. The thickness of the heat sink 15 is substantially smaller than that of the annular interposer substrate 12 , for example, 1/2, 1/3, 1/4 or 1/5 of the thickness of the annular interposer substrate 12 .
根据本实施例，所述下封装体100同样可利用所述环形转接基板12使所述封装胶体13的上下两侧具有相似的基板特性，以便在减少所述下封装体100整体厚度时，尽可能保持所述下封装体100的上下两侧具有较小的热膨胀系数差异，以相对减少所述下封装体100产生翘曲的机率，进而提高所述下封装体100的产品可靠度及使用寿命。更进一步的，在本实施例中，所述环形转接基板12的开口122处更增设所述散热片15，且所述散热片15热性接触所述芯片11的顶面，因此可以迅速的将所述芯片11产生的热能向上及向外导出，进而有利于提高所述下封装体100的散热效率，及增加所述环形转接基板12的结构强度，以相对减少所述下封装体100因高温而产生翘曲的机率。According to this embodiment, the lower package body 100 can also use the ring-shaped interposer substrate 12 to make the upper and lower sides of the molding compound 13 have similar substrate characteristics, so that when the overall thickness of the lower package body 100 is reduced, Keep the upper and lower sides of the lower package 100 with a small difference in thermal expansion coefficient as much as possible, so as to relatively reduce the probability of warping of the lower package 100, thereby improving the product reliability and use of the lower package 100. life. Furthermore, in this embodiment, the heat sink 15 is added at the opening 122 of the ring-shaped interposer substrate 12, and the heat sink 15 is in thermal contact with the top surface of the chip 11, so it can quickly The heat energy generated by the chip 11 is exported upwards and outwards, which is beneficial to improve the heat dissipation efficiency of the lower package body 100, and increase the structural strength of the ring-shaped interposer substrate 12, so as to relatively reduce the heat dissipation of the lower package body 100. Chance of warping due to high temperature.
请参照图4所示，本发明再一实施例的用于堆叠的半导体封装构造相似于本发明图1实施例，并大致沿用相同元件名称及图号，但本实施例的差异特征在于：本实施例的下封装体100(半导体封装构造)的环形转接基板12与所述上封装体200之间另夹设有一有机间隔基板(organic interposer)17，所述有机间隔基板17可选自厚度在50至100μm之间的无核芯层的印刷电路基板或可挠性薄膜基板，例如选自厚度为90μm的无核芯层的增层式(build-up)印刷电路基板(包含2层电路层)或者是厚度为75μm的可挠性薄膜基板，但并不限于此。Please refer to FIG. 4, the semiconductor package structure for stacking in another embodiment of the present invention is similar to the embodiment of the present invention in FIG. An organic interposer (organic interposer) 17 is interposed between the annular interposer substrate 12 of the lower package 100 (semiconductor package structure) of the embodiment and the upper package 200, and the organic interposer 17 can be selected from the thickness Core-free printed circuit substrates or flexible film substrates between 50 and 100 μm, e.g. selected from core-free build-up printed circuit substrates (comprising 2-layer circuits) with a thickness of 90 μm layer) or a flexible film substrate with a thickness of 75 μm, but not limited thereto.
根据本实施例，所述下封装体100同样可利用所述环形转接基板12使所述封装胶体13的上下两侧具有相似的基板特性，以便在减少所述下封装体100整体厚度时，尽可能保持所述下封装体100的上下两侧具有较小的热膨胀系数差异，以相对减少所述下封装体100产生翘曲的机率，进而提高所述下封装体100的产品可靠度及使用寿命。更进一步的，在本实施例中，当所述环形转接基板12的厚度已被设计成能使所述封装胶体13的上下两侧具有相似的基板特性(含热膨胀系数)，但所述环形转接基板12在有限的厚度下无法提供足够的焊垫重分布(redistribution)需求或散热需求时，本实施例即可通过额外使用所述有机间隔基板17来满足焊垫重分布需求或散热需求。According to this embodiment, the lower package body 100 can also use the ring-shaped interposer substrate 12 to make the upper and lower sides of the molding compound 13 have similar substrate characteristics, so that when the overall thickness of the lower package body 100 is reduced, Keep the upper and lower sides of the lower package 100 with a small difference in thermal expansion coefficient as much as possible, so as to relatively reduce the probability of warping of the lower package 100, thereby improving the product reliability and use of the lower package 100. life. Furthermore, in this embodiment, when the thickness of the annular interposer substrate 12 has been designed so that the upper and lower sides of the encapsulant 13 have similar substrate properties (including thermal expansion coefficients), but the annular When the interposer substrate 12 cannot provide sufficient pad redistribution requirements or heat dissipation requirements under the limited thickness, this embodiment can meet the pad redistribution requirements or heat dissipation requirements by additionally using the organic spacer substrate 17 .
请参照图5A、5B及5C所示，其揭示本发明图1实施例用于堆叠的半导体封装构造(下封装体100)的制造方法的流程示意图。Please refer to FIGS. 5A , 5B and 5C , which disclose a schematic flowchart of a manufacturing method for a stacked semiconductor package structure (lower package 100 ) according to the embodiment of FIG. 1 of the present invention.
首先，如图5A所示，先提供一底基板10，所述底基板10具有一上表面及一下表面，所述上表面具有数个焊垫101及一芯片承载区102；接着，将一芯片11固设于所述底基板10的芯片承载区102。First, as shown in FIG. 5A , a base substrate 10 is first provided, and the base substrate 10 has an upper surface and a lower surface, and the upper surface has several welding pads 101 and a chip carrying area 102; then, a chip 11 is fixed on the chip carrying area 102 of the base substrate 10 .
随后，如图5A及5B所示，再提供一环形转接基板12，并通过所述环形转接基板12的一下表面的数个转接组件121电性连接所述底基板10的焊垫101，其中所述环形转接基板12开设有一开口122，所述转接组件121围绕在所述开口122的周围Subsequently, as shown in FIGS. 5A and 5B , a ring-shaped transfer substrate 12 is provided, and several transfer components 121 on the lower surface of the ring-shaped transfer substrate 12 are electrically connected to the pads 101 of the base substrate 10. , wherein the annular adapter substrate 12 defines an opening 122, and the adapter assembly 121 surrounds the opening 122
最后，如图5B及5C所示，在填入所述封装胶体13之前，先在所述环形转接基板12的开口122上贴上一层临时性胶膜30，或者也可以将所述临时性胶膜30预先放置在一上模具(未绘示)的一模穴的一内顶面上，在将图5A的全部组件放于所述上模具与一下模具(未绘示)之间并进行合模时，所述临时性胶膜30就可转贴在所述环形转接基板12的开口122上；接着，将一封装胶体13填入所述底基板10与环形转接基板12之间形成的一间隙14内及所述环形转接基板12的开口122内，所述封装胶体13包覆所述芯片11及转接组件121，且所述开口122内的封装胶体13曝露出所述芯片11的一顶面。在完成填入所述封装胶体13的步骤之后，即撕除所述临时性胶膜30。通过上述步骤，本发明即可完成用于堆叠的半导体封装构造(下封装体100)的制造。Finally, as shown in Figures 5B and 5C, before filling the encapsulant 13, a layer of temporary adhesive film 30 is pasted on the opening 122 of the annular interposer substrate 12, or the temporary The plastic film 30 is pre-placed on an inner top surface of a mold cavity of an upper mold (not shown), and all the components of FIG. 5A are placed between the upper mold and the lower mold (not shown) and When the mold is closed, the temporary adhesive film 30 can be pasted on the opening 122 of the ring-shaped transfer substrate 12; then, an encapsulant 13 is filled between the bottom substrate 10 and the ring-shaped transfer substrate 12 In a gap 14 formed and in the opening 122 of the annular transfer substrate 12, the encapsulant 13 covers the chip 11 and the transfer assembly 121, and the encapsulant 13 in the opening 122 exposes the a top surface of the chip 11. After the step of filling the encapsulant 13 is completed, the temporary adhesive film 30 is torn off. Through the above steps, the present invention can complete the manufacture of the stacked semiconductor package structure (the lower package body 100 ).
再者，如图1所示，本发明亦可使所述下封装体100进一步结合一上封装体200，其中所述上封装体200的下表面的金属球21焊接结合在所述环形转接基板12的上表面的接垫123上，如此所述下封装体100及上封装体200即可共同构成一堆叠式封装体(POP)的架构。Furthermore, as shown in FIG. 1 , the present invention can also further combine the lower package body 100 with an upper package body 200, wherein the metal balls 21 on the lower surface of the upper package body 200 are soldered and bonded to the annular adapter. On the pads 123 on the upper surface of the substrate 12 , the lower package 100 and the upper package 200 can jointly form a package-on-package (POP) structure.
请参照图6A及6B所示，其揭示本发明图3实施例用于堆叠的半导体封装构造(下封装体100)的制造方法的流程示意图。本实施例的制造方法各步骤大致相似于本发明图5A至5C实施例的制造方法各步骤，并大致沿用相同元件名称及图号，但本实施例的差异特征在于：图3的下封装体100(半导体封装构造)是直接以一散热片15来取代所述临时性胶膜30。因此，在填入所述封装胶体13的步骤之前，本发明是先在所述环形转接基板12的开口122处设置一散热片15，所述散热片15对应所述开口122具有数个填胶孔151，及所述散热片15可以选择位于所述开口122内(如图2所示)，或位于所述开口122的上唇缘上(如图3所示)；以及，在填入所述封装胶体13的步骤中，通过所述散热片15的填胶孔151填入所述封装胶体13。也就是，在进行移转注模成型(transfer molding)工艺时，所述填胶孔151可方便一封胶注射器插入到所述开口122内的空间，以将所述封装胶体13填到所述开口122内的空间以及所述底基板10与环形转接基板12之间的间隙14内。Please refer to FIGS. 6A and 6B , which disclose a schematic flowchart of a manufacturing method for a stacked semiconductor package structure (lower package 100 ) according to the embodiment of FIG. 3 of the present invention. The steps of the manufacturing method of this embodiment are roughly similar to the steps of the manufacturing method of the embodiment of FIGS. 100 (semiconductor package structure) directly replaces the temporary adhesive film 30 with a heat sink 15 . Therefore, before the step of filling the encapsulant 13, the present invention firstly arranges a heat sink 15 at the opening 122 of the ring-shaped interposer substrate 12, and the heat sink 15 has several fillings corresponding to the opening 122. Glue holes 151, and the heat sink 15 can be selected to be located in the opening 122 (as shown in Figure 2), or on the upper lip of the opening 122 (as shown in Figure 3); In the step of describing the encapsulation compound 13, the encapsulation compound 13 is filled through the glue filling hole 151 of the heat sink 15 . That is, when the transfer molding (transfer molding) process is performed, the filling hole 151 can facilitate the insertion of a sealing syringe into the space in the opening 122, so as to fill the encapsulation compound 13 into the opening. 122 and the gap 14 between the base substrate 10 and the annular interposer substrate 12 .
再者，在本实施例中，所述散热片15的一下表面与所述芯片11的顶面之间具有一导热层16，所述导热层16用以确保所述散热片15与芯片11的热性连接关系。在填入所述封装胶体13的步骤之后，所述散热片15直接保留在所述下封装体100的环形转接基板12上，并不加以去除。另外，所述芯片11与所述底基板10的上表面之间可以省略原底部填充胶112，而直接以填充所述封装胶体13来加以取代。Furthermore, in this embodiment, there is a heat conduction layer 16 between the lower surface of the heat sink 15 and the top surface of the chip 11, and the heat conduction layer 16 is used to ensure the contact between the heat sink 15 and the chip 11. Thermal connections. After the step of filling the encapsulant 13 , the heat sink 15 remains directly on the ring-shaped interposer substrate 12 of the lower package body 100 and is not removed. In addition, the original underfill 112 can be omitted between the chip 11 and the upper surface of the base substrate 10 , and the encapsulant 13 can be directly filled instead.
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9318411B2 (en) * | 2013-11-13 | 2016-04-19 | Brodge Semiconductor Corporation | Semiconductor package with package-on-package stacking capability and method of manufacturing the same |
| US9299651B2 (en) * | 2013-11-20 | 2016-03-29 | Bridge Semiconductor Corporation | Semiconductor assembly and method of manufacturing the same |
| US9209154B2 (en) * | 2013-12-04 | 2015-12-08 | Bridge Semiconductor Corporation | Semiconductor package with package-on-package stacking capability and method of manufacturing the same |
| US9293442B2 (en) * | 2014-03-07 | 2016-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
| CN104659005A (en) * | 2015-01-23 | 2015-05-27 | 三星半导体(中国)研究开发有限公司 | Packaging device, package stacking structure comprising packaging device, and manufacturing method of packaging device |
| US9806066B2 (en) | 2015-01-23 | 2017-10-31 | Samsung Electronics Co., Ltd. | Semiconductor package including exposed connecting stubs |
| US10756072B2 (en) | 2015-12-25 | 2020-08-25 | Intel Corporation | Conductive wire through-mold connection apparatus and method |
| US9837385B1 (en) * | 2017-03-16 | 2017-12-05 | Powertech Technology Inc. | Substrate-less package structure |
| CN107017212A (en) * | 2017-05-22 | 2017-08-04 | 华进半导体封装先导技术研发中心有限公司 | High-density system-in-package structure and its manufacture method |
| CN107706172A (en) * | 2017-08-22 | 2018-02-16 | 中国电子科技集团公司第五十八研究所 | The wafer scale three-dimension packaging structure of multilayer wiring |
| US11658102B2 (en) * | 2020-01-22 | 2023-05-23 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| CN111312698A (en) * | 2020-02-26 | 2020-06-19 | 通富微电子股份有限公司 | Stack type packaging device |
| CN111243967A (en) * | 2020-02-26 | 2020-06-05 | 通富微电子股份有限公司 | Stack type packaging method |
| CN111312597A (en) * | 2020-02-26 | 2020-06-19 | 通富微电子股份有限公司 | Embedded packaging method |
| CN111883496A (en) * | 2020-08-31 | 2020-11-03 | 中国电子科技集团公司第五十八研究所 | Three-dimensional stacked package heat dissipation structure based on wafer reconstruction process and manufacturing method thereof |
| CN116134606A (en) * | 2020-09-25 | 2023-05-16 | 华为技术有限公司 | Packaging structure and packaging method, electronic device and manufacturing method thereof |
| CN114883206A (en) * | 2021-02-05 | 2022-08-09 | 天芯互联科技有限公司 | Chip packaging method and chip packaging mechanism |
| CN113035826B (en) * | 2021-02-23 | 2022-08-19 | 青岛歌尔智能传感器有限公司 | Packaging module, manufacturing method of packaging module and electronic equipment |
| CN113675162A (en) * | 2021-06-30 | 2021-11-19 | 通富微电子股份有限公司 | System-in-package device and method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064163A (en) * | 2010-04-02 | 2011-05-18 | 日月光半导体制造股份有限公司 | Stack packaging assembly |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI255023B (en) * | 2004-10-05 | 2006-05-11 | Via Tech Inc | Cavity down stacked multi-chip package |
| KR101037229B1 (en) * | 2006-04-27 | 2011-05-25 | 스미토모 베이클리트 컴퍼니 리미티드 | Semiconductor device and manufacturing method of semiconductor device |
| US7687897B2 (en) * | 2006-12-28 | 2010-03-30 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system with adhesive spacing structures |
-
2012
- 2012-05-25 CN CN201210167921.8A patent/CN102738094B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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