CN102044447B - Packaging process and packaging structure - Google Patents

Abstract

The invention relates to a packaging process and a packaging structure. The packaging process is as follows. First, a carrier plate is provided, and an adhesive layer is disposed on the carrier plate. Then, a plurality of first semiconductor elements are arranged on the adhesive layer. Then, a first encapsulant is formed on the carrier, and the first encapsulant covers the sidewalls of the first semiconductor elements and fills gaps between the first semiconductor elements, so that the first semiconductor elements and the first encapsulant form a chip array board. After that, the plurality of second semiconductor elements are flip-chip bonded to the first semiconductor elements, respectively. Then, a second encapsulant is formed on the chip array board, and the second encapsulant at least covers the sidewalls of the second semiconductor elements and fills the gaps between the second semiconductor elements. Then, the chip array board and the adhesive layer are separated. And finally, cutting the second packaging colloid and the first packaging colloid along the gap between the second semiconductor elements.

Description

Packaging process and packaging structure

technical field

The invention relates to a packaging process and a packaging structure, and in particular to a packaging process and a packaging structure in which a large chip is arranged on a small chip.

Background technique

In today's information society, users are pursuing high-speed, high-quality, and multi-functional electronic products. As far as product appearance is concerned, the design of electronic products is moving towards the trend of light, thin, short and small. Therefore, electronic packaging technology has developed multi-chip packaging technologies such as stacked chip packaging.

Stacked chip packaging uses vertical stacking to package multiple chips in the same package structure, which can increase the packaging density to make the package smaller, and can shorten the path length of signal transmission between chips by using three-dimensional stacking. In order to increase the speed of signal transmission between chips, chips with different functions can be combined in the same package.

The known manufacturing method of stacked chip packaging is to firstly bond a plurality of flip chips onto a wafer, then cut the wafer along the gaps between the chips to form a plurality of chip stack structures, and then dispose the chip stack structures on and form encapsulant on the circuit board to protect the chip stack structure.

Since the known manufacturing method of the stacked chip package is to form a plurality of chip stack structures by dicing the wafer, therefore, in the chip stack structure, the size of the chip formed by dicing the wafer must be larger than the size of the chip bonded to the wafer. The size of the loaded chip. Therefore, the known manufacturing method of stacked chip package can only form a package structure in which a small-sized chip is arranged on a large-sized chip.

In addition, in order to reduce the overall thickness of the stacked chip package in the known technology, the wafer is ground before the flip chip is bonded to the wafer, so as to reduce the thickness of the wafer. However, the current flip-chip bonding technology still has a limit value on the process capability. Therefore, when the thickness of the wafer used is less than the limit value of the process capability, fragments are prone to occur during the flip-chip bonding process, so that the process Yield decreases. In addition, wafers with a small thickness are easily broken during the dicing process, so that the process yield is reduced.

Contents of the invention

The invention provides a packaging process, which can manufacture a packaging structure formed by stacking chips of various sizes, and has a high process yield.

The invention provides a packaging structure, which arranges a large-size chip on a small-size chip.

In order to specifically describe the content of the present invention, a packaging process is proposed here as follows. Firstly, a bearing plate is provided, on which an adhesive layer is disposed. Next, a plurality of first semiconductor elements are arranged on the adhesive layer, and the first semiconductor elements are separated from each other and respectively fixed on the carrier board through the adhesive layer. Then, a first encapsulant is formed on the carrier board, the first encapsulant covers the sidewall of the first semiconductor element and fills the gap between the first semiconductor elements, so that the first semiconductor element and the first encapsulant form a chip array plate. After that, a plurality of second semiconductor elements are respectively flip-chip bonded to the first semiconductor element. Next, a second encapsulant is formed on the chip array board, the second encapsulant at least covers the sidewalls of the second semiconductor elements and fills the gaps between the second semiconductor elements. Then, the chip array plate and the adhesive layer were separated. After that, the second encapsulant and the first encapsulant are cut along the gap between the second semiconductor elements to form a plurality of chip packaging units.

In an embodiment of the present invention, the above-mentioned first semiconductor element has a plurality of TSV structures, and the packaging process further includes grinding the chip array plate after forming the chip array plate, so as to thin the chip array plate and expose the first The end face of the TSV structure of the semiconductor element.

In an embodiment of the present invention, the above method of grinding the chip array plate includes grinding the chip array plate until the thickness of the chip array plate is substantially less than or equal to 4 mils.

In an embodiment of the present invention, the above packaging process further includes forming a plurality of first primers separated from each other on the first semiconductor element after forming the chip array board, wherein each first primer covers the corresponding first The semiconductor element and the part of the first encapsulant surrounding the corresponding first semiconductor element, and when the second semiconductor element is respectively flip-chip bonded to the first semiconductor element, the plurality of conductive bumps of each second semiconductor element pass through the corresponding The first primer is used to bond with the corresponding first semiconductor element.

In an embodiment of the present invention, the above packaging process further includes disposing the chip packaging unit on the circuit substrate, so that the first semiconductor element is electrically and structurally connected to the circuit substrate.

In an embodiment of the present invention, the above packaging process further includes forming a second primer on the circuit substrate, so that the second primer is located between the first semiconductor element of the chip packaging unit and the circuit substrate and covers the first semiconductor. Multiple conductive bumps for a component.

In an embodiment of the present invention, the above packaging process further includes forming a third encapsulant on the circuit substrate, and the third encapsulant at least covers the sidewall of the chip packaging unit.

In order to specifically describe the content of the present invention, a package structure including a first semiconductor element, a first encapsulant, a second semiconductor element and a second encapsulant is proposed here. The first encapsulant encapsulates the sidewall of the first semiconductor element. The second semiconductor element is disposed on the first semiconductor element and part of the first encapsulant, and the size of the second semiconductor element is larger than that of the first semiconductor element. The second encapsulant at least covers the sidewall of the second semiconductor element and the first encapsulant, wherein the first encapsulant and the second encapsulant are molded separately.

In an embodiment of the present invention, the sidewall of the above-mentioned first encapsulant is aligned with the sidewall of the second encapsulant.

In an embodiment of the present invention, the first top surface of the above-mentioned first encapsulant facing the second semiconductor element is aligned with the second top surface of the first semiconductor element facing the second semiconductor element.

In an embodiment of the present invention, the thickness of the above-mentioned first encapsulant is substantially equal to the thickness of the first semiconductor element.

In an embodiment of the present invention, the above-mentioned second semiconductor element has a plurality of conductive bumps located between the second semiconductor element and the first semiconductor element, and the packaging structure further includes a primer, which is disposed between the second semiconductor element and the first semiconductor element. Between the first semiconductor element and between the second semiconductor element and the first encapsulant to cover the conductive bump of the second semiconductor element.

In an embodiment of the present invention, the thickness of the above-mentioned first semiconductor element is substantially less than or equal to 4 mils.

In an embodiment of the present invention, the above-mentioned second encapsulant also covers the top surface of the second semiconductor element away from the first semiconductor element.

In an embodiment of the present invention, the above-mentioned second encapsulant exposes the top surface of the second semiconductor element away from the first semiconductor element.

In an embodiment of the present invention, a plurality of conductive bumps are disposed on the bottom surface of the above-mentioned first semiconductor element away from the second semiconductor element.

In an embodiment of the present invention, the above package structure further includes a circuit substrate, the first semiconductor element is disposed on the circuit substrate, and the conductive bump is located between the first semiconductor element and the circuit substrate.

In an embodiment of the present invention, the above packaging structure further includes a primer disposed between the first semiconductor element and the circuit substrate to cover the conductive bumps.

In an embodiment of the present invention, the above-mentioned encapsulation structure further includes a third encapsulant disposed on the circuit substrate and covering at least the sidewalls of the first encapsulant and the second encapsulant.

Based on the above, the present invention can produce a packaging structure in which chips of various sizes are stacked on each other. In addition, since the second encapsulant can strengthen the chip array plate with a relatively small thickness, it can firmly connect all the second semiconductor elements and all the first semiconductor elements, and can be used in the process of forming chip packaging units by dicing. , to avoid chip array plate fragmentation, thereby improving process yield.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A-1I are cross-sectional views of the packaging process of the embodiment of the present invention.

2A-2D are cross-sectional views illustrating a packaging process according to another embodiment of the present invention.

Explanation of reference signs

100, 200: package structure

110: Loading board

120: Adhesive layer

130: The first semiconductor element

132: Conductive bump

134, 142, 164, 172, W, W1: side wall

136, 144, 166: top surface

138: opening

140: The first packaging colloid

150, 190: primer

160: Second semiconductor element

162: Conductive bump

168, 182: bottom surface

170, 210: the second encapsulant

180: circuit substrate

220, M: the third packaging colloid

A: Chip array board

C1, C2: chip packaging unit

D: conductive material

G1, G2: Gap

I: insulating layer

S: solder ball

T, T1, T2: Thickness

V: TSV structure

Detailed ways

1A-1I are cross-sectional views of the packaging process of the embodiment of the present invention.

First, please refer to FIG. 1A , a carrier board 110 is provided, and the shape and size of the carrier board 110 may be similar to a wafer. An adhesive layer 120 is disposed on the carrier board 110 . Next, a plurality of first semiconductor elements 130 are disposed on the adhesive layer 120 , and these first semiconductor elements 130 are separated from each other and respectively fixed on the carrier board 110 through the adhesive layer 120 . In this embodiment, the plurality of conductive bumps 132 of the first chip 130 may be buried in the adhesive layer 120 .

In detail, in this embodiment, before disposing the first semiconductor element 130 on the adhesive layer 120, a plurality of openings 138 with a high aspect ratio may be formed in the first semiconductor element 130, and the openings 138 The insulating layer I is formed on the inner wall of the hole 138, and then, the conductive material D is filled in each opening 138, and the insulating layer I is separated between the conductive material D and the inner wall of the opening 138, and then formed on each conductive material D Conductive bumps 132 .

Then, please refer to FIG. 1B , for example, a first encapsulant 140 is formed on the carrier board 110 by printing or molding, wherein the first encapsulant 140 covers the sidewall 134 of the first semiconductor element 130 And fill up the gap G1 between the first semiconductor elements 130 , so that the first semiconductor elements 130 and the first encapsulant 140 form a chip array board A. Specifically, in this embodiment, the chip array board A refers to a board-shaped structure composed of the first encapsulant 140 and all the first semiconductor elements 130 .

Afterwards, please refer to FIG. 1C , in this embodiment, the chip array plate A may be ground to thin the chip array plate A and expose the conductive material D. Referring to FIG. In this embodiment, the chip array plate A may be ground until the thickness T of the chip array plate A is substantially less than or equal to 4 mils. In this embodiment, the conductive material D, the insulating layer I and the opening 138 can constitute a through-silicon via (TSV) structure V. Referring to FIG.

It can be seen from the foregoing that the first semiconductor element 130 is electrically connected to the conductive bump 132 and other chips (not shown) that will be stacked on the first semiconductor element 130 by using the Through-Silicon Via (TSV) technology. connect. The TSV technology is, for example, fabricating conductive channels inside a chip or a wafer to form a vertical TSV structure V, which can maximize the stacking density of the first semiconductor elements 130 in three dimensions and minimize the external dimensions. Therefore, signals between the first semiconductor element 130 and other chips that will be stacked on the first semiconductor element 130 can be transmitted up and down through the TSV structure V, so as to reduce the length of the signal transmission path between the chips and reduce the Signal delay and power consumption.

Next, please refer to FIG. 1D. In this embodiment, a plurality of primers 150 separated from each other may be formed on the chip array board A by, for example, dispensing or screen printing, wherein each primer 150 covers the corresponding first A portion of the semiconductor element 130 and the first encapsulant 140 surrounding the corresponding first semiconductor element 130 . In detail, each primer 150 not only completely covers the corresponding first semiconductor device 130 , but also covers the portion of the first encapsulant 140 surrounding the corresponding first semiconductor device 130 . In other words, the projected area of the primer 150 on the carrier board 110 is larger than the projected area of the first semiconductor element 130 on the carrier board 110 . The material of the primer 150 includes non-contact paste (NCP1) or non-contact film (NCF1).

Then, referring to FIG. 1E , a plurality of second semiconductor elements 160 are respectively flip-chip bonded to the first semiconductor element 130, so that the plurality of conductive bumps 162 of each second semiconductor element 160 are connected with the corresponding primer 150 through the corresponding primer 150. The corresponding TSV structure V of the first semiconductor device 130 is bonded. In this embodiment, the projected area of the second semiconductor element 160 on the carrier board 110 is greater than the projected area of the first semiconductor element 130 on the carrier board 110 . In other words, the size of the second semiconductor element 160 is larger than that of the first semiconductor element 130 .

Afterwards, please refer to FIG. 1F , for example, a second encapsulant 170 is formed on the chip array board A by printing or molding. The second encapsulant 170 can selectively cover the sidewall 164 of the second semiconductor element 160 and the second The top surfaces 166 of the two semiconductor elements 160 away from the corresponding first semiconductor elements 130 fill up the gap G2 between the second semiconductor elements 160 to protect the second semiconductor elements 160 . It is worth noting that since the second encapsulant 170 fills the gap G2 between the second semiconductor elements 160, the second encapsulant 170 can strengthen the chip array board A with a relatively small thickness to firmly connect all the second semiconductor elements 160. The semiconductor element 160 and all the first semiconductor elements 130 . In addition, in other embodiments, the step of forming the primer 150 may be replaced by filling a portion of the second encapsulant 170 between the second semiconductor element 160 and the chip array board A. Referring to FIG.

Then, referring to FIG. 1G , the chip array plate A and the adhesive layer 120 are separated. Afterwards, referring to FIG. 1G and FIG. 1H , the second encapsulant 170 and the first encapsulant 140 are cut along the gap G2 between the second semiconductor elements 160 to form a plurality of chip packaging units C1 .

As can be seen from the foregoing, in this embodiment, a plurality of first semiconductor elements 130 are firstly connected with a first encapsulant 140 to form a chip array board A, and then a plurality of second semiconductor elements 160 are respectively arranged on the first surfaces of the chip array board A. The semiconductor element 130 is connected with the second encapsulant 170 , and then the first encapsulant 140 and the second encapsulant 170 are cut to form a plurality of chip packaging units C1 . In other words, in this embodiment, the first encapsulant 140 and the second encapsulant 170 are used to fix and connect the first semiconductor element 130 and the second semiconductor element 160 , and then the first encapsulant 140 and the second encapsulant 170 are cut to form A plurality of chip packaging units C1.

In this way, this embodiment is not limited to the size relationship between the first semiconductor element 130 and the second semiconductor element 160, that is, this embodiment can make the size of the first semiconductor element 130 larger than or equal to or smaller than that of the second semiconductor element 160 size chip packaging unit C1. In other words, in this embodiment, a package structure formed by stacking chips of various sizes can be produced. In addition, since the second encapsulant 170 can strengthen the chip array board A with a relatively small thickness, the chip array board A can be prevented from breaking during the process of forming the chip package unit C1 by cutting, thereby improving the process yield.

Next, please refer to FIG. 1H and FIG. 1I at the same time. In this embodiment, a primer 190 can be formed on a circuit substrate 180 (such as a printed circuit board), and the chip package unit C1 can be disposed on the circuit substrate 180, so that The first semiconductor element 130 can be electrically and structurally connected to the circuit substrate 180 through the conductive bump 132, and the primer 190 is located between the first semiconductor element 130 and the circuit substrate 180 of the chip packaging unit C1 to cover the first semiconductor. The conductive bump 132 of the component 130 .

Please refer to FIG. 1I. In this embodiment, for example, a third encapsulant M is formed on the circuit substrate 180 by printing or molding. The third encapsulant M can cover the sidewall W of the chip packaging unit C1 and the second The top surface 166 of the semiconductor element 160 . In detail, part of the third encapsulant M is located on the portion of the second encapsulant 170 covering the top surface 166 , in other words, the third encapsulant M indirectly covers the top surface 166 of the second semiconductor device 160 . In other unillustrated embodiments, the third encapsulant M may cover the sidewall W of the chip package unit C1 and expose the portion of the second encapsulant 170 covering the top surface 166 .

In addition, in other embodiments, the step of forming the primer 190 may be replaced by filling a part of the third encapsulant M between the first semiconductor element 130 and the circuit substrate 180 . In addition, in order to allow the chip package unit C1 to be electrically connected to other electronic components through the circuit substrate 180, a plurality of solder balls S may be formed on the bottom surface 182 of the circuit substrate 180 away from the chip package unit C1, and the solder balls S and The circuit substrate 180 is electrically connected. At this point, the packaging structure 100 of this embodiment has been preliminarily completed.

The package structure 100 of FIG. 1I will be described in detail below.

Referring to FIG. 1I , the package structure 100 of this embodiment includes a first semiconductor element 130 , a first encapsulant 140 , a second semiconductor element 160 and a second encapsulant 170 . In this embodiment, the thickness T2 of the first semiconductor element 130 is substantially less than or equal to 4 mils, for example, the thickness T2 of the first semiconductor element 130 is substantially 2 mils.

The first encapsulant 140 covers the sidewall 134 of the first semiconductor device 130 . In this embodiment, the top surface 144 of the first encapsulant 140 facing the second semiconductor element 160 can be aligned with the top surface 136 of the first semiconductor element 130 facing the second semiconductor element 160 , and the first encapsulant 140 The thickness T1 may be substantially equal to the thickness T2 of the first semiconductor element 130 .

The second semiconductor element 160 is disposed on the first semiconductor element 130 and part of the first encapsulant 140 , and the size of the second semiconductor element 160 is larger than that of the first semiconductor element 130 . In other words, the area of the bottom surface 168 facing the first semiconductor element 130 of the second semiconductor element 160 is larger than the area of the top surface 136 of the first semiconductor element 130 .

It is worth noting that the packaging structure 100 of this embodiment is to arrange a chip with a larger size on a chip with a smaller size. In a package structure on a small size chip. In addition, since the thickness T2 of the first semiconductor element 130 in this embodiment is small (for example, less than or equal to 4 mils), the overall thickness of the package structure 100 can be reduced.

The second encapsulant 170 covers the sidewall 164 of the second semiconductor element 160, the top surface 166 of the second semiconductor element 160 away from the first semiconductor element 130, and the first encapsulant 140, wherein the first encapsulant 140 and the second encapsulant 170 can be molded separately, and the sidewall 142 of the first encapsulant 140 can be cut flush with the sidewall 172 of the second encapsulant 170 .

In this embodiment, a plurality of conductive bumps 162 are disposed on the bottom surface 168 of the second semiconductor device 160 to be electrically connected to the first semiconductor device 130 . In order to protect the conductive bumps 162, a primer 150 can be disposed between the second semiconductor element 160 and the first semiconductor element 130 and between the second semiconductor element 160 and the first encapsulant 140, so that the primer 150 covers the conductive bumps. Block 162. In addition, in other embodiments, there may be no primer 150, that is, part of the second encapsulant 170 may be filled between the second semiconductor element 160 and the first semiconductor element 130 and between the second semiconductor element 160 and the first package. No primer 150 is required between the colloids 140 .

In this embodiment, the first semiconductor element 130 can be disposed on the circuit substrate 180 such that the plurality of conductive bumps 132 of the first semiconductor element 130 are electrically connected to the circuit substrate 180 . To protect the conductive bumps 132 , a primer 190 can be disposed between the first semiconductor element 130 and the circuit substrate 180 , so that the primer 190 covers the conductive bumps 132 .

In addition, in this embodiment, a third encapsulant M can be disposed on the circuit substrate 180, and the third encapsulant M covers the sidewall 142 of the first encapsulant 140, the sidewall 172 of the second encapsulant 170 and the second semiconductor. The top surface 166 of the component 160 away from the first semiconductor component 130 . In detail, part of the third encapsulant M is located on the portion of the second encapsulant 170 covering the top surface 166 of the second semiconductor device 160 , in other words, the third encapsulant M indirectly covers the top surface 166 . In other embodiments, the third encapsulant M may cover the sidewall 142 of the first encapsulant 140 and the sidewall 172 of the second encapsulant 170 , and expose the top of the second encapsulant 170 covering the second semiconductor element 160 . portion of face 166 . In addition, in other embodiments, there may be no primer 190 , that is, part of the third encapsulant M may be filled between the first semiconductor device 130 and the circuit substrate 180 without disposing the primer 190 .

In addition, a plurality of solder balls S may be disposed on the bottom surface 182 of the circuit substrate 180 away from the first semiconductor element 130, the solder balls S are electrically connected to the circuit substrate 180, and the circuit substrate 180 may be electrically connected to the circuit substrate 180 through the solder balls S. Other electronic components (such as circuit boards).

2A-2D are cross-sectional views illustrating a packaging process according to another embodiment of the present invention.

In this embodiment, the processes shown in FIG. 1A to FIG. 1E can be performed first, and then, referring to FIG. 2A , a second encapsulant 210 is formed on the chip array board A, and the second encapsulant 210 can selectively cover the second semiconductor. The sidewall 164 of the device 160 exposes the top surface 166 of the second semiconductor device 160 away from the corresponding first semiconductor device 130 , and fills the gap G2 between the second semiconductor devices 160 to protect the second semiconductor device 160 .

Then, referring to FIG. 2B , the chip array plate A and the adhesive layer 120 are separated. Afterwards, referring to FIG. 2B and FIG. 2C , the second encapsulant 170 and the first encapsulant 140 are cut along the gap G2 between the second semiconductor elements 160 to form a plurality of chip packaging units C2 . Next, in this embodiment, an underfill 190 may be formed on the circuit substrate 180 .

Next, please refer to FIG. 2C and FIG. 2D at the same time. In this embodiment, the chip package unit C2 can be disposed on the circuit substrate 180, so that the first semiconductor element 130 is electrically and structurally connected to the circuit through the conductive bump 132. The substrate 180 , and the primer 190 is positioned between the first semiconductor element 130 of the chip packaging unit C2 and the circuit substrate 180 to cover the conductive bumps 132 of the first semiconductor element 130 .

2D, in this embodiment, a third encapsulant 220 can be formed on the circuit substrate 180, and the third encapsulant 220 can cover the side wall W1 of the chip packaging unit C2 and expose the top surface of the second semiconductor element 160. 166. At this point, the packaging structure 200 of this embodiment has been preliminarily completed. In addition, in other unillustrated embodiments, the third encapsulant 220 may cover the sidewall W1 of the chip packaging unit C2 and the top surface 166 of the second semiconductor element 160 .

The structural parts of the package structure 200 in FIG. 2D will be described in detail below.

Please refer to FIG. 2D , the packaging structure 200 of this embodiment is similar to the packaging structure 100 of FIG. 1I , the difference between the two is that the second encapsulant 210 and the third encapsulant 220 of the encapsulation structure 200 jointly expose the second semiconductor element. 160 of the top surface 166 . Therefore, the package structure 200 can conduct the heat generated by the first semiconductor device 130 and the second semiconductor device 160 to the external environment through the top surface 166 of the second semiconductor device 160 , thereby improving the heat dissipation efficiency of the package structure 200 .

In summary, the present invention uses the first encapsulant and the second encapsulant to fix and connect the first semiconductor element and the second semiconductor element, and then forms a plurality of chips by cutting the first encapsulant and the second encapsulant packaging unit. Therefore, the present invention can produce a packaging structure in which chips of various sizes are stacked on each other. In addition, since the second encapsulant can strengthen the chip array plate with a relatively small thickness, it can firmly connect all the second semiconductor elements and all the first semiconductor elements, and can be used in the process of forming chip packaging units by dicing. , to avoid chip array plate fragmentation, thereby improving process yield.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (6)

1. A packaging process, comprising: providing a bearing plate, the bearing plate is configured with an adhesive layer; A plurality of first semiconductor elements are disposed on the adhesive layer, and the plurality of first semiconductor elements are separated from each other and respectively fixed on the carrier board through the adhesive layer, wherein each of the first semiconductor elements has a plurality of through-silicon Through-grain structure; A first encapsulant is formed on the carrier board, the first encapsulant covers the sidewalls of the plurality of first semiconductor elements and fills the gaps between the plurality of first semiconductor elements, so that the plurality of first semiconductor elements The element and the first encapsulant form a chip array board; After forming the chip array plate, grinding the chip array plate to thin the chip array plate and expose the end surfaces of the plurality of TSV structures of each of the first semiconductor elements; A plurality of second semiconductor elements are respectively flip-chip bonded to the plurality of first semiconductor elements of the chip array board, so that the plurality of conductive bumps of each of the second semiconductor elements are connected to the corresponding conductive bumps of each of the first semiconductor elements The end face bonding of the plurality of TSV structures, wherein the projected area of the second semiconductor element on the carrier plate is larger than the projected area of the first semiconductor element on the carrier plate; forming a second encapsulant on the chip array board, the second encapsulant at least covers the sidewalls of the plurality of second semiconductor elements and fills the gaps between the plurality of second semiconductor elements; separating the chip array board from the adhesive layer; and The second encapsulant and the first encapsulant are cut along gaps between the plurality of second semiconductor elements to form a plurality of chip packaging units. 2. The packaging process according to claim 1, wherein the method of grinding the chip array plate comprises: Grinding the chip array plate until the thickness of the chip array plate is substantially less than or equal to 4 mils. 3. The packaging process according to claim 1, further comprising: After the chip array board is formed, a plurality of first primers separated from each other are respectively formed on the plurality of first semiconductor elements, wherein each of the first primers covers the corresponding first semiconductor element and the first encapsulant The part surrounding the corresponding first semiconductor element, and when the plurality of second semiconductor elements are respectively flip-chip bonded to the plurality of first semiconductor elements, the plurality of conductive bumps of each second semiconductor element pass through The corresponding first primer is bonded with the corresponding first semiconductor element. 4. The packaging process according to claim 1, further comprising: The chip packaging unit is disposed on the circuit substrate, so that the first semiconductor element is electrically and structurally connected to the circuit substrate. 5. The packaging process according to claim 4, further comprising: A second primer is formed on the circuit substrate, so that the second primer is located between the first semiconductor element of the chip packaging unit and the circuit substrate and covers a plurality of conductive bumps of the first semiconductor element. 6. The packaging process according to claim 4, further comprising: A third encapsulant is formed on the circuit substrate, and the third encapsulant at least covers the sidewall of the chip package unit.

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