CN102590731A - Method for realizing silicon read-out circuit test in infrared focal plane array - Google Patents

Abstract

The invention relates to a method for realizing silicon readout circuit testing in an infrared focal plane array detector, which is characterized in that the interconnection between the silicon readout circuit and the test substrate is realized by adopting a flip-chip method; the silicon test substrate and the silicon readout circuit are realized After the butt interconnection of the test substrate, the rearrangement of the silicon test substrate pads is realized by rearranging the pads on the test substrate; a more complex layout design is adopted to avoid complicated processes to reduce the number of pads to be arranged; The pads on the test substrate are manufactured by the -off process, and a thin layer of indium plating is made on the pads to be rearranged by indium electroplating; the connection between the silicon substrate and the PCB is realized by the wire bonding process. The interconnection of the final readout circuit, signal input and output are all completed on the PCB. The invention combines layout design and simple process to realize the test of the silicon readout circuit.

Description

A Method for Realizing Testing of Silicon Readout Circuit in Infrared Focal Plane Array Detector

technical field

The invention relates to a method for testing silicon readout circuits in infrared focal plane array detectors, more precisely a method for testing silicon readout circuits without using expensive infrared focal plane devices The method belongs to the field of packaging and testing of semiconductor integrated circuits.

Background technique

In the cooled infrared focal plane imaging system, the core chip is shown in Figure 1, which is composed of a focal plane array device chip 101 and a readout circuit 103 flip-chip interconnected through indium bumps 102, wherein the infrared focal plane array device The chip receives the infrared signal radiated by the detected object and converts it into an electrical signal to realize the photoelectric conversion process. The readout circuit is responsible for the photoelectric signal acquisition and amplification processing. In the chip fabrication process, the focal plane device and the silicon readout circuit are fabricated separately; after the focal plane device and the silicon readout circuit are fabricated, their testing is crucial. The simplest and commonly used test method is to test the performance of the assembled chip after directly flip-chip-docking the focal plane device array device and the silicon readout circuit. Obviously, this method has its disadvantages: (1) In order to test the silicon readout chip, it is necessary to ensure the normal performance of the infrared focal plane array device, which is not easy to do; (2) the general cooled focal plane detector is based on HgCdTe, AsInGa and other non-industrial common semiconductor materials are made, the manufacturing process is complicated and the cost is high, while the silicon readout circuit manufacturing technology is mature and the cost is relatively low. It is not a wise choice to use high-cost chips to test low-cost chips. . Therefore, it is necessary to adopt a method with low cost and simple process (without making a well-made focal plane array device) to realize the test of the performance of the silicon readout circuit, and this is exactly the problem to be solved by the present invention.

Contents of the invention

The purpose of the present invention is to provide a method for realizing the test of the silicon readout circuit in the infrared focal plane array detector. In order to explain the principle of the present invention, the principle of this type of infrared photoelectricity is briefly explained: the focal plane array device is a close-packed array of photodiodes made on semiconductor materials such as HgCdTe and AsInGa, and each photodiode is a pixel. These pixels receive the infrared light information radiated by the measured object and convert it into an electrical signal to realize photoelectric conversion; on the other hand, the silicon readout circuit collects the electrical signal through the indium bump, and amplifies it and other processing. In this process, the focal plane array device is responsible for the photoelectric signal input and the readout circuit is responsible for the processing of the photoelectric signal. If the laboratory power supply is used to carry out the weak current instead of the input of the weak current signal of the focal plane device, the test of the silicon readout circuit can be realized without using an expensive infrared focal plane array device. It can be seen from Figure 1 that the electrodes on the silicon readout circuit are very small, and the side length of the pad on the readout circuit chip is generally a square of 60-80 μm. It is impossible to directly use laboratory equipment to input signals to the silicon readout circuit through these electrodes. of. In order to use the laboratory power supply for current input, these densely packed electrodes need to be rearranged, and finally realize the input and output of weak electrical signals on the PCB, and realize the detection of the silicon readout circuit. It can be seen from the test principle that the pad redistribution on the readout circuit chip is the key to realize the test of the silicon readout circuit, which is also the problem to be solved by the present invention.

The arrangement of the signal output and input ports on a readout circuit chip is actually designed as shown in FIG. 2 . In this circuit, 201 is 13 signal input and output terminals, which realize functions such as circuit control and photoelectric signal amplification and output. Since these 13 terminals have different functions, the pads corresponding to these 13 terminals must be rearranged to correspond to the PCB. board. 202 is a 32×32 array unit, which realizes the reception of photoelectric signals. The geometric parameters related to the pads in this readout circuit chip are: the horizontal spacing between the pads is 110 μm, the vertical spacing is 130 μm, the pads are squares of 60 μm×60 μm, the opening of the passivation layer on the pads is circular, and the pads are located in the square. In the center of the disk, its diameter is 30 μm, on which a circular Ti/Pt/Au UBM layer with a diameter of 40 μm and an indium solder ball with a height of about 40 μm are fabricated. After the infrared focal plane device is flip-chip interconnected with the circuit, it is equivalent to having 32×32=1024 signal input terminals. Note that the spacing on the pads on the test circuit chip is only 110 μm and 130 μm, so that such a dense 32×32 pad array is completely rearranged on the PCB board, and such a dense pad is drawn out on a layer of substrate. Its wiring process will be very difficult, and one method is to make a silicon-based multilayer test substrate (the PCB board cannot meet the size requirements in the test). However, making such a multi-layer substrate will involve complex semiconductor processes such as through-silicon vias (TSV), chemical mechanical polishing (CMP), electroplating and ball planting, which is difficult to manufacture and has a low success rate. It is noted that the photodiodes in the photodiode array have the same function, so it can be considered to reduce the number of arranged electrodes and simplify the pad arrangement process. In the test, after testing a small number of signal input terminals, the yield rate of these input terminals can be calculated according to the test results to infer the yield rate of 32×32 input terminals, so as to realize the test of the silicon readout circuit. In other words, there is no need to rearrange all the input electrodes during the test, such as uniformly sampling a certain number of pads from the 32×32 array, such as every 1, 2, 3... Extraction, rearrangement of these extracted pads will become much simpler. For example, if 16×16 pads are extracted from 32×32 pads (accounting for 25% of the total pads), the horizontal spacing between the extracted pads becomes 220 μm, and the vertical spacing becomes 260 μm. For pads of this size and size The difficulty of array lead-out and rearrangement can be solved through more complex layout design, and the process realization part will become simple. All pads are rearranged, the number of pads is 32×32+13=1037, the number of pads that needs to be rearranged every other pad is 16×16+13=269, and the number of pads needs to be rearranged every two pads The most important thing is that the number of pads is 10×10+13=113, and the number of pads that needs to be rearranged every two pads is 8×8+13=77. After simplified testing, the reduction in the number of pads can be seen

FIG. 3 shows 13 control terminal pads 201 corresponding to the readout circuit on the flip-chip substrate and a uniformly extracted 16×16 array 301. FIG. 4 shows the 16×16+13= A schematic diagram of rearranging pads 402 of 269 pads 401 . As shown in FIG. 6 , during testing, the readout circuit 103 is flip-chip mounted on the substrate 603 to realize the above-mentioned rearrangement of the 269 pads on the silicon test substrate. Finally, the rearranged pads are connected to the PCB 604 through gold wires 606 , and the final circuit testing operations are performed on the PCB.

In summary, realizing the rearrangement of the electrode pads on the silicon readout circuit is the key to realizing the purpose of the invention, and the electrodes on the silicon readout circuit are very small (300 μm×300 μm square), so the present invention proposes a Simplified method, combined with more complicated layout design and simpler process, can realize the design of silicon readout circuit.

A simple and low-cost focal plane infrared photoelectric chip readout circuit testing method provided by the present invention includes:

(1) The interconnection between the silicon readout circuit and the test substrate is realized by flip-chip;

(2) After the butt interconnection between the silicon test substrate and the silicon readout circuit is realized, the rearrangement of the silicon test substrate pads is realized by rearranging the pads on the test substrate;

(3) Reduce the number of pads to be arranged, and adopt more complex layout design to avoid complicated process;

(4) Adopt the lift-off process to realize the production of pads on the test substrate, and make a thin layer of indium plating on the pads to be rearranged by indium electroplating;

(5) The interconnection between the silicon substrate and the PCB board is realized through the wire bonding process, and finally the control of the readout circuit, signal input and output are all completed on the PCB board.

The specific steps are:

A: Fabrication of flip-chip test substrate

(a) Etch the aluminum pad on the silicon wafer

(1) A layer of oxide layer is thermally oxidized on a four-inch silicon wafer to obtain a flat and insulating substrate;

(2) sputtering aluminum film on the oxidized silicon wafer;

(3) Aluminum pads and aluminum wiring are corroded with aluminum etching solution after thin film photolithography;

(b) Passivation layer fabrication

(1) Deposit a layer of SiO ₂ as a passivation layer by PECVD (plasma-enhanced chemical vapor deposition, ion-enhanced vapor deposition method);

(2) After photolithography, RIE (Reaction Ion Etch, reactive ion etching) is used to open the passivation layer and open on the Al pad;

(c) Making the seed layer

(1) Photolithography of thin film and edge cleaning of silicon wafer;

(2) Sputter the Ti/Pt/Au seed layer, and the part on the pad is also used as the UBM (underbumpmetallization) layer;

(d) Thin film photolithography

(1) Thin glue lithography, after the lithography is completed, use an edge cleaning machine to clean the edge of the wafer;

(e) Indium plating on Ti/Pt/Au UBM

(1) The silicon wafer is placed in an indium electroplating tank for electroplating, and the indium coating is obtained by electroplating;

(f) removing the seed layer;

(1) Put the electroplated silicon wafer in acetone to remove the glue. After confirming that the photoresist is removed, the seed layer is removed by ultrasound. The final result is to electroplate the indium layer on the 269 pads that need to be rearranged; There is no indium plating on the pad after cloth, because the wire-bonding process needs to be used later, and the surface of gold sputtering is required in this process;

B: Flip chip the silicon readout circuit on the test substrate

(1) Flip-chip welding the silicon readout circuit to the flip-chip substrate made by the above process (before flip-chip welding, the silicon readout circuit has been implanted with indium solder balls by electroplating;

C: Realize the interconnection between the test substrate and the PCB board by wire bonding

(1) Design a pad corresponding to the pad on the silicon substrate on the PCB;

(2) Use the wire bonding method to realize the connection between the pad on the silicon substrate and the small pad on the PCB;

D: Make large pads (2mm×2mm) corresponding to small pads (300μm×300μm) on the PCB, use these large pads, combined with laboratory equipment to control the input and output signals of weak signals, Enables testing of silicon readout circuits.

Description of drawings

Fig. 1 is the core chip of the infrared focal plane, which is mainly composed of an infrared focal plane array 101, an indium bump 102 for interconnection and a silicon readout circuit 103;

2 is a schematic diagram of a silicon readout circuit illustrating the test principle. In this circuit, 13 pads 201 are used as circuit control terminals and signal test terminals and 32×32 current signal input ports 202 corresponding to focal plane array diodes;

FIG. 3 uniformly extracts 16×16 input terminals 301 and 201 composed of 13 pads corresponding to the control terminal and the signal test terminal of the readout circuit in the 32×32 array;

Fig. 4 is the pad 402 rearranged on the test substrate with 16*16+13=269 pads 401 in the readout circuit;

Figure 5 is a flow chart of test substrate fabrication; (1) substrate fabrication, (2) corroding aluminum Pad and Al wiring, (3) passivation layer opening, (4) sputtering UBM layer, (5) depositing indium layer, ( 6) Make pads;

FIG. 6 shows that the silicon readout circuit 103 is flipped on the silicon test substrate 603 through the indium bump array 102, and then the rearranged pads 402 are connected to the corresponding small pads 607 on the PCB 604 through gold wires 606. Connected to each other, through the pads 608 on the PCB board 604 to realize signal input, output and circuit control.

Detailed ways

In the present invention, the main manufacturing steps are substrate manufacturing and chip flip-chip technology.

(A) Substrate fabrication

The specific process steps of substrate fabrication are shown in Figure (5).

优先为

的SiO₂ 502作为绝缘层，然后在其上溅射一层

厚的Al层503；In Fig. 5(1), the silicon wafer 501 is used as the substrate, and the thickness of the oxide layer is

Priority is

SiO ₂ 502 as an insulating layer, and then sputter a layer on it

thick Al layer 503;

In Fig. 5(2), 1.5-2 μm, preferably 1.7 μm S1912 thin glue is coated on the substrate of sputtering 503, and then photolithography is performed. After the photolithography is completed, the aluminum pad and Al wiring 504 are etched in the Al etching solution;

的SiO2作为钝化层505。紧接着再一次涂覆1.7μm的S1912薄胶并光刻，然后用RIE(离子反应刻蚀)去除Al焊盘504上的部分SiO2以实现钝化层开口506；In Fig. 5(3), in order to protect the Al pad and the Al wiring, a layer with a thickness of

SiO2 is used as the passivation layer 505. Then apply 1.7 μm S1912 thin glue again and photolithography, and then use RIE (reactive ion etching) to remove part of SiO2 on the Al pad 504 to realize the passivation layer opening 506;

508；为在其后的种子层比较容易去除，光刻胶厚度为2-3μm之间；溅射Ti/Pt/Au种子层之前需对硅片进行清边，以使种子层与硅片边缘形成比较牢靠的接触；光刻完成后用磁控溅射在衬底上溅射Ti/Pt/Au

作为种子层508，铟凸点下的部分将作为其UBM层，其中溅射的金的厚度为

主要是为了在图所示的外围焊盘上能够顺利打线。In Figure 5(4), S1912 thin glue is coated again and photolithography 507 is sputtered on the seed layer and UBM layer Ti/Pt/Au

508; In order to remove the subsequent seed layer relatively easily, the thickness of the photoresist is between 2-3 μm; before sputtering the Ti/Pt/Au seed layer, the silicon wafer needs to be cleaned to make the seed layer and the edge of the silicon wafer Form a relatively strong contact; sputter Ti/Pt/Au on the substrate with magnetron sputtering after photolithography is completed

As a seed layer 508, the portion under the indium bump will serve as its UBM layer, where the sputtered gold has a thickness of

It is mainly for smooth wiring on the peripheral pads shown in the figure.

In Fig. 5(5), the S1912 photoresist of 2-3 μm is coated and photoetched, and the 509 after photoetching is obtained; the silicon wafer is placed in the indium electroplating tank, and the current density of 5mA-15mA/ ^cm A layer of indium layer 510 with a thickness of 2-3 μm is deposited on the rearranged pads, and the indium layer is electroplated mainly to obtain a good soldering effect when the silicon readout circuit is flip-chip mounted on the silicon substrate;

In Fig. 5 (6), the above-mentioned processed silicon chip is placed in acetone and soaked for a sufficient time, after confirming that the photoresist 507 and 509 are removed, the silicon chip is placed in an ultrasonic device to remove the seed layer; Pad 511 of Pt/Au/In cross-section.

(B) Chip Flip Chip

As shown in FIG. 6 , flip-chip the silicon readout circuit chip 103 implanted with indium balls 102 and the manufactured silicon test substrate 603 . The karlsuss flip-chip welding machine is used in the flip-chip, and the process parameters are: the pressure of the suction head is 2-5kg, the temperature of the suction head is 100°C, and the welding time is 0.5-2min.

(C) Realize the interconnection between the test substrate and the PCB board by wire bonding

First, the pads corresponding to the pads on the silicon substrate are designed, and then the pads on the silicon substrate are connected to the small pads on the PCB by wire bonding.

(D) Flip-chip substrate and PCB interconnection

For the point to be tested, realize the interconnection between the pad 402 on the silicon substrate and the small pad 607 on the PCB 604 via the gold wire 606, and realize the input and output of electric signals such as the current and voltage of the control terminal and the output terminal via the large pad 608, and test Circuit silicon readout circuit performance. All signal input, output and control can be completed on the PCB board.

Claims (5)

1. A method for realizing the silicon readout circuit test in the infrared focal plane array detector, characterized in that: (1) The interconnection between the silicon readout circuit and the test substrate is realized by flip-chip; (2) After the butt interconnection between the silicon test substrate and the silicon readout circuit is realized, the rearrangement of the silicon test substrate pads is realized by rearranging the pads on the test substrate; (3) Adopt more complex layout design to avoid complex process to reduce the number of pads to be arranged; (4) Adopt the lift-off process to realize the production of pads on the test substrate, and make a thin layer of indium plating on the pads to be rearranged by indium electroplating; (5) The interconnection between the silicon substrate and the PCB board is realized through the wire bonding process, and finally the control of the readout circuit, signal input and output are all completed on the PCB board. 2. by the described method of claim 1, it is characterized in that concrete steps are: A: Fabrication of flip-chip test substrate (a) Etch the aluminum pad on the silicon wafer (1) A layer of oxide layer is thermally oxidized on a four-inch silicon wafer to obtain a flat and insulating substrate; (2) sputtering aluminum film on the oxidized silicon wafer; (3) Aluminum pads and aluminum wiring are corroded with aluminum etching solution after thin film photolithography; (b) Passivation layer fabrication (1) Deposit a layer of SiO with PECVD ₂ as a passivation layer; (2) RIE is used to open the passivation layer after photolithography, and an opening is made on the Al pad; (c) Making the seed layer (1) Photolithography of thin film and edge cleaning of silicon wafer; (2) Ti/Pt/Au seed layer is sputtered, and the part on the pad is used as the UBM layer at the same time; (d) Thin film photolithography (1) Thin glue lithography, after the lithography is completed, use an edge cleaning machine to clean the edge of the wafer; (e) Indium plating on Ti/Pt/Au UBM The silicon wafer is placed in an indium electroplating tank for electroplating, and the indium coating is obtained by electroplating; (f) removing the seed layer; Put the electroplated silicon wafer in acetone to remove the glue. After confirming that the photoresist is removed, the seed layer is removed by ultrasound. The final result is to electroplate the indium layer on the 269 pads that need to be rearranged; There is no indium coating on the disk, because the surface that needs to be sputtered with gold in the wire-bonding process will be used later; B: Flip chip the silicon readout circuit on the test substrate The silicon readout circuit is flip-chip welded to the flip-chip substrate made by the above process, and the flip-chip is adopted by a karlsuso flip-chip welding machine; C: Realize the interconnection between the test substrate and the PCB board by wire bonding (1) Design a pad corresponding to the pad on the silicon substrate on the PCB; (2) Use the wire bonding method to realize the connection between the pad on the silicon substrate and the small pad on the PCB; D: Make large pads corresponding to the small pads on the PCB, use these large pads, and combine the control of the input and output signals of weak signals by laboratory equipment to realize the test of the silicon readout circuit. 3. The method according to claim 2, characterized in that before (1) flip-chip welding in step B, indium solder balls have been implanted on the silicon readout circuit by electroplating. 4. by the described method of claim 2, it is characterized in that: (1) The oxide layer thickness described in step A is

(2) the aluminum film thickness described in step A is

(3) In step A (b) the thin glue for photolithography is S1912, with a thickness of 1.5-2 μm; (4) the thickness of the indium coating described in step A (e) is 2-3 μm; (5) In step B, the pressure of flip-chip tip is 2-5kg, the tip temperature is 100°C, and the welding time is 0.5-2min; (6) The size of the small pad in step C is 300 μm×300 μm, and the size of the large pad is 2 mm×2 mm. 5. The method according to claim 4, characterized in that the current density of the indium coating in (4) is 5-15 mA/cm ² .

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