CN102394606B - Jump-key (JK) trigger capable of defending power attack - Google Patents

Abstract

The invention discloses a JK flip-flop for defending against energy attacks, which is characterized in that it includes a first complementary signal generating circuit, a second complementary signal generating circuit, a flip-flop prototype circuit, a first master-slave latch unit, and a second master-slave latch unit, the third master-slave latch unit and the fourth master-slave latch unit, the flip-flop prototype circuit is connected with the first master-slave latch unit, the first master-slave latch unit is connected with the first complementary signal generating circuit, and the first The complementary signal generating circuit is connected with the third master-slave latch unit, the third master-slave latch unit is connected with the flip-flop prototype circuit, the flip-flop prototype circuit is connected with the second master-slave latch unit, and the second master-slave latch unit is connected with the The second complementary signal generating circuit is connected, the second complementary signal generating circuit is connected with the fourth master-slave latch unit, and the fourth master-slave latch unit is connected with the flip-flop prototype circuit; the advantage is that the energy consumption and the processed data are independent of each other and can be The consumption is stable, and it has good performance in defending against energy attacks.

Description

A JK flip-flop for defense against energy attack

technical field

The invention relates to a JK trigger, in particular to a JK trigger for defending against energy attacks.

Background technique

With the development of computer and communication technology, users have more and more urgent demands on the security of information storage, processing and transmission. The strategy of implementing cryptographic algorithms on encryption devices is generally adopted to achieve the purpose of protecting information security. However, in the process of executing cryptographic algorithms, physical devices always leak various information related to the cryptographic system itself, such as energy consumption, electromagnetic radiation, and running time. The process in which an attacker uses this information to attack an encryption device to obtain a key is called a Side Channel Attack (SCA). Among many side channel attack schemes, Differential Power Analysis (DPA) technology has been proved to be a more effective and easy-to-implement strategy, which poses a major threat to the security of cryptographic modules.

In a cryptographic system, a flip-flop is the most commonly used unit circuit with a memory function and can store information. It is widely used in logic devices such as registers, counters, and shift registers. The static complementary CMOS logic unit is the basic component of the traditional flip-flop, because it only consumes energy when the node state has 0→1, 1→0 jumps, and does not consume energy when the node state remains unchanged, so its energy consumption There is asymmetry, and this feature has become a breakthrough for differential energy attack technology to crack traditional encryption devices.

Contents of the invention

The technical problem to be solved by the present invention is to provide a JK flip-flop for defending against energy attacks that is independent of energy consumption and processed data and has stable energy consumption under the premise of ensuring correct logic functions.

The technical solution adopted by the present invention to solve the above technical problems is: a JK flip-flop for defending against energy attacks, including a first complementary signal generating circuit, a second complementary signal generating circuit, a flip-flop prototype circuit, and a first master-slave latch unit , the second master-slave latch unit, the third master-slave latch unit and the fourth master-slave latch unit, the first signal output end of the flip-flop prototype circuit is connected to the first master-slave latch unit The first signal input terminal is connected, the second signal output terminal of the flip-flop prototype circuit is connected with the second signal input terminal of the first master-slave latch unit, and the first master-slave latch The first signal output terminal of the unit is connected with the first signal input terminal of the first complementary signal generating circuit, and the second signal output terminal of the first master-slave latch unit is connected with the first complementary signal The second signal input end of the generating circuit is connected, the first signal output end of the first complementary signal generating circuit is connected with the first signal input end of the third master-slave latch unit, and the first The second signal output end of a complementary signal generating circuit is connected with the second signal input end of the third master-slave latch unit, and the first signal output end of the third master-slave latch unit is connected with the The first signal input end of the flip-flop prototype circuit is connected, the second signal output end of the third master-slave latch unit is connected with the second signal input end of the flip-flop prototype circuit, and the The first signal output end of the flip-flop prototype circuit is connected with the second signal input end of the second master-slave latch unit, and the second signal output end of the flip-flop prototype circuit is connected with the second master-slave latch unit. The first signal input end of the slave latch unit is connected, the first signal output end of the second master-slave latch unit is connected with the first signal input end of the second complementary signal generating circuit, the The second signal output end of the second master-slave latch unit is connected to the second signal input end of the second complementary signal generation circuit, and the first signal output end of the second complementary signal generation circuit is connected to the second signal output end of the second complementary signal generation circuit. The first signal input end of the fourth master-slave latch unit described above is connected, the second signal output end of the second complementary signal generating circuit is connected with the second signal input end of the fourth master-slave latch unit connected, the first signal output end of the fourth master-slave latch unit is connected with the third signal input end of the flip-flop prototype circuit, the second signal of the fourth master-slave latch unit The output end is connected with the fourth signal input end of the flip-flop prototype circuit.

The first complementary signal generating circuit is composed of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, The ninth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor, the drain of the first PMOS transistor is connected to the positive terminal of the power supply, and the first PMOS transistor The source, the drain of the second PMOS transistor and the drain of the third PMOS transistor are connected, and the gate of the second PMOS transistor is connected to the first complementary signal generating circuit connected to the third signal input end of the third PMOS transistor, the gate of the third PMOS transistor is connected to the fourth signal input end of the first complementary signal generating circuit, the source electrode of the second PMOS transistor, the The drain of the fourth PMOS transistor and the drain of the sixth PMOS transistor are connected, the source of the third PMOS transistor, the drain of the fifth PMOS transistor and the The drains of the seventh PMOS transistor are connected to each other, and the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor are connected to the first signal input terminal of the first complementary signal generating circuit. connected, the source of the fourth PMOS transistor, the source of the sixth PMOS transistor, the source of the seventh PMOS transistor and the drain of the eighth PMOS transistor are connected , the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor are connected to the second signal input end of the first complementary signal generating circuit, and the fifth PMOS transistor The source is connected to the drain of the ninth PMOS transistor, the source of the eighth PMOS transistor, the drain of the first NMOS transistor, the drain of the second NMOS transistor, the The grid of the ninth PMOS transistor and the grid of the third NMOS transistor are connected to the first signal output end of the first complementary signal generating circuit, and the grid of the eighth PMOS transistor , the gate of the second NMOS transistor, the drain of the third NMOS transistor, the source of the ninth PMOS transistor and the drain of the fourth NMOS transistor are all connected to the drain of the first NMOS transistor The second signal output terminal of a complementary signal generating circuit is connected, the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor and the The sources of the fourth NMOS transistor are all grounded, and the grid of the first PMOS transistor, the grid of the first NMOS transistor and the grid of the fourth NMOS transistor are all connected to the clock signal input terminal .

The second complementary signal generation circuit consists of tenth PMOS transistors, eleventh PMOS transistors, twelfth PMOS transistors, thirteenth PMOS transistors, fourteenth PMOS transistors, fifteenth PMOS transistors, sixteenth PMOS transistors , the seventeenth PMOS transistor, the eighteenth PMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor, the drain of the tenth PMOS transistor is connected to the positive terminal of the power supply , the source of the tenth PMOS transistor, the drain of the eleventh PMOS transistor and the drain of the twelfth PMOS transistor are connected, and the gate of the eleventh PMOS transistor pole is connected with the third signal input end of the second complementary signal generating circuit, the gate of the twelfth PMOS transistor is connected with the fourth signal input end of the second complementary signal generating circuit, The source of the eleventh PMOS transistor, the drain of the thirteenth PMOS transistor and the drain of the fifteenth PMOS transistor are connected, and the source of the twelfth PMOS transistor pole, the drain of the fourteenth PMOS transistor and the drain of the sixteenth PMOS transistor are connected, the gate of the thirteenth PMOS transistor, the fourteenth PMOS transistor The gates of the gates are all connected to the first signal input end of the second complementary signal generating circuit, the source of the thirteenth PMOS transistor, the source of the fifteenth PMOS transistor, the The source electrode of the sixteenth PMOS transistor is connected to the drain electrode of the seventeenth PMOS transistor, and the gate electrode of the fifteenth PMOS transistor and the gate electrode of the sixteenth PMOS transistor are connected to each other. The second signal input end of the second complementary signal generating circuit is connected, the source of the fourteenth PMOS transistor is connected with the drain of the eighteenth PMOS transistor, and the seventeenth PMOS transistor is connected to the drain of the eighteenth PMOS transistor. The source of the PMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the gate of the eighteenth PMOS transistor, and the gate of the seventh NMOS transistor are all connected to the first signal output end of the second complementary signal generating circuit, the gate of the seventeenth PMOS transistor, the gate of the sixth NMOS transistor, the seventh NMOS transistor The drain, the source of the eighteenth PMOS transistor and the drain of the eighth NMOS transistor are all connected to the second signal output end of the second complementary signal generating circuit, and the first The source of the fifth NMOS transistor, the source of the sixth NMOS transistor, the source of the seventh NMOS transistor and the source of the eighth NMOS transistor are all grounded, and the source of the tenth PMOS transistor The gate, the gate of the fifth NMOS transistor and the gate of the eighth NMOS transistor are all connected to the clock signal input terminal.

The flip-flop prototype circuit consists of the nineteenth PMOS transistor, the twentieth PMOS transistor, the twenty-first PMOS transistor, the twenty-second PMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, The twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, the sixteenth NMOS transistor and the seventeenth NMOS transistor, the drain of the nineteenth PMOS transistor, the The drain of the twentieth PMOS transistor, the drain of the twenty-first PMOS transistor and the drain of the twenty-second PMOS transistor are all connected to the positive terminal of the power supply. The gate of the PMOS transistor, the gate of the ninth NMOS transistor, the source of the twenty-first PMOS transistor, the drain of the tenth NMOS transistor, and the twenty-second PMOS transistor The sources of all are connected to the first signal output end of the flip-flop prototype circuit, the source of the nineteenth PMOS transistor, the source of the twentieth PMOS transistor, the ninth The drain of the NMOS transistor, the grid of the twenty-first PMOS transistor and the grid of the tenth NMOS transistor are all connected to the second signal output end of the flip-flop prototype circuit, and the The source of the ninth NMOS transistor, the drain of the thirteenth NMOS transistor, the drain of the eleventh NMOS transistor, and the drain of the fourteenth NMOS transistor are connected, and the The source of the tenth NMOS transistor is connected to the drain of the twelfth NMOS transistor, and the gate of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor are connected to the drain of the twelfth NMOS transistor. The first signal input terminal of the flip-flop prototype circuit is connected, and the grid of the thirteenth NMOS transistor and the grid of the fourteenth NMOS transistor are connected with the second signal of the flip-flop prototype circuit. The input ends are connected, the source of the eleventh NMOS transistor, the source of the thirteenth NMOS transistor and the drain of the fifteenth NMOS transistor are connected, and the tenth NMOS transistor is connected to each other. The sources of the two NMOS transistors, the source of the fourteenth NMOS transistor and the drain of the sixteenth NMOS transistor are connected, the source of the fifteenth NMOS transistor, the The source of the sixteenth NMOS transistor and the drain of the seventeenth NMOS transistor are connected, and the gate of the sixteenth NMOS transistor is connected to the third signal input terminal of the flip-flop prototype circuit connected, the gate of the fifteenth NMOS transistor is connected to the fourth signal input terminal of the flip-flop prototype circuit, the source of the seventeenth NMOS transistor is grounded, and the seventeenth NMOS transistor is grounded. The gate of the NMOS transistor, the gate of the nineteenth PMOS transistor and the gate of the twenty-second PMOS transistor are all connected to the clock signal input end.

The internal structure of the first master-slave latch unit is the same as that of the second master-slave latch unit, and the first master-slave latch unit is composed of the first master latch circuit and the first slave latch circuit The first main latch circuit is composed of twenty-third PMOS transistors, twenty-fourth PMOS transistors, twenty-fifth PMOS transistors, twenty-sixth PMOS transistors, eighteenth NMOS transistors, and nineteenth NMOS transistors. tube, the twentieth NMOS tube, the twenty-first NMOS tube and the twenty-second NMOS tube, the drain of the twenty-third PMOS tube, the drain of the twenty-fourth PMOS tube, the The drain of the twenty-fifth PMOS transistor and the drain of the twenty-sixth PMOS transistor are connected to the positive terminal of the power supply, the grid of the twenty-fourth PMOS transistor, the tenth PMOS transistor The gate of the eighth NMOS transistor, the source of the twenty-fifth PMOS transistor, the drain of the nineteenth NMOS transistor and the source of the twenty-sixth PMOS transistor are all connected to the source of the twenty-sixth PMOS transistor. The first signal output end of a master latch circuit is connected, the source of the twenty-third PMOS transistor, the source of the twenty-fourth PMOS transistor, and the drain of the eighteenth NMOS transistor pole, the gate of the twenty-fifth PMOS transistor and the gate of the nineteenth NMOS transistor are all connected to the second signal output end of the first master latch circuit, and the first The source of the eighteenth NMOS transistor is connected to the drain of the twenty NMOS transistor, and the gate of the twenty NMOS transistor is connected to the first signal input terminal of the first master-slave latch unit The source of the nineteenth NMOS transistor is connected to the drain of the twenty-first NMOS transistor, and the gate of the twenty-first NMOS transistor is connected to the first master-slave The second signal input end of the latch unit is connected, the source of the twentieth NMOS transistor, the source of the twenty-first NMOS transistor and the drain of the twenty-second NMOS transistor three The source of the twenty-second NMOS transistor is grounded, the gate of the twenty-second NMOS transistor, the gate of the twenty-third PMOS transistor and the twenty-third The gates of the six PMOS transistors are all connected to the clock signal input terminal, and the first slave latch circuit is composed of the twenty-seventh PMOS transistor, the twenty-eighth PMOS transistor, the twenty-ninth PMOS transistor, and the thirty PMOS transistor. tube, the thirty-first PMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube and the twenty-sixth NMOS tube, the drain of the twenty-seventh PMOS tube connected to the positive terminal of the power supply, the source of the twenty-seventh PMOS transistor, the drain of the twenty-eighth PMOS transistor and the drain of the twenty-ninth PMOS transistor are connected, The gate of the twenty-eighth PMOS transistor is connected to the first signal input end of the first slave latch circuit, and the gate of the twenty-ninth PMOS transistor is connected to the first slave latch circuit. The second signal input terminal of the storage circuit is connected, the source of the twenty-eighth PMOS transistor is connected with the drain of the thirty-first PMOS transistor, and the The source of the twenty-ninth PMOS transistor is connected to the drain of the thirty-first PMOS transistor, the gate of the thirty-first PMOS transistor, the gate of the twenty-fourth NMOS transistor, The source of the thirty-first PMOS transistor, the drain of the twenty-fifth NMOS transistor and the drain of the twenty-sixth NMOS transistor are all connected to the first master-slave latch unit connected to the first signal output end of the 30th PMOS transistor, the drain of the 23rd NMOS transistor, the drain of the 24th NMOS transistor, the The gate of the thirty-first PMOS transistor and the gate of the twenty-fifth NMOS transistor are all connected to the second signal output end of the first master-slave latch unit, and the twenty-third The source of the NMOS transistor, the source of the twenty-fourth NMOS transistor, the source of the twenty-fifth NMOS transistor, and the source of the twenty-sixth NMOS transistor are all grounded, and the The gate of the twenty-third NMOS transistor, the gate of the twenty-sixth NMOS transistor and the gate of the twenty-seventh PMOS transistor are all connected to the clock signal input end, and the first main The first signal output end of the latch circuit is connected to the first signal input end of the first slave latch circuit, and the second signal output end of the first master latch circuit is connected to the first slave latch circuit. The second signal input terminals of the latch circuit are connected.

The third master-slave latch unit is identical to the internal structure of the fourth master-slave latch unit, and the third master-slave latch unit is composed of a second master latch circuit and a second slave latch circuit Composed of, the second main latch circuit is composed of the thirty-second PMOS tube, the thirty-third PMOS tube, the thirty-fourth PMOS tube, the thirty-fifth PMOS tube, the thirty-sixth PMOS tube, the twenty-first The seven NMOS transistors, the twenty-eighth NMOS transistors, the twenty-ninth NMOS transistors and the thirty NMOS transistors are composed of the thirty-second PMOS transistors whose drains are connected to the positive terminal of the power supply, and the thirty-second PMOS transistors The source electrode of the two PMOS transistors, the drain electrode of the thirty-third PMOS transistor and the drain electrode of the thirty-fourth PMOS transistor are connected, and the grid of the thirty-third PMOS transistor is connected to the drain electrode of the thirty-third PMOS transistor. The first signal input end of the third master-slave latch unit is connected, the gate of the thirty-fourth PMOS transistor is connected with the second signal input end of the third master-slave latch unit, and The source of the thirty-third PMOS transistor is connected to the drain of the thirty-fifth PMOS transistor, and the source of the thirty-fourth PMOS transistor is connected to the thirty-sixth PMOS transistor. The drains are connected, the gate of the thirty-fifth PMOS transistor, the gate of the twenty-eighth NMOS transistor, the source of the thirty-sixth PMOS transistor, the twenty-eighth PMOS transistor The drains of the nine NMOS transistors and the drains of the 30th NMOS transistors are all connected to the first signal output end of the second master latch circuit, and the source electrodes of the 35th PMOS transistors , the drain of the twenty-seventh NMOS transistor, the drain of the twenty-eighth NMOS transistor, the gate of the thirty-sixth PMOS transistor, and the gate of the twenty-ninth NMOS transistor The gates are all connected to the second signal output end of the second main latch circuit, the source of the twenty-seventh NMOS transistor, the source of the twenty-eighth NMOS transistor, the The source of the twenty-ninth NMOS transistor and the source of the thirtieth NMOS transistor are grounded, the gate of the twenty-seventh NMOS transistor, the gate of the thirtieth NMOS transistor and The gates of the thirty-second PMOS transistors are all connected to the clock signal input end, and the second slave latch circuit is composed of the thirty-seventh PMOS transistor, the thirty-eighth PMOS transistor, the thirty-ninth PMOS transistor tube, the fortieth PMOS tube, the thirty-first NMOS tube, the thirty-second NMOS tube, the thirty-third NMOS tube, the thirty-fourth NMOS tube and the thirty-fifth NMOS tube, the thirty-fifth The drain of the seventh PMOS transistor, the drain of the thirty-eighth PMOS transistor, the drain of the thirty-ninth PMOS transistor and the drain of the fortieth PMOS transistor are all in phase with the positive terminal of the power supply connection, the gate of the thirty-eighth PMOS transistor, the gate of the thirty-first NMOS transistor, the source of the thirty-ninth PMOS transistor, the thirty-second NMOS transistor The drain and the source of the fortieth PMOS transistor are connected to the first signal output end of the third master-slave latch unit, and the thirty-seventh The source of the PMOS transistor, the source of the thirty-eighth PMOS transistor, the drain of the thirty-first NMOS transistor, the gate of the thirty-ninth PMOS transistor, and the third The gates of the twelve NMOS transistors are all connected to the second signal output end of the third master-slave latch unit, and the source of the thirty-first NMOS transistor is connected to the thirty-third NMOS transistor. The drain of the thirty-third NMOS transistor is connected to the first signal input terminal of the second slave latch circuit, and the source of the thirty-second NMOS transistor is connected to the The drain of the thirty-fourth NMOS transistor is connected, the gate of the thirty-fourth NMOS transistor is connected to the second signal input end of the second slave latch circuit, and the first The source of the thirty-third NMOS transistor, the source of the thirty-fourth NMOS transistor and the drain of the thirty-fifth NMOS transistor are connected, and the source of the thirty-fifth NMOS transistor The gate of the thirty-fifth NMOS transistor, the gate of the thirty-seventh PMOS transistor and the gate of the fortieth PMOS transistor are all connected to the clock signal input end, and The first signal output end of the second master latch circuit is connected to the first signal input end of the second slave latch circuit, and the second signal output end of the second master latch circuit is connected to the second slave latch circuit. The second signal input terminal of the second slave latch circuit is connected.

Compared with the prior art, the advantage of the present invention is that in the design of the JK flip-flop, the sensitive amplification logic with the characteristics of energy consumption symmetry is applied, and combined with the influence of the channel width to length ratio on the data transmission rate, the traditional JK flip-flop On the basis of the device structure, a JK flip-flop that defends against energy attacks is proposed; under the HSPICE environment, computer simulation is carried out using PTM90nm CMOS process device parameters. The experimental results prove that the logic function of the flip-flop is correct, and the energy consumption is stable. The processed data are independent of each other and have good performance in defending against energy attacks.

Description of drawings

Fig. 1 is the circuit principle diagram of JK flip-flop of the present invention;

Fig. 2 is the circuit principle diagram and the symbol representation diagram of the first master-slave latch unit in the JK flip-flop of the present invention;

Fig. 3 is the circuit principle diagram and the symbol representation diagram of the third master-slave latch unit in the JK flip-flop of the present invention;

Fig. 4 is the analog waveform of the JK flip-flop of the present invention;

Fig. 5 is the energy consumption curve of the JK flip-flop of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

与第一主从锁存单元4的第二信号输入端相连接，第一主从锁存单元4的第一信号输出端与第一互补信号产生电路1的第一信号输入端相连接，第一主从锁存单元4的第二信号输出端与第一互补信号产生电路1的第二信号输入端相连接，第一互补信号产生电路1的第一信号输出端

与第三主从锁存单元6的第一信号输入端相连接，第一互补信号产生电路1的第二信号输出端x与第三主从锁存单元6的第二信号输入端相连接，第三主从锁存单元6的第一信号输出端与触发器原型电路2的第一信号输入端相连接，第三主从锁存单元6的第二信号输出端与触发器原型电路2的第二信号输入端相连接，触发器原型电路2的第一信号输出端Q与第二主从锁存单元5的第二信号输入端相连接，触发器原型电路2的第二信号输出端

与第二主从锁存单元5的第一信号输入端相连接，第二主从锁存单元5的第一信号输出端与第二互补信号产生电路3的第一信号输入端相连接，第二主从锁存单元5的第二信号输出端与第二互补信号产生电路3的第二信号输入端相连接，第二互补信号产生电路3的第一信号输出端

与第四主从锁存单元7的第一信号输入端相连接，第二互补信号产生电路3的第二信号输出端y与第四主从锁存单元7的第二信号输入端相连接，第四主从锁存单元7的第一信号输出端与触发器原型电路2的第三信号输入端相连接，第四主从锁存单元7的第二信号输出端与触发器原型电路2的第四信号输入端相连接。As shown in Figure 1, a JK flip-flop that defends against energy attacks includes a first complementary signal generating circuit 1, a second complementary signal generating circuit 3, a flip-flop prototype circuit 2, a first master-slave latch unit 4, a second The master-slave latch unit 5, the third master-slave latch unit 6 and the fourth master-slave latch unit 7, the first signal output terminal Q of the flip-flop prototype circuit 2 and the first signal of the first master-slave latch unit 4 The input terminals are connected, and the second signal output terminal of the flip-flop prototype circuit 2

Be connected with the second signal input end of the first master-slave latch unit 4, the first signal output end of the first master-slave latch unit 4 is connected with the first signal input end of the first complementary signal generation circuit 1, the second The second signal output end of a master-slave latch unit 4 is connected with the second signal input end of the first complementary signal generating circuit 1, and the first signal output end of the first complementary signal generating circuit 1

Be connected with the first signal input terminal of the third master-slave latch unit 6, the second signal output terminal x of the first complementary signal generating circuit 1 is connected with the second signal input terminal of the third master-slave latch unit 6, The first signal output end of the third master-slave latch unit 6 is connected with the first signal input end of the flip-flop prototype circuit 2, and the second signal output end of the third master-slave latch unit 6 is connected with the flip-flop prototype circuit 2. The second signal input end is connected, the first signal output end Q of the flip-flop prototype circuit 2 is connected with the second signal input end of the second master-slave latch unit 5, the second signal output end of the flip-flop prototype circuit 2

Be connected with the first signal input end of the second master-slave latch unit 5, the first signal output end of the second master-slave latch unit 5 is connected with the first signal input end of the second complementary signal generation circuit 3, the second The second signal output end of the two master-slave latch units 5 is connected with the second signal input end of the second complementary signal generating circuit 3, and the first signal output end of the second complementary signal generating circuit 3

Be connected with the first signal input terminal of the fourth master-slave latch unit 7, the second signal output terminal y of the second complementary signal generating circuit 3 is connected with the second signal input terminal of the fourth master-slave latch unit 7, The first signal output end of the fourth master-slave latch unit 7 is connected with the third signal input end of the flip-flop prototype circuit 2, and the second signal output end of the fourth master-slave latch unit 7 is connected with the flip-flop prototype circuit 2. The fourth signal input terminals are connected.

相连接，第二PMOS管P2的源极、第四PMOS管P4的漏极及第六PMOS管P6的漏极三者相连接，第三PMOS管P3的源极、第五PMOS管P5的漏极及第七PMOS管P7的漏极三者相连接，第四PMOS管P4的栅极、第五PMOS管P5的栅极均与第一互补信号产生电路1的第一信号输入端相连接，第四PMOS管P4的源极、第六PMOS管P6的源极、第七PMOS管P7的源极及第八PMOS管P8的漏极四者相连接，第六PMOS管P6的栅极、第七PMOS管P7的栅极均与第一互补信号产生电路1的第二信号输入端相连接，第五PMOS管P5的源极与第九PMOS管P9的漏极相连接，第八PMOS管P8的源极、第一NMOS管N1的漏极、第二NMOS管N2的漏极、第九PMOS管P9的栅极及第三NMOS管N3的栅极均与第一互补信号产生电路1的第一信号输出端

相连接，第八PMOS管P8的栅极、第二NMOS管N2的栅极、第三NMOS管N3的漏极、第九PMOS管P9的源极及第四NMOS管N4的漏极均与第一互补信号产生电路1的第二信号输出端x相连接，第一NMOS管N1的源极、第二NMOS管N2的源极、第三NMOS管N3的源极及第四NMOS管N4的源极均接地，第一PMOS管P1的栅极、第一NMOS管N1的栅极及第四NMOS管N4的栅极均与时钟信号输入端clk相连接。The first complementary signal generating circuit 1 is composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, The eighth PMOS transistor P8, the ninth PMOS transistor P9, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3 and the fourth NMOS transistor N4, the drain of the first PMOS transistor P1 is connected to the positive power supply terminal VDD The source of the first PMOS transistor P1, the drain of the second PMOS transistor P2 and the drain of the third PMOS transistor P3 are connected, and the gate of the second PMOS transistor P2 is connected to the first complementary signal generating circuit 1 The third signal input terminal J of the third PMOS transistor P3 is connected to the fourth signal input terminal of the first complementary signal generation circuit 1

The source of the second PMOS transistor P2, the drain of the fourth PMOS transistor P4 and the drain of the sixth PMOS transistor P6 are connected, the source of the third PMOS transistor P3, the drain of the fifth PMOS transistor P5 pole and the drain of the seventh PMOS transistor P7 are connected, the grid of the fourth PMOS transistor P4 and the grid of the fifth PMOS transistor P5 are connected with the first signal input terminal of the first complementary signal generating circuit 1, The source of the fourth PMOS transistor P4, the source of the sixth PMOS transistor P6, the source of the seventh PMOS transistor P7, and the drain of the eighth PMOS transistor P8 are connected, and the gate of the sixth PMOS transistor P6 and the drain of the sixth PMOS transistor P6 are connected to each other. The gates of the seven PMOS transistors P7 are all connected to the second signal input terminal of the first complementary signal generating circuit 1, the source of the fifth PMOS transistor P5 is connected to the drain of the ninth PMOS transistor P9, and the eighth PMOS transistor P8 The source of the first NMOS transistor N1, the drain of the second NMOS transistor N2, the gate of the ninth PMOS transistor P9 and the gate of the third NMOS transistor N3 are all connected to the first complementary signal generating circuit 1 a signal output

connected, the gate of the eighth PMOS transistor P8, the gate of the second NMOS transistor N2, the drain of the third NMOS transistor N3, the source of the ninth PMOS transistor P9 and the drain of the fourth NMOS transistor N4 are all connected to the drain of the fourth NMOS transistor N4 The second signal output terminal x of a complementary signal generating circuit 1 is connected, the source of the first NMOS transistor N1, the source of the second NMOS transistor N2, the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 Both poles are grounded, and the gates of the first PMOS transistor P1, the first NMOS transistor N1 and the fourth NMOS transistor N4 are all connected to the clock signal input terminal clk.

相连接，第十二PMOS管P12的栅极与第二互补信号产生电路3的第四信号输入端K相连接，第十一PMOS管P11的源极、第十三PMOS管P13的漏极及第十五PMOS管P15的漏极三者相连接，第十二PMOS管P12的源极、第十四PMOS管P14的漏极及第十六PMOS管P16的漏极三者相连接，第十三PMOS管P13的栅极、第十四PMOS管P14的栅极均与第二互补信号产生电路3的第一信号输入端相连接，第十三PMOS管P13的源极、第十五PMOS管P15的源极、第十六PMOS管P16的源极及第十七PMOS管P17的漏极四者相连接，第十五PMOS管P15的栅极、第十六PMOS管P16的栅极均与第二互补信号产生电路3的第二信号输入端相连接，第十四PMOS管P14的源极与第十八PMOS管P18的漏极相连接，第十七PMOS管P17的源极、第五NMOS管N5的漏极、第六NMOS管N6的漏极、第十八PMOS管P18的栅极及第七NMOS管N7的栅极均与第二互补信号产生电路3的第一信号输出端

相连接，第十七PMOS管P17的栅极、第六NMOS管N6的栅极、第七NMOS管N7的漏极、第十八PMOS管P18的源极及第八NMOS管N8的漏极均与第二互补信号产生电路3的第二信号输出端y相连接，第五NMOS管N5的源极、第六NMOS管N6的源极、第七NMOS管N7的源极及第八NMOS管N8的源极均接地，第十PMOS管P10的栅极、第五NMOS管N5的栅极及第八NMOS管N8的栅极均与时钟信号输入端clk相连接。The second complementary signal generating circuit 3 is composed of the tenth PMOS transistor P10, the eleventh PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the fifteenth PMOS transistor P15, the The sixteenth PMOS transistor P16, the seventeenth PMOS transistor P17, the eighteenth PMOS transistor P18, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7 and the eighth NMOS transistor N8, the tenth PMOS transistor P10 The drain of the power supply is connected to the positive power supply terminal VDD, the source of the tenth PMOS transistor P10, the drain of the eleventh PMOS transistor P11 and the drain of the twelfth PMOS transistor P12 are connected, and the eleventh PMOS transistor P11 The gate and the third signal input terminal of the second complementary signal generating circuit 3

The gate of the twelfth PMOS transistor P12 is connected with the fourth signal input terminal K of the second complementary signal generating circuit 3, the source of the eleventh PMOS transistor P11, the drain of the thirteenth PMOS transistor P13 and The drains of the fifteenth PMOS transistor P15 are connected, the source of the twelfth PMOS transistor P12, the drain of the fourteenth PMOS transistor P14 and the drain of the sixteenth PMOS transistor P16 are connected, and the drains of the tenth PMOS transistor P16 are connected. The gates of the third PMOS transistor P13 and the gate of the fourteenth PMOS transistor P14 are all connected to the first signal input terminal of the second complementary signal generating circuit 3, the source of the thirteenth PMOS transistor P13, the fifteenth PMOS transistor The source of P15, the source of the sixteenth PMOS transistor P16, and the drain of the seventeenth PMOS transistor P17 are connected to each other, and the gate of the fifteenth PMOS transistor P15 and the gate of the sixteenth PMOS transistor P16 are connected to each other. The second signal input terminal of the second complementary signal generating circuit 3 is connected, the source of the fourteenth PMOS transistor P14 is connected with the drain of the eighteenth PMOS transistor P18, the source of the seventeenth PMOS transistor P17, the fifth The drain of the NMOS transistor N5, the drain of the sixth NMOS transistor N6, the gate of the eighteenth PMOS transistor P18, and the gate of the seventh NMOS transistor N7 are all connected to the first signal output terminal of the second complementary signal generating circuit 3

The gate of the seventeenth PMOS transistor P17, the gate of the sixth NMOS transistor N6, the drain of the seventh NMOS transistor N7, the source of the eighteenth PMOS transistor P18, and the drain of the eighth NMOS transistor N8 are all Connected to the second signal output terminal y of the second complementary signal generating circuit 3, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6, the source of the seventh NMOS transistor N7 and the eighth NMOS transistor N8 The sources of the transistors are all grounded, and the gates of the tenth PMOS transistor P10, the fifth NMOS transistor N5, and the eighth NMOS transistor N8 are all connected to the clock signal input terminal clk.

The flip-flop prototype circuit 2 consists of the nineteenth PMOS transistor P19, the twentieth PMOS transistor P20, the twenty-first PMOS transistor P21, the twenty-second PMOS transistor P22, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the tenth One NMOS tube N11, the twelfth NMOS tube N12, the thirteenth NMOS tube N13, the fourteenth NMOS tube N14, the fifteenth NMOS tube N15, the sixteenth NMOS tube N16 and the seventeenth NMOS tube N17, the tenth The drain of the ninth PMOS transistor P19, the drain of the twentieth PMOS transistor P20, the drain of the twenty-first PMOS transistor P21 and the drain of the twenty-second PMOS transistor P22 are all connected to the positive power supply terminal VDD, and the second The gate of the tenth PMOS transistor P20, the gate of the ninth NMOS transistor N9, the source of the twenty-first PMOS transistor P21, the drain of the tenth NMOS transistor N10, and the source of the twenty-second PMOS transistor P22 are all connected to the trigger The first signal output terminal Q of the device prototype circuit 2 is connected, the source of the nineteenth PMOS transistor P19, the source of the twentieth PMOS transistor P20, the drain of the ninth NMOS transistor N9, the twenty-first PMOS transistor P21 The gate of the gate and the gate of the tenth NMOS transistor N10 are connected with the second signal output end of the flip-flop prototype circuit 2 The source of the ninth NMOS transistor N9, the drain of the thirteenth NMOS transistor N13, the drain of the eleventh NMOS transistor N11 and the drain of the fourteenth NMOS transistor N14 are connected, and the tenth NMOS transistor The source of N10 is connected to the drain of the twelfth NMOS transistor N12, and the gate of the eleventh NMOS transistor N11 and the gate of the twelfth NMOS transistor N12 are connected to the first signal input terminal of the flip-flop prototype circuit 2. connection, the gate of the thirteenth NMOS transistor N13 and the gate of the fourteenth NMOS transistor N14 are connected to the second signal input terminal of the flip-flop prototype circuit 2, the source of the eleventh NMOS transistor N11, the gate of the thirteenth NMOS transistor N14 The source of the NMOS transistor N13 and the drain of the fifteenth NMOS transistor N15 are connected, the source of the twelfth NMOS transistor N12, the source of the fourteenth NMOS transistor N14 and the drain of the sixteenth NMOS transistor N16 The three are connected, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16 and the drain of the seventeenth NMOS transistor N17 are connected, the gate of the sixteenth NMOS transistor N16 is connected to the trigger The third signal input end of flip-flop prototype circuit 2 is connected, the gate of the fifteenth NMOS transistor N15 is connected with the fourth signal input end of flip-flop prototype circuit 2, the source of the seventeenth NMOS transistor N17 is grounded, and the gate of the tenth NMOS transistor N17 is grounded. The gate of the seventh NMOS transistor N17, the gate of the nineteenth PMOS transistor P19 and the gate of the twenty-second PMOS transistor P22 are all connected to the clock signal input terminal clk.

相连接，第十八NMOS管N18的源极与第二十NMOS管N20的漏极相连接，第二十NMOS管N20的栅极与第一主从锁存单元4的第一信号输入端

相连接，第十九NMOS管N19的源极与第二十一NMOS管N21的漏极相连接，第二十一NMOS管N21的栅极与第一主从锁存单元4的第二信号输入端Qⁿ相连接，第二十NMOS管N20的源极、第二十一NMOS管N21的源极及第二十二NMOS管N22的漏极三者相连接，第二十二NMOS管N22的源极接地，第二十二NMOS管N22的栅极、第二十三PMOS管P23的栅极及第二十六PMOS管P26的栅极均与时钟信号输入端clk相连接，第一从锁存电路9由第二十七PMOS管P27、第二十八PMOS管P28、第二十九PMOS管P29、第三十PMOS管P30、第三十一PMOS管P31、第二十三NMOS管N23、第二十四NMOS管N24、第二十五NMOS管N25及第二十六NMOS管N26组成，第二十七PMOS管P27的漏极与电源正端VDD相连接，第二十七PMOS管P27的源极、第二十八PMOS管P28的漏极及第二十九PMOS管P29的漏极三者相连接，第二十八PMOS管P28的栅极与第一从锁存电路9的第一信号输入端in1连接，第二十九PMOS管P29的栅极与第一从锁存电路9的第二信号输入端

连接，第二十八PMOS管P28的源极与第三十PMOS管P30的漏极相连接，第二十九PMOS管P29的源极与第三十一PMOS管P31的漏极相连接，第三十PMOS管P30的栅极、第二十四NMOS管N24的栅极、第三十一PMOS管P31的源极、第二十五NMOS管N25的漏极及第二十六NMOS管N26的漏极均与第一主从锁存单元4的第一信号输出端

相连接，第三十PMOS管P30的源极、第二十三NMOS管N23的漏极、第二十四NMOS管N24的漏极、第三十一PMOS管P31的栅极及第二十五NMOS管N25的栅极均与第一主从锁存单元4的第二信号输出端out2相连接，第二十三NMOS管N23的源极、第二十四NMOS管N24的源极、第二十五NMOS管N25的源极及第二十六NMOS管N26的源极均接地，第二十三NMOS管N23的栅极、第二十六NMOS管N26的栅极及第二十七PMOS管P27的栅极均与时钟信号输入端clk相连接，第一主锁存电路8的第一信号输出端out1与第一从锁存电路9的第一信号输入端in1相连接，第一主锁存电路8的第二信号输出端

与第一从锁存电路9的第二信号输入端

相连接。The first master-slave latch unit 4 is identical to the internal structure of the second master-slave latch unit 5, as shown in Figure 2, the first master-slave latch unit 4 is latched by the first master latch circuit 8 and the first slave latch The circuit 9 is composed of the first main latch circuit 8 consisting of the twenty-third PMOS transistor P23, the twenty-fourth PMOS transistor P24, the twenty-fifth PMOS transistor P25, the twenty-sixth PMOS transistor P26, and the eighteenth NMOS transistor N18 , the nineteenth NMOS transistor N19, the twentieth NMOS transistor N20, the twenty-first NMOS transistor N21 and the twenty-second NMOS transistor N22, the drain of the twenty-third PMOS transistor P23, the twenty-fourth PMOS transistor P24 The drain of the twenty-fifth PMOS transistor P25 and the drain of the twenty-sixth PMOS transistor P26 are all connected to the positive power supply terminal VDD, the gate of the twenty-fourth PMOS transistor P24, the gate of the eighteenth NMOS transistor The gate of N18, the source of the twenty-fifth PMOS transistor P25, the drain of the nineteenth NMOS transistor N19, and the source of the twenty-sixth PMOS transistor P26 are all connected to the first signal output of the first main latch circuit 8 terminal out1, the source of the twenty-third PMOS transistor P23, the source of the twenty-fourth PMOS transistor P24, the drain of the eighteenth NMOS transistor N18, the gate of the twenty-fifth PMOS transistor P25 and the tenth The gates of the nine NMOS transistors N19 are all connected to the second signal output end of the first main latch circuit 8

The source of the eighteenth NMOS transistor N18 is connected to the drain of the twentieth NMOS transistor N20, and the gate of the twentieth NMOS transistor N20 is connected to the first signal input terminal of the first master-slave latch unit 4

The source of the nineteenth NMOS transistor N19 is connected to the drain of the twenty-first NMOS transistor N21, and the gate of the twenty-first NMOS transistor N21 is connected to the second signal input of the first master-slave latch unit 4 Terminal Q ⁿ is connected, the source of the twentieth NMOS transistor N20, the source of the twenty-first NMOS transistor N21 and the drain of the twenty-second NMOS transistor N22 are connected, and the source of the twenty-second NMOS transistor N22 The source is grounded, the gate of the twenty-second NMOS transistor N22, the gate of the twenty-third PMOS transistor P23, and the gate of the twenty-sixth PMOS transistor P26 are all connected to the clock signal input terminal clk, and the first slave lock The storage circuit 9 is composed of the twenty-seventh PMOS transistor P27, the twenty-eighth PMOS transistor P28, the twenty-ninth PMOS transistor P29, the thirty-first PMOS transistor P30, the thirty-first PMOS transistor P31, and the twenty-third NMOS transistor N23 , the twenty-fourth NMOS transistor N24, the twenty-fifth NMOS transistor N25 and the twenty-sixth NMOS transistor N26, the drain of the twenty-seventh PMOS transistor P27 is connected to the positive power supply terminal VDD, the twenty-seventh PMOS transistor The source electrode of P27, the drain electrode of the twenty-eighth PMOS transistor P28 and the drain electrode of the twenty-ninth PMOS transistor P29 are connected, and the gate of the twenty-eighth PMOS transistor P28 is connected to the gate of the first slave latch circuit 9 The first signal input terminal in1 is connected, and the gate of the twenty-ninth PMOS transistor P29 is connected to the second signal input terminal of the first slave latch circuit 9

connection, the source of the twenty-eighth PMOS transistor P28 is connected to the drain of the thirtieth PMOS transistor P30, the source of the twenty-ninth PMOS transistor P29 is connected to the drain of the thirty-first PMOS transistor P31, and the drain of the thirty-first PMOS transistor P31 is connected. The gate of the thirty-first PMOS transistor P30, the gate of the twenty-fourth NMOS transistor N24, the source of the thirty-first PMOS transistor P31, the drain of the twenty-fifth NMOS transistor N25, and the gate of the twenty-sixth NMOS transistor N26 The drains are connected to the first signal output end of the first master-slave latch unit 4

The source of the thirtieth PMOS transistor P30, the drain of the twenty-third NMOS transistor N23, the drain of the twenty-fourth NMOS transistor N24, the gate of the thirty-first PMOS transistor P31 and the twenty-fifth The gates of the NMOS transistor N25 are all connected to the second signal output terminal out2 of the first master-slave latch unit 4, the source of the twenty-third NMOS transistor N23, the source of the twenty-fourth NMOS transistor N24, the second The source of the fifteenth NMOS transistor N25 and the source of the twenty-sixth NMOS transistor N26 are grounded, the gate of the twenty-third NMOS transistor N23, the gate of the twenty-sixth NMOS transistor N26 and the twenty-seventh PMOS transistor The gates of P27 are all connected with the clock signal input terminal clk, the first signal output terminal out1 of the first master latch circuit 8 is connected with the first signal input terminal in1 of the first slave latch circuit 9, and the first master latch circuit The second signal output end of storage circuit 8

and the second signal input terminal of the first slave latch circuit 9

connected.

相连接，第二十七NMOS管N27的源极、第二十八NMOS管N28的源极、第二十九NMOS管N29的源极及第三十NMOS管N30的源极均接地，第二十七NMOS管N27的栅极、第三十NMOS管N30的栅极及第三十二PMOS管P32的栅极均与时钟信号输入端clk相连接，第二从锁存电路11由第三十七PMOS管P37、第三十八PMOS管P38、第三十九PMOS管P39、第四十PMOS管P40、第三十一NMOS管N31、第三十二NMOS管N32、第三十三NMOS管N33、第三十四NMOS管N34及第三十五NMOS管N35组成，第三十七PMOS管P37的漏极、第三十八PMOS管P38的漏极、第三十九PMOS管P39的漏极及第四十PMOS管P40的漏极均与电源正端VDD相连接，第三十八PMOS管P38的栅极、第三十一NMOS管N31的栅极、第三十九PMOS管P39的源极、第三十二NMOS管N32的漏极及第四十PMOS管P40的源极均与第三主从锁存单元6的第一信号输出端out4相连接，第三十七PMOS管P37的源极、第三十八PMOS管P38的源极、第三十一NMOS管N31的漏极、第三十九PMOS管P39的栅极及第三十二NMOS管N32的栅极均与第三主从锁存单元6的第二信号输出端相连接，第三十一NMOS管N31的源极与第三十三NMOS管N33的漏极相连接，第三十三NMOS管N33的栅极与第二从锁存电路11的第一信号输入端in2相连接，第三十二NMOS管N32的源极与第三十四NMOS管N34的漏极相连接，第三十四NMOS管N34的栅极与第二从锁存电路11的第二信号输入端

相连接，第三十三NMOS管N33的源极、第三十四NMOS管N34的源极及第三十五NMOS管N35的漏极三者相连接，第三十五NMOS管N35的源极接地，第三十五NMOS管N35的栅极、第三十七PMOS管P37的栅极及第四十PMOS管P40的栅极均与时钟信号输入端clk相连接，第二主锁存电路10的第一信号输出端out3与第二从锁存电路11的第一信号输入端in2相连接，第二主锁存电路10的第二信号输出端与第二从锁存电路11的第二信号输入端

相连接。The 3rd master-slave latch unit 6 is identical with the internal structure of the 4th master-slave latch unit 7, as shown in Figure 3, the 3rd master-slave latch unit 6 is latched by the second master latch circuit 10 and the second slave The circuit 11 is composed of the second main latch circuit 10 by the thirty-second PMOS transistor P32, the thirty-third PMOS transistor P33, the thirty-fourth PMOS transistor P34, the thirty-fifth PMOS transistor P35, and the thirty-sixth PMOS transistor P36, the twenty-seventh NMOS transistor N27, the twenty-eighth NMOS transistor N28, the twenty-ninth NMOS transistor N29 and the thirtieth NMOS transistor N30, the drain of the thirty-second PMOS transistor P32 is in phase with the positive terminal VDD of the power supply connection, the source of the thirty-second PMOS transistor P32, the drain of the thirty-third PMOS transistor P33 and the drain of the thirty-fourth PMOS transistor P34 are connected, and the gate of the thirty-third PMOS transistor P33 is connected to The first signal input end x of the third master-slave latch unit 6 is connected, the gate of the thirty-fourth PMOS transistor P34 is connected with the second signal input end y of the third master-slave latch unit 6, and the thirty-third PMOS The source of the transistor P33 is connected to the drain of the thirty-fifth PMOS transistor P35, the source of the thirty-fourth PMOS transistor P34 is connected to the drain of the thirty-sixth PMOS transistor P36, and the thirty-fifth PMOS transistor P35 The gate of the twenty-eighth NMOS transistor N28, the source of the thirty-sixth PMOS transistor P36, the drain of the twenty-ninth NMOS transistor N29 and the drain of the thirtieth NMOS transistor N30 are all connected to the second The first signal output terminal out3 of the main latch circuit 10 is connected, the source of the thirty-fifth PMOS transistor P35, the drain of the twenty-seventh NMOS transistor N27, the drain of the twenty-eighth NMOS transistor N28, the third The gate of the sixteenth PMOS transistor P36 and the gate of the twenty-ninth NMOS transistor N29 are connected to the second signal output end of the second main latch circuit 10

The source of the twenty-seventh NMOS transistor N27, the source of the twenty-eighth NMOS transistor N28, the source of the twenty-ninth NMOS transistor N29 and the source of the thirtieth NMOS transistor N30 are all grounded, and the source of the second The gate of the seventeenth NMOS transistor N27, the gate of the thirtieth NMOS transistor N30, and the gate of the thirty-second PMOS transistor P32 are all connected to the clock signal input terminal clk, and the second slave latch circuit 11 is controlled by the thirty-second Seventh PMOS transistor P37, thirty-eighth PMOS transistor P38, thirty-ninth PMOS transistor P39, fortieth PMOS transistor P40, thirty-first NMOS transistor N31, thirty-second NMOS transistor N32, thirty-third NMOS transistor N33, the thirty-fourth NMOS transistor N34 and the thirty-fifth NMOS transistor N35 are composed, the drain of the thirty-seventh PMOS transistor P37, the drain of the thirty-eighth PMOS transistor P38, and the drain of the thirty-ninth PMOS transistor P39 and the drain of the fortieth PMOS transistor P40 are connected to the positive power supply terminal VDD, the gate of the thirty-eighth PMOS transistor P38, the gate of the thirty-first NMOS transistor N31, the gate of the thirty-ninth PMOS transistor P39 The source, the drain of the thirty-second NMOS transistor N32 and the source of the fortieth PMOS transistor P40 are all connected to the first signal output terminal out4 of the third master-slave latch unit 6, and the thirty-seventh PMOS transistor P37 The source of the thirty-eighth PMOS transistor P38, the drain of the thirty-first NMOS transistor N31, the gate of the thirty-ninth PMOS transistor P39, and the gate of the thirty-second NMOS transistor N32 are all connected to the gate of the thirty-second NMOS transistor N32. The second signal output terminal of the three master-slave latch unit 6 The source of the thirty-first NMOS transistor N31 is connected to the drain of the thirty-third NMOS transistor N33, and the gate of the thirty-third NMOS transistor N33 is connected to the first signal input from the second slave latch circuit 11. terminal in2, the source of the thirty-second NMOS transistor N32 is connected to the drain of the thirty-fourth NMOS transistor N34, and the gate of the thirty-fourth NMOS transistor N34 is connected to the second slave latch circuit 11. signal input

The source of the thirty-third NMOS transistor N33, the source of the thirty-fourth NMOS transistor N34 and the drain of the thirty-fifth NMOS transistor N35 are connected, and the source of the thirty-fifth NMOS transistor N35 Grounded, the gate of the thirty-fifth NMOS transistor N35, the gate of the thirty-seventh PMOS transistor P37 and the gate of the fortieth PMOS transistor P40 are all connected to the clock signal input terminal clk, the second main latch circuit 10 The first signal output terminal out3 of the second slave latch circuit 11 is connected to the first signal input terminal in2, and the second signal output terminal of the second master latch circuit 10 and the second signal input terminal of the second slave latch circuit 11

connected.

The turn-on rate of the twenty-seventh PMOS transistor P27 described in the above embodiment is faster than that of the twenty-third PMOS transistor P23 and the twenty-sixth PMOS transistor P26, that is, the aspect ratio of the twenty-seventh PMOS transistor P27 is greater than that of the first PMOS transistor P27. The width-to-length ratio of the twenty-third PMOS transistor P23 and the twenty-sixth PMOS transistor P26, the conduction rate of the thirty-fifth NMOS transistor N35 is faster than that of the twenty-seventh NMOS transistor N27 and the thirtieth NMOS transistor N30, That is, the width-to-length ratio of the thirty-fifth NMOS transistor N35 is greater than the width-to-length ratios of the twenty-seventh NMOS transistor N27 and the thirtieth NMOS transistor N30.

均置为1；第一主从锁存单元4和第二主从锁存单元5输出内部储存的互补信号Qⁿ和

并将信号Qⁿ传送至第一互补信号产生电路1的第一信号输入端和第二互补信号产生电路3的第二信号输入端，将互补信号

传送至第一互补信号产生电路1的第二信号输入端和第二互补信号产生电路3的第一信号输入端；第一互补信号产生电路1和第二互补信号产生电路3进入求值阶段，均进行与/与非操作，第一互补信号产生电路1的第一信号输出端输出互补信号

，第一互补信号产生电路1的第二信号输出端输出信号x，第二互补信号产生电路3的第一信号输出端输出互补信号

第二互补信号产生电路3的第二信号输出端输出信号y；第三主从锁存单元6接收互补信号x和

并将其暂存在器件单元内部；第四主从锁存单元7接收互补信号y和

并将其暂存在器件单元内部；当时钟信号clk=1时，第一互补信号产生电路1和第二互补信号产生电路3进入预充阶段，输出端均置为低电平0状态；第三主从锁存单元6输出内部储存的互补信号x和

第四主从锁存单元7输出内部储存的互补信号y和

并将信号x传送至触发器原型电路2的第二信号输入端，将互补信号

传送至触发器原型电路2的第一信号输入端，将信号y传送至触发器原型电路2的第四信号输入端，将互补信号

传送至触发器原型电路2的第三信号输入端；触发器原型电路2进入求值阶段，进行或/或非操作，第一信号输出端Q和第二信号输出端

输出互补信号Qⁿ⁺¹和第一主从锁存单元4和第二主从锁存单元5接收并暂存触发器原型电路2输出的互补信号Qⁿ⁺¹和

The working process of the JK flip-flop of the present invention: when the clock signal clk=0, the flip-flop prototype circuit 2 enters the pre-charging stage, and the first signal output terminal Q and the second signal output terminal of the flip-flop prototype circuit 2

are all set to 1; the first master-slave latch unit 4 and the second master-slave latch unit 5 output internally stored complementary signals Q ⁿ and

And the signal Q ⁿ is sent to the first signal input end of the first complementary signal generating circuit 1 and the second signal input end of the second complementary signal generating circuit 3, and the complementary signal

Delivered to the second signal input end of the first complementary signal generating circuit 1 and the first signal input end of the second complementary signal generating circuit 3; the first complementary signal generating circuit 1 and the second complementary signal generating circuit 3 enter the evaluation stage, Both perform AND/AND operations, and the first signal output terminal of the first complementary signal generating circuit 1 outputs a complementary signal

, the second signal output terminal of the first complementary signal generating circuit 1 outputs the signal x, and the first signal output terminal of the second complementary signal generating circuit 3 outputs the complementary signal

The second signal output terminal of the second complementary signal generating circuit 3 outputs signal y; the third master-slave latch unit 6 receives the complementary signal x and

and temporarily store it inside the device unit; the fourth master-slave latch unit 7 receives complementary signals y and

And temporarily store it inside the device unit; when the clock signal clk=1, the first complementary signal generating circuit 1 and the second complementary signal generating circuit 3 enter the pre-charging stage, and the output terminals are all set to a low level 0 state; the third The master-slave latch unit 6 outputs internally stored complementary signals x and

The fourth master-slave latch unit 7 outputs internally stored complementary signals y and

and transmit the signal x to the second signal input end of the flip-flop prototype circuit 2, and the complementary signal

Transmit to the first signal input terminal of the flip-flop prototype circuit 2, transmit the signal y to the fourth signal input terminal of the flip-flop prototype circuit 2, and transmit the complementary signal

Delivered to the third signal input end of the flip-flop prototype circuit 2; the flip-flop prototype circuit 2 enters the evaluation stage, performs or/or non-operation, the first signal output Q and the second signal output

Output complementary signals Q ⁿ⁺¹ and The first master-slave latch unit 4 and the second master-slave latch unit 5 receive and temporarily store the complementary signals Q ⁿ⁺¹ and

均置为1；否则，当clk为高电平时，该电路在J=0、K=0时具有保持功能；在J=0、K=1时具有置0功能；在J=1、K=0时具有置1功能；在J=1、K=1时具有翻转功能。结果与表1一致，证明所设计电路具有正确的逻辑功能。图5给出了该触发器的功耗曲线，结果表明该设计在不同时钟周期内，功耗曲线是一致的，具有功耗恒定特性。In the HSPICE environment, using PTM90nm CMOS process device parameters, computer simulation is carried out on the above-mentioned JK flip-flop, wherein the twenty-seventh PMOS transistor P27 has a width-to-length ratio of 1.35um/0.09um, and the twenty-third PMOS transistor P23, The width-to-length ratio of the twenty-sixth PMOS transistor P26 is 0.09um/0.09um; the width-to-length ratio of the thirty-fifth NMOS transistor N35 is 0.9um/0.09um; The ratio is 0.09um/0.09um, the width-length ratio of other NMOS tubes is 0.36um/0.09um, and the width-length ratio of other PMOS tubes is 0.72um/0.09um. Figure 4 shows the analog waveform of the flip-flop, where the input signals J and K are "10101010..." and "00110011..." respectively, the operating frequency is 50MHz, and the load capacitance is 10fF. Analysis shows that if clk is low, flip-flop output Q and

All are set to 1; otherwise, when clk is high, the circuit has a hold function when J=0, K=0; it has a function of setting 0 when J=0, K=1; when J=1, K= It has the function of setting 1 when it is 0; it has the function of flipping when J=1 and K=1. The results are consistent with Table 1, proving that the designed circuit has correct logic functions. Figure 5 shows the power consumption curve of the flip-flop, and the results show that the design has the same power consumption curve in different clock cycles and has the characteristic of constant power consumption.

Table 1: The state transition truth table of the JK flip-flop of the present invention

Table 2: Comparison of the average energy consumption in the period of the present invention and the traditional JK flip-flop (unit: 10-14J)

Comparing the JK flip-flop of the present invention with the traditional JK flip-flop, the difference in average energy consumption in different clock cycles is used to reflect the anti-differential energy attack performance of the circuit. The computer simulation results are shown in Table 2. Where Eneri(i=1-8) is the average energy consumption of the circuit in the i-th clock cycle; E is the average energy consumption of the circuit in eight clock cycles, and σ _E is the mean square error of the average energy consumption in different clock cycles . The second line in Table 2 shows that when traditional JK flip-flops process different data in different clock cycles, the average energy consumption is different. Among the first four clock cycles, the average energy consumption in the third clock cycle is the largest. Analyzing JK From the function of the trigger, it can be seen that the flip-flop has a flip function at this time, so it can be seen that there is a correlation between its energy consumption and the processed data. If the traditional JK flip-flop is used as a part of the cryptographic system, the information protected by the cryptographic system can be analyzed by recording the energy consumption of the system and using the differential energy attack technology. The third row in the table shows that the average energy consumption of the JK flip-flop in each clock cycle of the present invention is basically the same, that is, it has the characteristics that energy consumption and processed data are independent of each other.

The normalized standard deviation (Normalized Standard Deviation, NSD) is a common standard to measure the performance of circuits against differential energy attacks, which is defined as:

$\mathrm{<span\; class="notranslate">\; NSD</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&sigma;</span>}}_{\mathrm{<span\; class="notranslate">\; E.</span>}}}{\stackrel{<span\; class="notranslate">\; \&OverBar;</span>}{\mathrm{<span\; class="notranslate">\; E.</span>}}}$

Therefore, it can be calculated that the normalized standard deviations of the JK flip-flop of the present invention and the traditional JK flip-flop are 0.6% and 43.8%, respectively. Compared with the traditional design, the normalized standard deviation of this design is only 1/73 (0.6%/43.8%) of the former, which proves that its defense performance against energy attacks is remarkable.

Claims (6)

1. a JK flip-flop of defending Attacks, it is characterized in that comprising the first mutual supplementary signal generation circuit, the second mutual supplementary signal generation circuit, trigger prototype circuit, first principal and subordinate's latch units, second principal and subordinate's latch units, the 3rd principal and subordinate's latch units and the 4th principal and subordinate's latch units, the first signal output of described trigger prototype circuit is connected with the first signal input of described first principal and subordinate's latch units, the secondary signal output of described trigger prototype circuit is connected with the secondary signal input of described first principal and subordinate's latch units, the first signal output of first described principal and subordinate's latch units is connected with the first signal input of the first described mutual supplementary signal generation circuit, the secondary signal output of first described principal and subordinate's latch units is connected with the secondary signal input of the first described mutual supplementary signal generation circuit, the first signal output of the first described mutual supplementary signal generation circuit is connected with the first signal input of described the 3rd principal and subordinate's latch units, the secondary signal output of the first described mutual supplementary signal generation circuit is connected with the secondary signal input of described the 3rd principal and subordinate's latch units, the first signal output of the 3rd described principal and subordinate's latch units is connected with the first signal input of described trigger prototype circuit, the secondary signal output of the 3rd described principal and subordinate's latch units is connected with the secondary signal input of described trigger prototype circuit, the first signal output of described trigger prototype circuit is connected with the secondary signal input of described second principal and subordinate's latch units, the secondary signal output of described trigger prototype circuit is connected with the first signal input of described second principal and subordinate's latch units, the first signal output of second described principal and subordinate's latch units is connected with the first signal input of the second described mutual supplementary signal generation circuit, the secondary signal output of second described principal and subordinate's latch units is connected with the secondary signal input of the second described mutual supplementary signal generation circuit, the first signal output of the second described mutual supplementary signal generation circuit is connected with the first signal input of described the 4th principal and subordinate's latch units, the secondary signal output of the second described mutual supplementary signal generation circuit is connected with the secondary signal input of described the 4th principal and subordinate's latch units, the first signal output of the 4th described principal and subordinate's latch units is connected with the 3rd signal input part of described trigger prototype circuit, the secondary signal output of the 4th described principal and subordinate's latch units is connected with the 4th signal input part of described trigger prototype circuit.

2. a kind of JK flip-flop of defending Attacks according to claim 1, is characterized in that the first described mutual supplementary signal generation circuit managed by a PMOS, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe form, and the drain electrode of a described PMOS pipe is connected with power positive end, the source electrode of a described PMOS pipe, the drain electrode three of the drain electrode of the 2nd described PMOS pipe and described the 3rd PMOS pipe is connected, the grid of the 2nd described PMOS pipe is connected with the 3rd signal input part of the first described mutual supplementary signal generation circuit, the grid of the 3rd described PMOS pipe is connected with the 4th signal input part of the first described mutual supplementary signal generation circuit, the source electrode of the 2nd described PMOS pipe, the drain electrode three of the drain electrode of the 4th described PMOS pipe and described the 6th PMOS pipe is connected, the source electrode of the 3rd described PMOS pipe, the drain electrode three of the drain electrode of the 5th described PMOS pipe and described the 7th PMOS pipe is connected, the grid of the 4th described PMOS pipe, the grid of the 5th described PMOS pipe is all connected with the first signal input of described the first mutual supplementary signal generation circuit, the source electrode of the 4th described PMOS pipe, the source electrode of the 6th described PMOS pipe, the drain electrode of the source electrode of the 7th described PMOS pipe and the 8th described PMOS pipe is connected, the grid of the 6th described PMOS pipe, the grid of the 7th described PMOS pipe is all connected with the secondary signal input of described the first mutual supplementary signal generation circuit, and the source electrode of the 5th described PMOS pipe is connected with the drain electrode of the 9th described PMOS pipe, the source electrode of the 8th described PMOS pipe, the drain electrode of a described NMOS pipe, the drain electrode of the 2nd described NMOS pipe, the grid of the grid of the 9th described PMOS pipe and the 3rd described NMOS pipe is all connected with the first signal output of described the first mutual supplementary signal generation circuit, the grid of the 8th described PMOS pipe, the grid of the 2nd described NMOS pipe, the drain electrode of the 3rd described NMOS pipe, the drain electrode of the source electrode of the 9th described PMOS pipe and the 4th described NMOS pipe is all connected with the secondary signal output of described the first mutual supplementary signal generation circuit, the source electrode of a described NMOS pipe, the source electrode of the 2nd described NMOS pipe, the source grounding of the source electrode of the 3rd described NMOS pipe and the 4th described NMOS pipe, the grid of a described PMOS pipe, the grid of the grid of a described NMOS pipe and the 4th described NMOS pipe is all connected with clock signal input terminal.

3. a kind of JK flip-flop of defending Attacks according to claim 1, the second mutual supplementary signal generation circuit described in it is characterized in that is managed by the tenth PMOS, the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 17 PMOS pipe, the 18 PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe form, the drain electrode of the tenth described PMOS pipe is connected with power positive end, the source electrode of the tenth described PMOS pipe, the drain electrode three of the drain electrode of the 11 described PMOS pipe and the 12 described PMOS pipe is connected, the grid of the 11 described PMOS pipe is connected with the 3rd signal input part of the second described mutual supplementary signal generation circuit, the grid of the 12 described PMOS pipe is connected with the 4th signal input part of the second described mutual supplementary signal generation circuit, the source electrode of the 11 described PMOS pipe, the drain electrode three of the drain electrode of the 13 described PMOS pipe and the 15 described PMOS pipe is connected, the source electrode of the 12 described PMOS pipe, the drain electrode three of the drain electrode of the 14 described PMOS pipe and the 16 described PMOS pipe is connected, the grid of the 13 described PMOS pipe, the grid of the 14 described PMOS pipe is all connected with the first signal input of described the second mutual supplementary signal generation circuit, the source electrode of the 13 described PMOS pipe, the source electrode of the 15 described PMOS pipe, the drain electrode of the source electrode of the 16 described PMOS pipe and the 17 described PMOS pipe is connected, the grid of the 15 described PMOS pipe, the grid of the 16 described PMOS pipe is all connected with the secondary signal input of described the second mutual supplementary signal generation circuit, the source electrode of the 14 described PMOS pipe is connected with the drain electrode of the 18 described PMOS pipe, the source electrode of the 17 described PMOS pipe, the drain electrode of the 5th described NMOS pipe, the drain electrode of the 6th described NMOS pipe, the grid of the grid of the 18 described PMOS pipe and the 7th described NMOS pipe is all connected with the first signal output of described the second mutual supplementary signal generation circuit, the grid of the 17 described PMOS pipe, the grid of the 6th described NMOS pipe, the drain electrode of the 7th described NMOS pipe, the drain electrode of the source electrode of the 18 described PMOS pipe and the 8th described NMOS pipe is all connected with the secondary signal output of described the second mutual supplementary signal generation circuit, the source electrode of the 5th described NMOS pipe, the source electrode of the 6th described NMOS pipe, the source grounding of the source electrode of the 7th described NMOS pipe and the 8th described NMOS pipe, the grid of the tenth described PMOS pipe, the grid of the grid of the 5th described NMOS pipe and the 8th described NMOS pipe is all connected with clock signal input terminal.

4. a kind of JK flip-flop of defending Attacks according to claim 1, is characterized in that described trigger prototype circuit managed by the 19 PMOS, the 20 PMOS pipe, the 21 PMOS pipe, the 22 PMOS pipe, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe form, the drain electrode of the 19 described PMOS pipe, the drain electrode of the 20 described PMOS pipe, the drain electrode of the drain electrode of the 21 described PMOS pipe and the 22 described PMOS pipe is all connected with power positive end, the grid of the 20 described PMOS pipe, the grid of the 9th described NMOS pipe, the source electrode of the 21 described PMOS pipe, the source electrode of the drain electrode of the tenth described NMOS pipe and the 22 described PMOS pipe is all connected with the first signal output of described trigger prototype circuit, the source electrode of the 19 described PMOS pipe, the source electrode of the 20 described PMOS pipe, the drain electrode of the 9th described NMOS pipe, the grid of the grid of the 21 described PMOS pipe and the tenth described NMOS pipe is all connected with the secondary signal output of described trigger prototype circuit, the source electrode of the 9th described NMOS pipe, the drain electrode of the 13 described NMOS pipe, the drain electrode of the drain electrode of the 11 described NMOS pipe and the 14 described NMOS pipe is connected, and the source electrode of the tenth described NMOS pipe is connected with the drain electrode of the 12 described NMOS pipe, the grid of the 11 described NMOS pipe, the grid of the 12 described NMOS pipe is all connected with the first signal input of described trigger prototype circuit, the grid of the 13 described NMOS pipe, the grid of the 14 described NMOS pipe is all connected with the secondary signal input of described trigger prototype circuit, the source electrode of the 11 described NMOS pipe, the drain electrode three of the source electrode of the 13 described NMOS pipe and the 15 described NMOS pipe is connected, the source electrode of the 12 described NMOS pipe, the drain electrode three of the source electrode of the 14 described NMOS pipe and the 16 described NMOS pipe is connected, the source electrode of the 15 described NMOS pipe, the drain electrode three of the source electrode of the 16 described NMOS pipe and the 17 described NMOS pipe is connected, the grid of the 16 described NMOS pipe is connected with the 3rd signal input part of described trigger prototype circuit, the grid of the 15 described NMOS pipe is connected with the 4th signal input part of described trigger prototype circuit, the source ground of the 17 described NMOS pipe, the grid of the 17 described NMOS pipe, the grid of the grid of the 19 described PMOS pipe and the 22 described PMOS pipe is all connected with clock signal input terminal.

5. a kind of JK flip-flop of defending Attacks according to claim 1, first principal and subordinate's latch units described in it is characterized in that is identical with the internal structure of second described principal and subordinate's latch units, first described principal and subordinate's latch units is comprised of from latch cicuit the first main latch circuit and first, the first described main latch circuit is managed by the 23 PMOS, the 24 PMOS pipe, the 25 PMOS pipe, the 26 PMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe, the 20 NMOS pipe, the 21 NMOS pipe and the 22 NMOS pipe form, the drain electrode of the 23 described PMOS pipe, the drain electrode of the 24 described PMOS pipe, the drain electrode of the drain electrode of the 25 described PMOS pipe and the 26 described PMOS pipe is all connected with power positive end, the grid of the 24 described PMOS pipe, the grid of the 18 described NMOS pipe, the source electrode of the 25 described PMOS pipe, the source electrode of the drain electrode of the 19 described NMOS pipe and the 26 described PMOS pipe is all connected with the first signal output of described the first main latch circuit, the source electrode of the 23 described PMOS pipe, the source electrode of the 24 described PMOS pipe, the drain electrode of the 18 described NMOS pipe, the grid of the grid of the 25 described PMOS pipe and the 19 described NMOS pipe is all connected with the secondary signal output of described the first main latch circuit, the source electrode of the 18 described NMOS pipe is connected with the drain electrode of the 20 described NMOS pipe, the grid of the 20 described NMOS pipe is connected with the first signal input of described first principal and subordinate's latch units, the source electrode of the 19 described NMOS pipe is connected with the drain electrode of the 21 described NMOS pipe, the grid of the 21 described NMOS pipe is connected with the secondary signal input of described first principal and subordinate's latch units, the source electrode of the 20 described NMOS pipe, the drain electrode three of the source electrode of the 21 described NMOS pipe and the 22 described NMOS pipe is connected, the source ground of the 22 described NMOS pipe, the grid of the 22 described NMOS pipe, the grid of the grid of the 23 described PMOS pipe and the 26 described PMOS pipe is all connected with clock signal input terminal, described first is managed by the 27 PMOS from latch cicuit, the 28 PMOS pipe, the 29 PMOS pipe, the 30 PMOS pipe, the 31 PMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS pipe and the 26 NMOS pipe form, the drain electrode of the 27 described PMOS pipe is connected with power positive end, the source electrode of the 27 described PMOS pipe, the drain electrode three of the drain electrode of the 28 described PMOS pipe and the 29 described PMOS pipe is connected, the grid of the 28 described PMOS pipe is connected from the first signal input of latch cicuit with described first, the grid of the 29 described PMOS pipe is connected from the secondary signal input of latch cicuit with described first, the source electrode of the 28 described PMOS pipe is connected with the drain electrode of the 30 described PMOS pipe, the source electrode of the 29 described PMOS pipe is connected with the drain electrode of the 31 described PMOS pipe, the grid of the 30 described PMOS pipe, the grid of the 24 described NMOS pipe, the source electrode of the 31 described PMOS pipe, the drain electrode of the drain electrode of the 25 described NMOS pipe and the 26 described NMOS pipe is all connected with the first signal output of described first principal and subordinate's latch units, the source electrode of the 30 described PMOS pipe, the drain electrode of the 23 described NMOS pipe, the drain electrode of the 24 described NMOS pipe, the grid of the grid of the 31 described PMOS pipe and the 25 described NMOS pipe is all connected with the secondary signal output of described first principal and subordinate's latch units, the source electrode of the 23 described NMOS pipe, the source electrode of the 24 described NMOS pipe, the source grounding of the source electrode of the 25 described NMOS pipe and the 26 described NMOS pipe, the grid of the 23 described NMOS pipe, the grid of the grid of the 26 described NMOS pipe and the 27 described PMOS pipe is all connected with clock signal input terminal, the first signal output of the first described main latch circuit is connected from the first signal input of latch cicuit with described first, the secondary signal output of the first described main latch circuit is connected from the secondary signal input of latch cicuit with described first.

6. a kind of JK flip-flop of defending Attacks according to claim 1, the 3rd principal and subordinate's latch units described in it is characterized in that is identical with the internal structure of the 4th described principal and subordinate's latch units, the 3rd described principal and subordinate's latch units is comprised of from latch cicuit the second main latch circuit and second, the second described main latch circuit is managed by the 32 PMOS, the 33 PMOS pipe, the 34 PMOS pipe, the 35 PMOS pipe, the 36 PMOS pipe, the 27 NMOS pipe, the 28 NMOS pipe, the 29 NMOS pipe and the 30 NMOS pipe form, the drain electrode of the 32 described PMOS pipe is connected with power positive end, the source electrode of the 32 described PMOS pipe, the drain electrode three of the drain electrode of the 33 described PMOS pipe and the 34 described PMOS pipe is connected, the grid of the 33 described PMOS pipe is connected with the first signal input of described the 3rd principal and subordinate's latch units, the grid of the 34 described PMOS pipe is connected with the secondary signal input of described the 3rd principal and subordinate's latch units, the source electrode of the 33 described PMOS pipe is connected with the drain electrode of the 35 described PMOS pipe, the source electrode of the 34 described PMOS pipe is connected with the drain electrode of the 36 described PMOS pipe, the grid of the 35 described PMOS pipe, the grid of the 28 described NMOS pipe, the source electrode of the 36 described PMOS pipe, the drain electrode of the drain electrode of the 29 described NMOS pipe and the 30 described NMOS pipe is all connected with the first signal output of described the second main latch circuit, the source electrode of the 35 described PMOS pipe, the drain electrode of the 27 described NMOS pipe, the drain electrode of the 28 described NMOS pipe, the grid of the grid of the 36 described PMOS pipe and the 29 described NMOS pipe is all connected with the secondary signal output of described the second main latch circuit, the source electrode of the 27 described NMOS pipe, the source electrode of the 28 described NMOS pipe, the source grounding of the source electrode of the 29 described NMOS pipe and the 30 described NMOS pipe, the grid of the 27 described NMOS pipe, the grid of the grid of the 30 described NMOS pipe and the 32 described PMOS pipe is all connected with clock signal input terminal, described second is managed by the 37 PMOS from latch cicuit, the 38 PMOS pipe, the 39 PMOS pipe, the 40 PMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS pipe and the 35 NMOS pipe form, the drain electrode of the 37 described PMOS pipe, the drain electrode of the 38 described PMOS pipe, the drain electrode of the drain electrode of the 39 described PMOS pipe and the 40 described PMOS pipe is all connected with power positive end, the grid of the 38 described PMOS pipe, the grid of the 31 described NMOS pipe, the source electrode of the 39 described PMOS pipe, the source electrode of the drain electrode of the 32 described NMOS pipe and the 40 described PMOS pipe is all connected with the first signal output of described the 3rd principal and subordinate's latch units, the source electrode of the 37 described PMOS pipe, the source electrode of the 38 described PMOS pipe, the drain electrode of the 31 described NMOS pipe, the grid of the grid of the 39 described PMOS pipe and the 32 described NMOS pipe is all connected with the secondary signal output of described the 3rd principal and subordinate's latch units, the source electrode of the 31 described NMOS pipe is connected with the drain electrode of the 33 described NMOS pipe, the grid of the 33 described NMOS pipe is connected from the first signal input of latch cicuit with described second, the source electrode of the 32 described NMOS pipe is connected with the drain electrode of the 34 described NMOS pipe, the grid of the 34 described NMOS pipe is connected from the secondary signal input of latch cicuit with described second, the source electrode of the 33 described NMOS pipe, the drain electrode three of the source electrode of the 34 described NMOS pipe and the 35 described NMOS pipe is connected, the source ground of the 35 described NMOS pipe, the grid of the 35 described NMOS pipe, the grid of the grid of the 37 described PMOS pipe and the 40 described PMOS pipe is all connected with clock signal input terminal, the first signal output of the second described main latch circuit is connected from the first signal input of latch cicuit with described second, the secondary signal output of the second described main latch circuit is connected from the secondary signal input of latch cicuit with described second.

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