CN102394606A - Jump-key (JK) trigger capable of defending power attack - Google Patents

Abstract

The invention discloses a JK flip-flop for defending against energy attacks, which is characterized in that it includes a first complementary signal generating circuit, a second complementary signal generating circuit, a flip-flop prototype circuit, a first master-slave latch unit, and a second master-slave latch unit, the third master-slave latch unit and the fourth master-slave latch unit, the flip-flop prototype circuit is connected with the first master-slave latch unit, the first master-slave latch unit is connected with the first complementary signal generating circuit, and the first The complementary signal generating circuit is connected with the third master-slave latch unit, the third master-slave latch unit is connected with the flip-flop prototype circuit, the flip-flop prototype circuit is connected with the second master-slave latch unit, and the second master-slave latch unit is connected with the The second complementary signal generating circuit is connected, the second complementary signal generating circuit is connected with the fourth master-slave latch unit, and the fourth master-slave latch unit is connected with the flip-flop prototype circuit; the advantage is that the energy consumption and the processed data are independent of each other and can be The consumption is stable, and it has good performance in defending against energy attacks.

Description

A kind of JK flip-flop of defending energy attack

Technical field

The present invention relates to a kind of JK flip-flop, especially relate to a kind of JK flip-flop of defending energy attack.

Background technology

Along with computer and development of Communication Technique, the user is more and more urgent to information stores, processing and transmission safety sexual demand, generally is employed in to encrypt the strategy of carrying out cryptographic algorithm on the device, reaches the purpose of protection information security.Yet physical device always will leak out the various information relevant with cryptographic system itself in carrying out the cryptographic algorithm process, such as energy consumption, electromagnetic radiation, running time etc.The assailant utilize these information attacks encrypt process that devices obtain keys be called lie attack (Side Channel Attack, SCA).In many lie attack options, differential power attack (Differential PowerAnalysis, DPA) technology be proved to be a kind of more effectively and the strategy that is easy to realize, the safety of crypto module is constituted significant threat.

In the cryptographic system, trigger is a kind of the most frequently used element circuit with memory function, ability stored information, is widely used in logical devices such as register, counter, shift register.Static complementary cmos logical block is the element of conventional trigger device; Because it is consumed energy when there is 0 → 1,1 → 0 saltus step in node state only; And when node state remains unchanged consumed energy not; Therefore there is asymmetry in its energy consumption, and these characteristics have become the breach that the differential power attack technology cracks the conventional cryptography device.

Summary of the invention

Technical problem to be solved by this invention provides and is a kind ofly guaranteeing to have under the prerequisite of correct logic functions, energy consumption with the JK flip-flop of the defence energy attack that the data of handling are separate and energy consumption is stable.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of JK flip-flop of defending energy attack; Comprise first mutual supplementary signal generation circuit, second mutual supplementary signal generation circuit, trigger prototype circuit, first principal and subordinate's latch units, second principal and subordinate's latch units, the 3rd principal and subordinate's latch units and the 4th principal and subordinate's latch units; First signal output part of described trigger prototype circuit is connected with first signal input part of described first principal and subordinate's latch units; The secondary signal output of described trigger prototype circuit is connected with the secondary signal input of described first principal and subordinate's latch units; First signal output part of described first principal and subordinate's latch units is connected with first signal input part of described first mutual supplementary signal generation circuit; The secondary signal output of described first principal and subordinate's latch units is connected with the secondary signal input of described first mutual supplementary signal generation circuit; First signal output part of described first mutual supplementary signal generation circuit is connected with first signal input part of described the 3rd principal and subordinate's latch units; The secondary signal output of described first mutual supplementary signal generation circuit is connected with the secondary signal input of described the 3rd principal and subordinate's latch units; First signal output part of described the 3rd principal and subordinate's latch units is connected with first signal input part of described trigger prototype circuit; The secondary signal output of described the 3rd principal and subordinate's latch units is connected with the secondary signal input of described trigger prototype circuit; First signal output part of described trigger prototype circuit is connected with the secondary signal input of described second principal and subordinate's latch units; The secondary signal output of described trigger prototype circuit is connected with first signal input part of described second principal and subordinate's latch units; First signal output part of described second principal and subordinate's latch units is connected with first signal input part of described second mutual supplementary signal generation circuit; The secondary signal output of described second principal and subordinate's latch units is connected with the secondary signal input of described second mutual supplementary signal generation circuit; First signal output part of described second mutual supplementary signal generation circuit is connected with first signal input part of described the 4th principal and subordinate's latch units; The secondary signal output of described second mutual supplementary signal generation circuit is connected with the secondary signal input of described the 4th principal and subordinate's latch units; First signal output part of described the 4th principal and subordinate's latch units is connected with the 3rd signal input part of described trigger prototype circuit, and the secondary signal output of described the 4th principal and subordinate's latch units is connected with the 4th signal input part of described trigger prototype circuit.

Described first mutual supplementary signal generation circuit by a PMOS manage, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe form; The drain electrode of described PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described PMOS pipe, described the 2nd PMOS pipe and described the 3rd PMOS pipe is connected; The grid of described the 2nd PMOS pipe is connected with the 3rd signal input part of described first mutual supplementary signal generation circuit; The grid of described the 3rd PMOS pipe is connected with the 4th signal input part of described first mutual supplementary signal generation circuit; The drain electrode three of the drain electrode of the source electrode of described the 2nd PMOS pipe, described the 4th PMOS pipe and described the 6th PMOS pipe is connected; The drain electrode three of the drain electrode of the source electrode of described the 3rd PMOS pipe, described the 5th PMOS pipe and described the 7th PMOS pipe is connected; The grid of the grid of described the 4th PMOS pipe, described the 5th PMOS pipe all is connected with first signal input part of described first mutual supplementary signal generation circuit; The drain electrode of the source electrode of the source electrode of the source electrode of described the 4th PMOS pipe, described the 6th PMOS pipe, described the 7th PMOS pipe and described the 8th PMOS pipe is connected; The grid of the grid of described the 6th PMOS pipe, described the 7th PMOS pipe all is connected with the secondary signal input of described first mutual supplementary signal generation circuit; The source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 9th PMOS pipe; The grid of the grid of the drain electrode of the drain electrode of the source electrode of described the 8th PMOS pipe, described NMOS pipe, described the 2nd NMOS pipe, described the 9th PMOS pipe and described the 3rd NMOS pipe all is connected with first signal output part of described first mutual supplementary signal generation circuit; The drain electrode of the source electrode of the drain electrode of the grid of the grid of described the 8th PMOS pipe, described the 2nd NMOS pipe, described the 3rd NMOS pipe, described the 9th PMOS pipe and described the 4th NMOS pipe all is connected with the secondary signal output of described first mutual supplementary signal generation circuit; The source grounding of the source electrode of the source electrode of the source electrode of described NMOS pipe, described the 2nd NMOS pipe, described the 3rd NMOS pipe and described the 4th NMOS pipe, the grid of the grid of described PMOS pipe, described NMOS pipe and the grid of described the 4th NMOS pipe all are connected with clock signal input terminal.

Described second mutual supplementary signal generation circuit by the tenth PMOS manage, the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 17 PMOS pipe, the 18 PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe form; The drain electrode of described the tenth PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described the tenth PMOS pipe, described the 11 PMOS pipe and described the 12 PMOS pipe is connected; The grid of described the 11 PMOS pipe is connected with the 3rd signal input part of described second mutual supplementary signal generation circuit; The grid of described the 12 PMOS pipe is connected with the 4th signal input part of described second mutual supplementary signal generation circuit; The drain electrode three of the drain electrode of the source electrode of described the 11 PMOS pipe, described the 13 PMOS pipe and described the 15 PMOS pipe is connected; The drain electrode three of the drain electrode of the source electrode of described the 12 PMOS pipe, described the 14 PMOS pipe and described the 16 PMOS pipe is connected; The grid of the grid of described the 13 PMOS pipe, described the 14 PMOS pipe all is connected with first signal input part of described second mutual supplementary signal generation circuit; The drain electrode of the source electrode of the source electrode of the source electrode of described the 13 PMOS pipe, described the 15 PMOS pipe, described the 16 PMOS pipe and described the 17 PMOS pipe is connected; The grid of the grid of described the 15 PMOS pipe, described the 16 PMOS pipe all is connected with the secondary signal input of described second mutual supplementary signal generation circuit; The source electrode of described the 14 PMOS pipe is connected with the drain electrode of described the 18 PMOS pipe; The grid of the grid of the drain electrode of the drain electrode of the source electrode of described the 17 PMOS pipe, described the 5th NMOS pipe, described the 6th NMOS pipe, described the 18 PMOS pipe and described the 7th NMOS pipe all is connected with first signal output part of described second mutual supplementary signal generation circuit; The drain electrode of the source electrode of the drain electrode of the grid of the grid of described the 17 PMOS pipe, described the 6th NMOS pipe, described the 7th NMOS pipe, described the 18 PMOS pipe and described the 8th NMOS pipe all is connected with the secondary signal output of described second mutual supplementary signal generation circuit; The source grounding of the source electrode of the source electrode of the source electrode of described the 5th NMOS pipe, described the 6th NMOS pipe, described the 7th NMOS pipe and described the 8th NMOS pipe, the grid of the grid of described the tenth PMOS pipe, described the 5th NMOS pipe and the grid of described the 8th NMOS pipe all are connected with clock signal input terminal.

Described trigger prototype circuit is made up of the 19 PMOS pipe, the 20 PMOS pipe, the 21 PMOS pipe, the 22 PMOS pipe, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 19 PMOS pipe, described the 20 PMOS pipe, described the 21 PMOS pipe and described the 22 PMOS pipe all is connected with power positive end; The source electrode of the drain electrode of the source electrode of the grid of the grid of described the 20 PMOS pipe, described the 9th NMOS pipe, described the 21 PMOS pipe, described the tenth NMOS pipe and described the 22 PMOS pipe all is connected with first signal output part of described trigger prototype circuit; The grid of the grid of the drain electrode of the source electrode of the source electrode of described the 19 PMOS pipe, described the 20 PMOS pipe, described the 9th NMOS pipe, described the 21 PMOS pipe and described the tenth NMOS pipe all is connected with the secondary signal output of described trigger prototype circuit; The drain electrode of the drain electrode of the drain electrode of the source electrode of described the 9th NMOS pipe, described the 13 NMOS pipe, described the 11 NMOS pipe and described the 14 NMOS pipe is connected; The source electrode of described the tenth NMOS pipe is connected with the drain electrode of described the 12 NMOS pipe; The grid of the grid of described the 11 NMOS pipe, described the 12 NMOS pipe all is connected with first signal input part of described trigger prototype circuit; The grid of the grid of described the 13 NMOS pipe, described the 14 NMOS pipe all is connected with the secondary signal input of described trigger prototype circuit; The drain electrode three of the source electrode of the source electrode of described the 11 NMOS pipe, described the 13 NMOS pipe and described the 15 NMOS pipe is connected; The drain electrode three of the source electrode of the source electrode of described the 12 NMOS pipe, described the 14 NMOS pipe and described the 16 NMOS pipe is connected; The drain electrode three of the source electrode of the source electrode of described the 15 NMOS pipe, described the 16 NMOS pipe and described the 17 NMOS pipe is connected; The grid of described the 16 NMOS pipe is connected with the 3rd signal input part of described trigger prototype circuit; The grid of described the 15 NMOS pipe is connected with the 4th signal input part of described trigger prototype circuit; The source ground of described the 17 NMOS pipe, the grid of the grid of described the 17 NMOS pipe, described the 19 PMOS pipe and the grid of described the 22 PMOS pipe all are connected with clock signal input terminal.

Described first principal and subordinate's latch units is identical with the internal structure of described second principal and subordinate's latch units; Described first principal and subordinate's latch units is made up of from latch cicuit first main latch circuit and first; Described first main latch circuit is made up of the 23 PMOS pipe, the 24 PMOS pipe, the 25 PMOS pipe, the 26 PMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe, the 20 NMOS pipe, the 21 NMOS pipe and the 22 NMOS pipe; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 23 PMOS pipe, described the 24 PMOS pipe, described the 25 PMOS pipe and described the 26 PMOS pipe all is connected with power positive end; The source electrode of the drain electrode of the source electrode of the grid of the grid of described the 24 PMOS pipe, described the 18 NMOS pipe, described the 25 PMOS pipe, described the 19 NMOS pipe and described the 26 PMOS pipe all is connected with first signal output part of described first main latch circuit; The grid of the grid of the drain electrode of the source electrode of the source electrode of described the 23 PMOS pipe, described the 24 PMOS pipe, described the 18 NMOS pipe, described the 25 PMOS pipe and described the 19 NMOS pipe all is connected with the secondary signal output of described first main latch circuit; The source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 20 NMOS pipe; The grid of described the 20 NMOS pipe is connected with first signal input part of described first principal and subordinate's latch units; The source electrode of described the 19 NMOS pipe is connected with the drain electrode of described the 21 NMOS pipe; The grid of described the 21 NMOS pipe is connected with the secondary signal input of described first principal and subordinate's latch units; The drain electrode three of the source electrode of the source electrode of described the 20 NMOS pipe, described the 21 NMOS pipe and described the 22 NMOS pipe is connected; The source ground of described the 22 NMOS pipe, the grid of the grid of described the 22 NMOS pipe, described the 23 PMOS pipe and the grid of described the 26 PMOS pipe all are connected with clock signal input terminal, described first from latch cicuit by the 27 PMOS pipe, the 28 PMOS pipe, the 29 PMOS pipe, the 30 PMOS pipe, the 31 PMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS manages and the 26 NMOS manages and forms; The drain electrode of described the 27 PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described the 27 PMOS pipe, described the 28 PMOS pipe and described the 29 PMOS pipe is connected, and the grid of described the 28 PMOS pipe is connected with described first first signal input part from latch cicuit, and the grid of described the 29 PMOS pipe is connected with the described first secondary signal input from latch cicuit; The source electrode of described the 28 PMOS pipe is connected with the drain electrode of described the 30 PMOS pipe; The source electrode of described the 29 PMOS pipe is connected with the drain electrode of described the 31 PMOS pipe, and the drain electrode of the grid of described the 30 PMOS pipe, the grid of described the 24 NMOS pipe, the source electrode of described the 31 PMOS pipe, described the 25 NMOS pipe and the drain electrode of described the 26 NMOS pipe all are connected with first signal output part of described first principal and subordinate's latch units, and the grid of the source electrode of described the 30 PMOS pipe, the drain electrode of described the 23 NMOS pipe, the drain electrode of described the 24 NMOS pipe, described the 31 PMOS pipe and the grid of described the 25 NMOS pipe all are connected with the secondary signal output of described first principal and subordinate's latch units; The source grounding of the source electrode of the source electrode of the source electrode of described the 23 NMOS pipe, described the 24 NMOS pipe, described the 25 NMOS pipe and described the 26 NMOS pipe; The grid of the grid of the grid of described the 23 NMOS pipe, described the 26 NMOS pipe and described the 27 PMOS pipe all is connected with clock signal input terminal, and first signal output part of described first main latch circuit is connected with described first first signal input part from latch cicuit, and the secondary signal output of described first main latch circuit is connected with the described first secondary signal input from latch cicuit.

Described the 3rd principal and subordinate's latch units is identical with the internal structure of described the 4th principal and subordinate's latch units; Described the 3rd principal and subordinate's latch units is made up of from latch cicuit second main latch circuit and second; Described second main latch circuit is made up of the 32 PMOS pipe, the 33 PMOS pipe, the 34 PMOS pipe, the 35 PMOS pipe, the 36 PMOS pipe, the 27 NMOS pipe, the 28 NMOS pipe, the 29 NMOS pipe and the 30 NMOS pipe; The drain electrode of described the 32 PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described the 32 PMOS pipe, described the 33 PMOS pipe and described the 34 PMOS pipe is connected; The grid of described the 33 PMOS pipe is connected with first signal input part of described the 3rd principal and subordinate's latch units; The grid of described the 34 PMOS pipe is connected with the secondary signal input of described the 3rd principal and subordinate's latch units; The source electrode of described the 33 PMOS pipe is connected with the drain electrode of described the 35 PMOS pipe; The source electrode of described the 34 PMOS pipe is connected with the drain electrode of described the 36 PMOS pipe; The drain electrode of the drain electrode of the source electrode of the grid of the grid of described the 35 PMOS pipe, described the 28 NMOS pipe, described the 36 PMOS pipe, described the 29 NMOS pipe and described the 30 NMOS pipe all is connected with first signal output part of described second main latch circuit; The grid of the grid of the drain electrode of the drain electrode of the source electrode of described the 35 PMOS pipe, described the 27 NMOS pipe, described the 28 NMOS pipe, described the 36 PMOS pipe and described the 29 NMOS pipe all is connected with the secondary signal output of described second main latch circuit; The source grounding of the source electrode of the source electrode of the source electrode of described the 27 NMOS pipe, described the 28 NMOS pipe, described the 29 NMOS pipe and described the 30 NMOS pipe, the grid of the grid of described the 27 NMOS pipe, described the 30 NMOS pipe and the grid of described the 32 PMOS pipe all are connected with clock signal input terminal, described second from latch cicuit by the 37 PMOS pipe, the 38 PMOS pipe, the 39 PMOS pipe, the 40 PMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS manages and the 35 NMOS manages and forms; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 37 PMOS pipe, described the 38 PMOS pipe, described the 39 PMOS pipe and described the 40 PMOS pipe all is connected with power positive end; The source electrode of the drain electrode of the source electrode of the grid of the grid of described the 38 PMOS pipe, described the 31 NMOS pipe, described the 39 PMOS pipe, described the 32 NMOS pipe and described the 40 PMOS pipe all is connected with first signal output part of described the 3rd principal and subordinate's latch units, and the grid of the source electrode of described the 37 PMOS pipe, the source electrode of described the 38 PMOS pipe, the drain electrode of described the 31 NMOS pipe, described the 39 PMOS pipe and the grid of described the 32 NMOS pipe all are connected with the secondary signal output of described the 3rd principal and subordinate's latch units, and the source electrode of described the 31 NMOS pipe is connected with the drain electrode of described the 33 NMOS pipe; The grid of described the 33 NMOS pipe is connected with described second first signal input part from latch cicuit; The source electrode of described the 32 NMOS pipe is connected with the drain electrode of described the 34 NMOS pipe, and the grid of described the 34 NMOS pipe is connected with the described second secondary signal input from latch cicuit, and the source electrode of the source electrode of described the 33 NMOS pipe, described the 34 NMOS pipe and the drain electrode three of described the 35 NMOS pipe are connected; The source ground of described the 35 NMOS pipe; The grid of the grid of the grid of described the 35 NMOS pipe, described the 37 PMOS pipe and described the 40 PMOS pipe all is connected with clock signal input terminal, and first signal output part of described second main latch circuit is connected with described second first signal input part from latch cicuit, and the secondary signal output of described second main latch circuit is connected with the described second secondary signal input from latch cicuit.

Compared with prior art; The invention has the advantages that on the basis of traditional JK flip-flop structure; The sensitive scale-up version logic that will have energy consumption symmetry characteristics is incorporated in the design of JK flip-flop; And combine the influence of channel width-over-length ratio to message transmission rate, a kind of JK flip-flop of defending energy attack is proposed; Under the HSPICE environment; Adopt PTM 90nm CMOS technology device parameters to carry out Computer Simulation; The logic function of this trigger of experimental result proof is correct, energy consumption stable and energy consumption and the data of handling separate, have the performance of good defence energy attack.

Description of drawings

Fig. 1 is the circuit theory diagrams of JK flip-flop of the present invention;

Fig. 2 is the circuit theory diagrams and the symbol table diagrammatic sketch of first principal and subordinate's latch units in the JK flip-flop of the present invention;

Fig. 3 is the circuit theory diagrams and the symbol table diagrammatic sketch of the 3rd principal and subordinate's latch units in the JK flip-flop of the present invention;

Fig. 4 is the analog waveform of JK flip-flop of the present invention;

Fig. 5 is the energy consumption curve of JK flip-flop of the present invention.

Embodiment

Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.

As shown in Figure 1; A kind of JK flip-flop of defending energy attack; Comprise first mutual supplementary signal generation circuit 1, second mutual supplementary signal generation circuit 3, trigger prototype circuit 2, first principal and subordinate's latch units 4, second principal and subordinate's latch units 5, the 3rd principal and subordinate's latch units 6 and the 4th principal and subordinate's latch units 7; The first signal output part Q of trigger prototype circuit 2 is connected with first signal input part of first principal and subordinate's latch units 4; The secondary signal output Q of trigger prototype circuit 2 is connected with the secondary signal input of first principal and subordinate's latch units 4; First signal output part of first principal and subordinate's latch units 4 is connected with first signal input part of first mutual supplementary signal generation circuit 1; The secondary signal output of first principal and subordinate's latch units 4 is connected with the secondary signal input of first mutual supplementary signal generation circuit 1; The first signal output part x of first mutual supplementary signal generation circuit 1 is connected with first signal input part of the 3rd principal and subordinate's latch units 6; The secondary signal output x of first mutual supplementary signal generation circuit 1 is connected with the secondary signal input of the 3rd principal and subordinate's latch units 6; First signal output part of the 3rd principal and subordinate's latch units 6 is connected with first signal input part of trigger prototype circuit 2; The secondary signal output of the 3rd principal and subordinate's latch units 6 is connected with the secondary signal input of trigger prototype circuit 2; The first signal output part Q of trigger prototype circuit 2 is connected with the secondary signal input of second principal and subordinate's latch units 5; The secondary signal output Q of trigger prototype circuit 2 is connected with first signal input part of second principal and subordinate's latch units 5; First signal output part of second principal and subordinate's latch units 5 is connected with first signal input part of second mutual supplementary signal generation circuit 3; The secondary signal output of second principal and subordinate's latch units 5 is connected with the secondary signal input of second mutual supplementary signal generation circuit 3, and the first signal output part y of second mutual supplementary signal generation circuit 3 is connected with first signal input part of the 4th principal and subordinate's latch units 7, and the secondary signal output y of second mutual supplementary signal generation circuit 3 is connected with the secondary signal input of the 4th principal and subordinate's latch units 7; First signal output part of the 4th principal and subordinate's latch units 7 is connected with the 3rd signal input part of trigger prototype circuit 2, and the secondary signal output of the 4th principal and subordinate's latch units 7 is connected with the 4th signal input part of trigger prototype circuit 2.

First mutual supplementary signal generation circuit 1 is made up of PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, the 4th PMOS pipe P4, the 5th PMOS pipe P5, the 6th PMOS pipe P6, the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 9th PMOS pipe P9, NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the 4th NMOS pipe N4; The drain electrode of the one PMOS pipe P1 is connected with power positive end VDD; The drain electrode three of the drain electrode of the source electrode of the one PMOS pipe P1, the 2nd PMOS pipe P2 and the 3rd PMOS pipe P3 is connected; The grid of the 2nd PMOS pipe P2 is connected with the 3rd signal input part J of first mutual supplementary signal generation circuit 1; The grid of the 3rd PMOS pipe P3 is connected with the 4th signal input part J of first mutual supplementary signal generation circuit 1; The drain electrode three of the drain electrode of the source electrode of the 2nd PMOS pipe P2, the 4th PMOS pipe P4 and the 6th PMOS pipe P6 is connected; The drain electrode three of the drain electrode of the source electrode of the 3rd PMOS pipe P3, the 5th PMOS pipe P5 and the 7th PMOS pipe P7 is connected; The grid of the grid of the 4th PMOS pipe P4, the 5th PMOS pipe P5 all is connected with first signal input part of first mutual supplementary signal generation circuit 1; The drain electrode of the source electrode of the source electrode of the source electrode of the 4th PMOS pipe P4, the 6th PMOS pipe P6, the 7th PMOS pipe P7 and the 8th PMOS pipe P8 is connected; The grid of the grid of the 6th PMOS pipe P6, the 7th PMOS pipe P7 all is connected with the secondary signal input of first mutual supplementary signal generation circuit 1; The source electrode of the 5th PMOS pipe P5 is connected with the drain electrode of the 9th PMOS pipe P9; The grid of the grid of the drain electrode of the drain electrode of the source electrode of the 8th PMOS pipe P8, NMOS pipe N1, the 2nd NMOS pipe N2, the 9th PMOS pipe P9 and the 3rd NMOS pipe N3 all is connected with the first signal output part x of first mutual supplementary signal generation circuit 1; The drain electrode of the source electrode of the drain electrode of the grid of the grid of the 8th PMOS pipe P8, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 9th PMOS pipe P9 and the 4th NMOS pipe N4 all is connected with the secondary signal output x of first mutual supplementary signal generation circuit 1; The source grounding of the source electrode of the source electrode of the source electrode of the one NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the 4th NMOS pipe N4, the grid of the grid of PMOS pipe P1, NMOS pipe N1 and the grid of the 4th NMOS pipe N4 all are connected with clock signal input terminal clk.

Second mutual supplementary signal generation circuit 3 is made up of the tenth PMOS pipe P10, the 11 PMOS pipe P11, the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14, the 15 PMOS pipe P15, the 16 PMOS pipe P16, the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 5th NMOS pipe N5, the 6th NMOS pipe N6, the 7th NMOS pipe N7 and the 8th NMOS pipe N8; The drain electrode of the tenth PMOS pipe P10 is connected with power positive end VDD; The drain electrode three of the drain electrode of the source electrode of the tenth PMOS pipe P10, the 11 PMOS pipe P11 and the 12 PMOS pipe P12 is connected; The grid of the 11 PMOS pipe P11 is connected with the 3rd signal input part K of second mutual supplementary signal generation circuit 3; The grid of the 12 PMOS pipe P12 is connected with the 4th signal input part K of second mutual supplementary signal generation circuit 3; The drain electrode three of the drain electrode of the source electrode of the 11 PMOS pipe P11, the 13 PMOS pipe P13 and the 15 PMOS pipe P15 is connected; The drain electrode three of the drain electrode of the source electrode of the 12 PMOS pipe P12, the 14 PMOS pipe P14 and the 16 PMOS pipe P16 is connected; The grid of the grid of the 13 PMOS pipe P13, the 14 PMOS pipe P14 all is connected with first signal input part of second mutual supplementary signal generation circuit 3; The drain electrode of the source electrode of the source electrode of the source electrode of the 13 PMOS pipe P13, the 15 PMOS pipe P15, the 16 PMOS pipe P16 and the 17 PMOS pipe P17 is connected; The grid of the grid of the 15 PMOS pipe P15, the 16 PMOS pipe P16 all is connected with the secondary signal input of second mutual supplementary signal generation circuit 3; The source electrode of the 14 PMOS pipe P14 is connected with the drain electrode of the 18 PMOS pipe P18; The grid of the grid of the drain electrode of the drain electrode of the source electrode of the 17 PMOS pipe P17, the 5th NMOS pipe N5, the 6th NMOS pipe N6, the 18 PMOS pipe P18 and the 7th NMOS pipe N7 all is connected with the first signal output part y of second mutual supplementary signal generation circuit 3; The drain electrode of the source electrode of the drain electrode of the grid of the grid of the 17 PMOS pipe P17, the 6th NMOS pipe N6, the 7th NMOS pipe N7, the 18 PMOS pipe P18 and the 8th NMOS pipe N8 all is connected with the secondary signal output y of second mutual supplementary signal generation circuit 3; The source grounding of the source electrode of the source electrode of the source electrode of the 5th NMOS pipe N5, the 6th NMOS pipe N6, the 7th NMOS pipe N7 and the 8th NMOS pipe N8, the grid of the grid of the tenth PMOS pipe P10, the 5th NMOS pipe N5 and the grid of the 8th NMOS pipe N8 all are connected with clock signal input terminal clk.

Trigger prototype circuit 2 is made up of the 19 PMOS pipe P19, the 20 PMOS pipe P20, the 21 PMOS pipe P21, the 22 PMOS pipe P22, the 9th NMOS pipe N9, the tenth NMOS pipe N10, the 11 NMOS pipe N11, the 12 NMOS pipe N12, the 13 NMOS pipe N13, the 14 NMOS pipe N14, the 15 NMOS pipe N15, the 16 NMOS pipe N16 and the 17 NMOS pipe N17; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the 19 PMOS pipe P19, the 20 PMOS pipe P20, the 21 PMOS pipe P21 and the 22 PMOS pipe P22 all is connected with power positive end VDD; The source electrode of the drain electrode of the source electrode of the grid of the grid of the 20 PMOS pipe P20, the 9th NMOS pipe N9, the 21 PMOS pipe P21, the tenth NMOS pipe N10 and the 22 PMOS pipe P22 all is connected with the first signal output part Q of trigger prototype circuit 2; The grid of the grid of the drain electrode of the source electrode of the source electrode of the 19 PMOS pipe P19, the 20 PMOS pipe P20, the 9th NMOS pipe N9, the 21 PMOS pipe P21 and the tenth NMOS pipe N10 all is connected with the secondary signal output Q of trigger prototype circuit 2; The drain electrode of the drain electrode of the drain electrode of the source electrode of the 9th NMOS pipe N9, the 13 NMOS pipe N13, the 11 NMOS pipe N11 and the 14 NMOS pipe N14 is connected; The source electrode of the tenth NMOS pipe N10 is connected with the drain electrode of the 12 NMOS pipe N12; The grid of the grid of the 11 NMOS pipe N11, the 12 NMOS pipe N12 all is connected with first signal input part of trigger prototype circuit 2; The grid of the grid of the 13 NMOS pipe N13, the 14 NMOS pipe N14 all is connected with the secondary signal input of trigger prototype circuit 2; The drain electrode three of the source electrode of the source electrode of the 11 NMOS pipe N11, the 13 NMOS pipe N13 and the 15 NMOS pipe N15 is connected; The drain electrode three of the source electrode of the source electrode of the 12 NMOS pipe N12, the 14 NMOS pipe N14 and the 16 NMOS pipe N16 is connected; The drain electrode three of the source electrode of the source electrode of the 15 NMOS pipe N15, the 16 NMOS pipe N16 and the 17 NMOS pipe N17 is connected; The grid of the 16 NMOS pipe N16 is connected with the 3rd signal input part of trigger prototype circuit 2; The grid of the 15 NMOS pipe N15 is connected with the 4th signal input part of trigger prototype circuit 2; The source ground of the 17 NMOS pipe N17, the grid of the grid of the 17 NMOS pipe N17, the 19 PMOS pipe P19 and the grid of the 22 PMOS pipe P22 all are connected with clock signal input terminal clk.

First principal and subordinate's latch units 4 is identical with the internal structure of second principal and subordinate's latch units 5; As shown in Figure 2; First principal and subordinate's latch units 4 is made up of from latch cicuit 9 first main latch circuit 8 and first; First main latch circuit 8 is made up of the 23 PMOS pipe P23, the 24 PMOS pipe P24, the 25 PMOS pipe P25, the 26 PMOS pipe P26, the 18 NMOS pipe N18, the 19 NMOS pipe N19, the 20 NMOS pipe N20, the 21 NMOS pipe N21 and the 22 NMOS pipe N22; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the 23 PMOS pipe P23, the 24 PMOS pipe P24, the 25 PMOS pipe P25 and the 26 PMOS pipe P26 all is connected with power positive end VDD; The source electrode of the drain electrode of the source electrode of the grid of the grid of the 24 PMOS pipe P24, the 18 NMOS pipe N18, the 25 PMOS pipe P25, the 19 NMOS pipe N19 and the 26 PMOS pipe P26 all is connected with the first signal output part out1 of first main latch circuit 8, the grid that the source electrode of the source electrode of the 23 PMOS pipe P23, the 24 PMOS pipe P24, the drain electrode of the 18 NMOS pipe N18, grid that the 25 PMOS manages P25 and the 19 NMOS manage N19 all with the secondary signal output of first main latch circuit 8

Be connected, the source electrode of the 18 NMOS pipe N18 is connected with the drain electrode of the 20 NMOS pipe N20, the grid of the 20 NMOS pipe N20 and first signal input part of first principal and subordinate's latch units 4

Be connected, the source electrode of the 19 NMOS pipe N19 is connected with the drain electrode of the 21 NMOS pipe N21, the grid of the 21 NMOS pipe N21 and the secondary signal input Q of first principal and subordinate's latch units 4 ⁿBe connected; The drain electrode three of the source electrode of the source electrode of the 20 NMOS pipe N20, the 21 NMOS pipe N21 and the 22 NMOS pipe N22 is connected; The source ground of the 22 NMOS pipe N22; The grid of the grid of the grid of the 22 NMOS pipe N22, the 23 PMOS pipe P23 and the 26 PMOS pipe P26 all is connected with clock signal input terminal clk; First manages P31, the 23 NMOS pipe N23, the 24 NMOS pipe N24, the 25 NMOS pipe N25 and the 26 NMOS pipe N26 from latch cicuit 9 by the 27 PMOS pipe P27, the 28 PMOS pipe P28, the 29 PMOS pipe P29, the 30 PMOS pipe P30, the 31 PMOS forms; The drain electrode of the 27 PMOS pipe P27 is connected with power positive end VDD; The drain electrode three of the drain electrode of the source electrode of the 27 PMOS pipe P27, the 28 PMOS pipe P28 and the 29 PMOS pipe P29 is connected; The grid of the 28 PMOS pipe P28 is connected with the first first signal input part in1 from latch cicuit 9, the grid and the first secondary signal input from latch cicuit 9 of the 29 PMOS pipe P29 Connect; The source electrode of the 28 PMOS pipe P28 is connected with the drain electrode of the 30 PMOS pipe P30; The source electrode of the 29 PMOS pipe P29 is connected with the drain electrode of the 31 PMOS pipe P31, the drain electrode of the grid of the grid of the 30 PMOS pipe P30, the 24 NMOS pipe N24, the source electrode of the 31 PMOS pipe P31, the 25 NMOS pipe N25 and the drain electrode that the 26 NMOS manages N26 all with first signal output part of first principal and subordinate's latch units 4

Be connected; The grid of the grid of the drain electrode of the drain electrode of the source electrode of the 30 PMOS pipe P30, the 23 NMOS pipe N23, the 24 NMOS pipe N24, the 31 PMOS pipe P31 and the 25 NMOS pipe N25 all is connected with the secondary signal output out2 of first principal and subordinate's latch units 4; The source grounding of the source electrode of the source electrode of the source electrode of the 23 NMOS pipe N23, the 24 NMOS pipe N24, the 25 NMOS pipe N25 and the 26 NMOS pipe N26; The grid of the grid of the grid of the 23 NMOS pipe N23, the 26 NMOS pipe N26 and the 27 PMOS pipe P27 all is connected with clock signal input terminal clk; The first signal output part out1 of first main latch circuit 8 is connected the secondary signal output of first main latch circuit 8 with the first first signal input part in1 from latch cicuit 9 With first the secondary signal input from latch cicuit 9

Be connected.

The 3rd principal and subordinate's latch units 6 is identical with the internal structure of the 4th principal and subordinate's latch units 7; As shown in Figure 3; The 3rd principal and subordinate's latch units 6 is made up of from latch cicuit 11 second main latch circuit 10 and second; Second main latch circuit 10 is made up of the 32 PMOS pipe P32, the 33 PMOS pipe P33, the 34 PMOS pipe P34, the 35 PMOS pipe P35, the 36 PMOS pipe P36, the 27 NMOS pipe N27, the 28 NMOS pipe N28, the 29 NMOS pipe N29 and the 30 NMOS pipe N30; The drain electrode of the 32 PMOS pipe P32 is connected with power positive end VDD; The drain electrode three of the drain electrode of the source electrode of the 32 PMOS pipe P32, the 33 PMOS pipe P33 and the 34 PMOS pipe P34 is connected; The grid of the 33 PMOS pipe P33 is connected with the first signal input part x of the 3rd principal and subordinate's latch units 6; The grid of the 34 PMOS pipe P34 is connected with the secondary signal input y of the 3rd principal and subordinate's latch units 6; The source electrode of the 33 PMOS pipe P33 is connected with the drain electrode of the 35 PMOS pipe P35; The source electrode of the 34 PMOS pipe P34 is connected with the drain electrode of the 36 PMOS pipe P36; The drain electrode of the drain electrode of the source electrode of the grid of the grid of the 35 PMOS pipe P35, the 28 NMOS pipe N28, the 36 PMOS pipe P36, the 29 NMOS pipe N29 and the 30 NMOS pipe N30 all is connected with the first signal output part out3 of second main latch circuit 10, and the grid of the drain electrode of the source electrode of the 35 PMOS pipe P35, the 27 NMOS pipe N27, the drain electrode of the 28 NMOS pipe N28, the 36 PMOS pipe P36 and the grid of the 29 NMOS pipe N29 all are connected with the secondary signal output

of second main latch circuit 10, the source grounding of the source electrode of the source electrode of the 27 NMOS pipe N27, the 28 NMOS pipe N28, the source electrode of the 29 NMOS pipe N29 and the 30 NMOS pipe N30; The grid of the grid of the grid of the 27 NMOS pipe N27, the 30 NMOS pipe N30 and the 32 PMOS pipe P32 all is connected with clock signal input terminal clk; Second manages N31, the 32 NMOS pipe N32, the 33 NMOS pipe N33, the 34 NMOS pipe N34 and the 35 NMOS pipe N35 from latch cicuit 11 by the 37 PMOS pipe P37, the 38 PMOS pipe P38, the 39 PMOS pipe P39, the 40 PMOS pipe P40, the 31 NMOS forms, and the 37 PMOS manages the drain electrode of P37, the drain electrode of the 38 PMOS pipe P38, the drain electrode of the 39 PMOS pipe P39 and the drain electrode of the 40 PMOS pipe P40 and all is connected with power positive end VDD, and the source electrode of the source electrode of the grid that the grid of the 38 PMOS pipe P38, the 31 NMOS manage N31, the 39 PMOS pipe P39, the drain electrode of the 32 NMOS pipe N32 and the 40 PMOS pipe P40 all is connected with the first signal output part out4 of the 3rd principal and subordinate's latch units 6; The grid of the grid of the drain electrode of the source electrode of the source electrode of the 37 PMOS pipe P37, the 38 PMOS pipe P38, the 31 NMOS pipe N31, the 39 PMOS pipe P39 and the 32 NMOS pipe N32 all is connected with the secondary signal output

of the 3rd principal and subordinate's latch units 6; The source electrode of the 31 NMOS pipe N31 is connected with the drain electrode of the 33 NMOS pipe N33, and the grid of the 33 NMOS pipe N33 is connected with the second first signal input part in2 from latch cicuit 11, and the source electrode of the 32 NMOS pipe N32 is connected with the drain electrode of the 34 NMOS pipe N34; The grid of the 34 NMOS pipe N34 is connected with the second secondary signal input from latch cicuit 11

; The drain electrode three of the source electrode of the source electrode of the 33 NMOS pipe N33, the 34 NMOS pipe N34 and the 35 NMOS pipe N35 is connected, the source ground of the 35 NMOS pipe N35, and the grid of the grid of the 35 NMOS pipe N35, the 37 PMOS pipe P37 and the grid of the 40 PMOS pipe P40 all are connected with clock signal input terminal clk; The first signal output part out3 of second main latch circuit 10 is connected with the second first signal input part in2 from latch cicuit 11, and the secondary signal output of second main latch circuit 10

is connected with the second secondary signal input from latch cicuit 11

.

P26 is fast than the 23 PMOS pipe P23, the 26 PMOS pipe for the turn-on rate of the 27 PMOS pipe P27 described in the foregoing description; Promptly the breadth length ratio of the 27 PMOS pipe P27 is greater than the breadth length ratio of the 23 PMOS pipe P23, the 26 PMOS pipe P26; N30 is fast than the 27 NMOS pipe N27, the 30 NMOS pipe for the turn-on rate of described the 35 NMOS pipe N35, and promptly the breadth length ratio of the 35 NMOS pipe N35 is greater than the breadth length ratio of the 27 NMOS pipe N27, the 30 NMOS pipe N30.

The course of work of JK flip-flop of the present invention: when clock signal clk=0, trigger prototype circuit 2 gets into the preliminary filling stage, the first signal output part Q and the secondary signal output of trigger prototype circuit 2

All be changed to 1; The complementary signal Q of first principal and subordinate's latch units 4 and second principal and subordinate's latch units, 5 output internal reservoir ⁿWith And with signal Q ⁿBe sent to first signal input part of first mutual supplementary signal generation circuit 1 and the secondary signal input of second mutual supplementary signal generation circuit 3, with complementary signal Be sent to the secondary signal input of first mutual supplementary signal generation circuit 1 and first signal input part of second mutual supplementary signal generation circuit 3; First mutual supplementary signal generation circuit 1 and second mutual supplementary signal generation circuit 3 get into evaluate phase, all carry out and/NOT-AND operation first signal output part output complementary signal of first mutual supplementary signal generation circuit 1

The secondary signal output output signal x of first mutual supplementary signal generation circuit 1, first signal output part output complementary signal of second mutual supplementary signal generation circuit 3

The secondary signal output output signal y of second mutual supplementary signal generation circuit 3; The 3rd principal and subordinate's latch units 6 receive complementary signal x with

And it is temporarily stored in device cell inside; The 4th principal and subordinate's latch units 7 receive complementary signal y with

And it is temporarily stored in device cell inside; When clock signal clk=1, first mutual supplementary signal generation circuit 1 and second mutual supplementary signal generation circuit 3 get into the preliminary filling stage, and output all is changed to low level 0 state; The complementary signal x of the 3rd principal and subordinate's latch units 6 output internal reservoir with

The complementary signal y of the 4th principal and subordinate's latch units 7 output internal reservoir with

And signal x is sent to the secondary signal input of trigger prototype circuit 2, with complementary signal

Be sent to first signal input part of trigger prototype circuit 2, signal y be sent to the 4th signal input part of trigger prototype circuit 2, complementary signal Be sent to the 3rd signal input part of trigger prototype circuit 2; Trigger prototype circuit 2 gets into evaluate phase, carry out or/NOR operation, the first signal output part Q and secondary signal output

Output complementary signal Q ^N+1With

The complementary signal Q of first principal and subordinate's latch units 4 and 5 receptions of second principal and subordinate's latch units and 2 outputs of temporary trigger prototype circuit ^N+1With

Under the HSPICE environment; Adopt PTM 90nm CMOS technology device parameters; Above-mentioned described JK flip-flop is carried out Computer Simulation; Wherein the 27 PMOS pipe P27 breadth length ratio is 1.35um/0.09um, and the 23 PMOS pipe P23, the 26 PMOS pipe P26 breadth length ratio are 0.09um/0.09um; The 35 NMOS pipe N35 breadth length ratio is 0.9um/0.09um; The 27 NMOS pipe N27, the 30 NMOS pipe N30 breadth length ratio are 0.09um/0.09um; Other NMOS pipe breadth length ratio is all got 0.36um/0.09um, and other PMOS pipe breadth length ratio is all got 0.72um/0.09um.Fig. 4 has provided the analog waveform of this trigger; Wherein input signal J and K are respectively " 10101010... " and " 00110011... "; Operating frequency is 50MHz; Load capacitance is 10fF; Analysis shows that if clk is a low level, trigger output Q and

all are changed to 1; Otherwise when clk was high level, this circuit had the maintenance function when J=0, K=0; When J=0, K=1, have and put 0 function; When J=1, K=0, have and put 1 function; When J=1, K=1, has turn over function.The result is consistent with table 1, proves that the circuit that designs has correct logic functions.Fig. 5 has provided the power consumption curve of this trigger, and the result shows this design at different clocks in the cycle, and the power consumption curve is consistent, has the power consumption permanent character.

Table 1: the state transitions truth table of JK flip-flop of the present invention

Table 2: average energy consumption contrasts (unit: 10-14J) in the present invention and traditional JK flip-flop cycle

JK flip-flop of the present invention and traditional JK flip-flop are compared, reflect the resisting differential energy attack performance of circuit with the difference of different clocks average energy consumption in the cycle, computer artificial result is as shown in table 2.Wherein Eneri (i=1-8) is the average energy consumption of circuit in i clock cycle;

Be the average energy consumption of circuit in eight clock cycle, σ _EMean square deviation for different clocks average energy consumption in the cycle.Second row shows in the table 2; When traditional JK flip-flop when different clocks is handled different pieces of information in the cycle, average energy consumption is not quite similar, in preceding four clock cycle; Average energy consumption is maximum in the 3rd clock cycle; Analyzing the function of JK flip-flop can know, this moment, trigger had turn over function, this shows that there is correlation in the data of its energy consumption and processing.If with the part of traditional JK flip-flop as cryptographic system, energy consumption when working through register system adopts the differential power attack technology, can analyze the information of cryptographic system protection.The third line shows in the table, the average energy consumption basically identical of JK flip-flop of the present invention in each clock cycle, and promptly it has the separate characteristics of data of energy consumption and processing.

The normalization standard deviation (Normalized Standard Deviation is a working standard of weighing circuit resisting differential energy attack performance NSD), and it is defined as:

$\mathrm{NSD}=\frac{{\mathrm{\σ}}_E}{\stackrel{\‾}{E}}$

Thereby can calculate JK flip-flop of the present invention and traditional JK flip-flop normalization standard deviation is respectively 0.6% and 43.8%.Than traditional design, the normalization standard deviation of this design is merely the former 1/73 (0.6%/43.8%), proves that its defence energy attack performance is remarkable.

Claims (6)

1. JK flip-flop of defending energy attack; It is characterized in that comprising first mutual supplementary signal generation circuit, second mutual supplementary signal generation circuit, trigger prototype circuit, first principal and subordinate's latch units, second principal and subordinate's latch units, the 3rd principal and subordinate's latch units and the 4th principal and subordinate's latch units; First signal output part of described trigger prototype circuit is connected with first signal input part of described first principal and subordinate's latch units; The secondary signal output of described trigger prototype circuit is connected with the secondary signal input of described first principal and subordinate's latch units; First signal output part of described first principal and subordinate's latch units is connected with first signal input part of described first mutual supplementary signal generation circuit; The secondary signal output of described first principal and subordinate's latch units is connected with the secondary signal input of described first mutual supplementary signal generation circuit; First signal output part of described first mutual supplementary signal generation circuit is connected with first signal input part of described the 3rd principal and subordinate's latch units; The secondary signal output of described first mutual supplementary signal generation circuit is connected with the secondary signal input of described the 3rd principal and subordinate's latch units; First signal output part of described the 3rd principal and subordinate's latch units is connected with first signal input part of described trigger prototype circuit; The secondary signal output of described the 3rd principal and subordinate's latch units is connected with the secondary signal input of described trigger prototype circuit; First signal output part of described trigger prototype circuit is connected with the secondary signal input of described second principal and subordinate's latch units; The secondary signal output of described trigger prototype circuit is connected with first signal input part of described second principal and subordinate's latch units; First signal output part of described second principal and subordinate's latch units is connected with first signal input part of described second mutual supplementary signal generation circuit; The secondary signal output of described second principal and subordinate's latch units is connected with the secondary signal input of described second mutual supplementary signal generation circuit; First signal output part of described second mutual supplementary signal generation circuit is connected with first signal input part of described the 4th principal and subordinate's latch units; The secondary signal output of described second mutual supplementary signal generation circuit is connected with the secondary signal input of described the 4th principal and subordinate's latch units; First signal output part of described the 4th principal and subordinate's latch units is connected with the 3rd signal input part of described trigger prototype circuit, and the secondary signal output of described the 4th principal and subordinate's latch units is connected with the 4th signal input part of described trigger prototype circuit.

2. a kind of JK flip-flop of defending energy attack according to claim 1; It is characterized in that described first mutual supplementary signal generation circuit by a PMOS manage, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 7th PMOS pipe, the 8th PMOS pipe, the 9th PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe form; The drain electrode of described PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described PMOS pipe, described the 2nd PMOS pipe and described the 3rd PMOS pipe is connected; The grid of described the 2nd PMOS pipe is connected with the 3rd signal input part of described first mutual supplementary signal generation circuit; The grid of described the 3rd PMOS pipe is connected with the 4th signal input part of described first mutual supplementary signal generation circuit; The drain electrode three of the drain electrode of the source electrode of described the 2nd PMOS pipe, described the 4th PMOS pipe and described the 6th PMOS pipe is connected; The drain electrode three of the drain electrode of the source electrode of described the 3rd PMOS pipe, described the 5th PMOS pipe and described the 7th PMOS pipe is connected; The grid of the grid of described the 4th PMOS pipe, described the 5th PMOS pipe all is connected with first signal input part of described first mutual supplementary signal generation circuit; The drain electrode of the source electrode of the source electrode of the source electrode of described the 4th PMOS pipe, described the 6th PMOS pipe, described the 7th PMOS pipe and described the 8th PMOS pipe is connected; The grid of the grid of described the 6th PMOS pipe, described the 7th PMOS pipe all is connected with the secondary signal input of described first mutual supplementary signal generation circuit; The source electrode of described the 5th PMOS pipe is connected with the drain electrode of described the 9th PMOS pipe; The grid of the grid of the drain electrode of the drain electrode of the source electrode of described the 8th PMOS pipe, described NMOS pipe, described the 2nd NMOS pipe, described the 9th PMOS pipe and described the 3rd NMOS pipe all is connected with first signal output part of described first mutual supplementary signal generation circuit; The drain electrode of the source electrode of the drain electrode of the grid of the grid of described the 8th PMOS pipe, described the 2nd NMOS pipe, described the 3rd NMOS pipe, described the 9th PMOS pipe and described the 4th NMOS pipe all is connected with the secondary signal output of described first mutual supplementary signal generation circuit; The source grounding of the source electrode of the source electrode of the source electrode of described NMOS pipe, described the 2nd NMOS pipe, described the 3rd NMOS pipe and described the 4th NMOS pipe, the grid of the grid of described PMOS pipe, described NMOS pipe and the grid of described the 4th NMOS pipe all are connected with clock signal input terminal.

3. a kind of JK flip-flop of defending energy attack according to claim 1; It is characterized in that described second mutual supplementary signal generation circuit by the tenth PMOS manage, the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe, the 15 PMOS pipe, the 16 PMOS pipe, the 17 PMOS pipe, the 18 PMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe form; The drain electrode of described the tenth PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described the tenth PMOS pipe, described the 11 PMOS pipe and described the 12 PMOS pipe is connected; The grid of described the 11 PMOS pipe is connected with the 3rd signal input part of described second mutual supplementary signal generation circuit; The grid of described the 12 PMOS pipe is connected with the 4th signal input part of described second mutual supplementary signal generation circuit; The drain electrode three of the drain electrode of the source electrode of described the 11 PMOS pipe, described the 13 PMOS pipe and described the 15 PMOS pipe is connected; The drain electrode three of the drain electrode of the source electrode of described the 12 PMOS pipe, described the 14 PMOS pipe and described the 16 PMOS pipe is connected; The grid of the grid of described the 13 PMOS pipe, described the 14 PMOS pipe all is connected with first signal input part of described second mutual supplementary signal generation circuit; The drain electrode of the source electrode of the source electrode of the source electrode of described the 13 PMOS pipe, described the 15 PMOS pipe, described the 16 PMOS pipe and described the 17 PMOS pipe is connected; The grid of the grid of described the 15 PMOS pipe, described the 16 PMOS pipe all is connected with the secondary signal input of described second mutual supplementary signal generation circuit; The source electrode of described the 14 PMOS pipe is connected with the drain electrode of described the 18 PMOS pipe; The grid of the grid of the drain electrode of the drain electrode of the source electrode of described the 17 PMOS pipe, described the 5th NMOS pipe, described the 6th NMOS pipe, described the 18 PMOS pipe and described the 7th NMOS pipe all is connected with first signal output part of described second mutual supplementary signal generation circuit; The drain electrode of the source electrode of the drain electrode of the grid of the grid of described the 17 PMOS pipe, described the 6th NMOS pipe, described the 7th NMOS pipe, described the 18 PMOS pipe and described the 8th NMOS pipe all is connected with the secondary signal output of described second mutual supplementary signal generation circuit; The source grounding of the source electrode of the source electrode of the source electrode of described the 5th NMOS pipe, described the 6th NMOS pipe, described the 7th NMOS pipe and described the 8th NMOS pipe, the grid of the grid of described the tenth PMOS pipe, described the 5th NMOS pipe and the grid of described the 8th NMOS pipe all are connected with clock signal input terminal.

4. a kind of JK flip-flop of defending energy attack according to claim 1; It is characterized in that described trigger prototype circuit is made up of the 19 PMOS pipe, the 20 PMOS pipe, the 21 PMOS pipe, the 22 PMOS pipe, the 9th NMOS pipe, the tenth NMOS pipe, the 11 NMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 19 PMOS pipe, described the 20 PMOS pipe, described the 21 PMOS pipe and described the 22 PMOS pipe all is connected with power positive end; The source electrode of the drain electrode of the source electrode of the grid of the grid of described the 20 PMOS pipe, described the 9th NMOS pipe, described the 21 PMOS pipe, described the tenth NMOS pipe and described the 22 PMOS pipe all is connected with first signal output part of described trigger prototype circuit; The grid of the grid of the drain electrode of the source electrode of the source electrode of described the 19 PMOS pipe, described the 20 PMOS pipe, described the 9th NMOS pipe, described the 21 PMOS pipe and described the tenth NMOS pipe all is connected with the secondary signal output of described trigger prototype circuit; The drain electrode of the drain electrode of the drain electrode of the source electrode of described the 9th NMOS pipe, described the 13 NMOS pipe, described the 11 NMOS pipe and described the 14 NMOS pipe is connected; The source electrode of described the tenth NMOS pipe is connected with the drain electrode of described the 12 NMOS pipe; The grid of the grid of described the 11 NMOS pipe, described the 12 NMOS pipe all is connected with first signal input part of described trigger prototype circuit; The grid of the grid of described the 13 NMOS pipe, described the 14 NMOS pipe all is connected with the secondary signal input of described trigger prototype circuit; The drain electrode three of the source electrode of the source electrode of described the 11 NMOS pipe, described the 13 NMOS pipe and described the 15 NMOS pipe is connected; The drain electrode three of the source electrode of the source electrode of described the 12 NMOS pipe, described the 14 NMOS pipe and described the 16 NMOS pipe is connected; The drain electrode three of the source electrode of the source electrode of described the 15 NMOS pipe, described the 16 NMOS pipe and described the 17 NMOS pipe is connected; The grid of described the 16 NMOS pipe is connected with the 3rd signal input part of described trigger prototype circuit; The grid of described the 15 NMOS pipe is connected with the 4th signal input part of described trigger prototype circuit; The source ground of described the 17 NMOS pipe, the grid of the grid of described the 17 NMOS pipe, described the 19 PMOS pipe and the grid of described the 22 PMOS pipe all are connected with clock signal input terminal.

5. a kind of JK flip-flop of defending energy attack according to claim 1; It is characterized in that described first principal and subordinate's latch units is identical with the internal structure of described second principal and subordinate's latch units; Described first principal and subordinate's latch units is made up of from latch cicuit first main latch circuit and first; Described first main latch circuit is made up of the 23 PMOS pipe, the 24 PMOS pipe, the 25 PMOS pipe, the 26 PMOS pipe, the 18 NMOS pipe, the 19 NMOS pipe, the 20 NMOS pipe, the 21 NMOS pipe and the 22 NMOS pipe; The drain electrode of the drain electrode of the drain electrode of the drain electrode of described the 23 PMOS pipe, described the 24 PMOS pipe, described the 25 PMOS pipe and described the 26 PMOS pipe all is connected with power positive end; The source electrode of the drain electrode of the source electrode of the grid of the grid of described the 24 PMOS pipe, described the 18 NMOS pipe, described the 25 PMOS pipe, described the 19 NMOS pipe and described the 26 PMOS pipe all is connected with first signal output part of described first main latch circuit; The grid of the grid of the drain electrode of the source electrode of the source electrode of described the 23 PMOS pipe, described the 24 PMOS pipe, described the 18 NMOS pipe, described the 25 PMOS pipe and described the 19 NMOS pipe all is connected with the secondary signal output of described first main latch circuit; The source electrode of described the 18 NMOS pipe is connected with the drain electrode of described the 20 NMOS pipe; The grid of described the 20 NMOS pipe is connected with first signal input part of described first principal and subordinate's latch units; The source electrode of described the 19 NMOS pipe is connected with the drain electrode of described the 21 NMOS pipe; The grid of described the 21 NMOS pipe is connected with the secondary signal input of described first principal and subordinate's latch units, and the source electrode of the source electrode of described the 20 NMOS pipe, described the 21 NMOS pipe and the drain electrode three of described the 22 NMOS pipe are connected the source ground of described the 22 NMOS pipe; The grid of the grid of the grid of described the 22 NMOS pipe, described the 23 PMOS pipe and described the 26 PMOS pipe all is connected with clock signal input terminal; Described first is made up of the 27 PMOS pipe, the 28 PMOS pipe, the 29 PMOS pipe, the 30 PMOS pipe, the 31 PMOS pipe, the 23 NMOS pipe, the 24 NMOS pipe, the 25 NMOS pipe and the 26 NMOS pipe from latch cicuit, and the drain electrode of described the 27 PMOS pipe is connected with power positive end, and the drain electrode three that drain electrode that the source electrode of described the 27 PMOS pipe, described the 28 PMOS manage and described the 29 PMOS manage is connected; The grid of described the 28 PMOS pipe is connected with described first first signal input part from latch cicuit; The grid of described the 29 PMOS pipe is connected with the described first secondary signal input from latch cicuit, and the source electrode of described the 28 PMOS pipe is connected with the drain electrode of described the 30 PMOS pipe, and the source electrode of described the 29 PMOS pipe is connected with the drain electrode of described the 31 PMOS pipe; The drain electrode of the drain electrode of the source electrode of the grid of the grid of described the 30 PMOS pipe, described the 24 NMOS pipe, described the 31 PMOS pipe, described the 25 NMOS pipe and described the 26 NMOS pipe all is connected with first signal output part of described first principal and subordinate's latch units; The grid of the grid of the drain electrode of the drain electrode of the source electrode of described the 30 PMOS pipe, described the 23 NMOS pipe, described the 24 NMOS pipe, described the 31 PMOS pipe and described the 25 NMOS pipe all is connected with the secondary signal output of described first principal and subordinate's latch units, the source electrode of the source electrode of described the 23 NMOS pipe, the source electrode of described the 24 NMOS pipe, described the 25 NMOS pipe and the source grounding of described the 26 NMOS pipe, and the grid of the grid of described the 23 NMOS pipe, described the 26 NMOS pipe and the grid of described the 27 PMOS pipe all are connected with clock signal input terminal; First signal output part of described first main latch circuit is connected with described first first signal input part from latch cicuit, and the secondary signal output of described first main latch circuit is connected with the described first secondary signal input from latch cicuit.

6. a kind of JK flip-flop of defending energy attack according to claim 1; It is characterized in that described the 3rd principal and subordinate's latch units is identical with the internal structure of described the 4th principal and subordinate's latch units; Described the 3rd principal and subordinate's latch units is made up of from latch cicuit second main latch circuit and second; Described second main latch circuit is made up of the 32 PMOS pipe, the 33 PMOS pipe, the 34 PMOS pipe, the 35 PMOS pipe, the 36 PMOS pipe, the 27 NMOS pipe, the 28 NMOS pipe, the 29 NMOS pipe and the 30 NMOS pipe; The drain electrode of described the 32 PMOS pipe is connected with power positive end; The drain electrode three of the drain electrode of the source electrode of described the 32 PMOS pipe, described the 33 PMOS pipe and described the 34 PMOS pipe is connected; The grid of described the 33 PMOS pipe is connected with first signal input part of described the 3rd principal and subordinate's latch units; The grid of described the 34 PMOS pipe is connected with the secondary signal input of described the 3rd principal and subordinate's latch units; The source electrode of described the 33 PMOS pipe is connected with the drain electrode of described the 35 PMOS pipe; The source electrode of described the 34 PMOS pipe is connected with the drain electrode of described the 36 PMOS pipe; The drain electrode of the drain electrode of the source electrode of the grid of the grid of described the 35 PMOS pipe, described the 28 NMOS pipe, described the 36 PMOS pipe, described the 29 NMOS pipe and described the 30 NMOS pipe all is connected with first signal output part of described second main latch circuit, and the grid of the source electrode of described the 35 PMOS pipe, the drain electrode of described the 27 NMOS pipe, the drain electrode of described the 28 NMOS pipe, described the 36 PMOS pipe and the grid of described the 29 NMOS pipe all are connected with the secondary signal output of described second main latch circuit, the source electrode of the source electrode of described the 27 NMOS pipe, the source electrode of described the 28 NMOS pipe, described the 29 NMOS pipe and the source grounding of described the 30 NMOS pipe; The grid of the grid of the grid of described the 27 NMOS pipe, described the 30 NMOS pipe and described the 32 PMOS pipe all is connected with clock signal input terminal; Described second is made up of the 37 PMOS pipe, the 38 PMOS pipe, the 39 PMOS pipe, the 40 PMOS pipe, the 31 NMOS pipe, the 32 NMOS pipe, the 33 NMOS pipe, the 34 NMOS pipe and the 35 NMOS pipe from latch cicuit, and the drain electrode of the drain electrode of described the 37 PMOS pipe, the drain electrode of described the 38 PMOS pipe, described the 39 PMOS pipe and the drain electrode of described the 40 PMOS pipe all are connected with power positive end, and the source electrode that the source electrode that the grid of described the 38 PMOS pipe, the grid of described the 31 NMOS pipe, described the 39 PMOS manage, the drain electrode that described the 32 NMOS manages and described the 40 PMOS manage all is connected with first signal output part of described the 3rd principal and subordinate's latch units; The grid of the grid of the drain electrode of the source electrode of the source electrode of described the 37 PMOS pipe, described the 38 PMOS pipe, described the 31 NMOS pipe, described the 39 PMOS pipe and described the 32 NMOS pipe all is connected with the secondary signal output of described the 3rd principal and subordinate's latch units; The source electrode of described the 31 NMOS pipe is connected with the drain electrode of described the 33 NMOS pipe, and the grid of described the 33 NMOS pipe is connected with described second first signal input part from latch cicuit, and the source electrode of described the 32 NMOS pipe is connected with the drain electrode of described the 34 NMOS pipe; The grid of described the 34 NMOS pipe is connected with the described second secondary signal input from latch cicuit; The drain electrode three of the source electrode of the source electrode of described the 33 NMOS pipe, described the 34 NMOS pipe and described the 35 NMOS pipe is connected, the source ground of described the 35 NMOS pipe, and the grid of the grid of described the 35 NMOS pipe, described the 37 PMOS pipe and the grid of described the 40 PMOS pipe all are connected with clock signal input terminal; First signal output part of described second main latch circuit is connected with described second first signal input part from latch cicuit, and the secondary signal output of described second main latch circuit is connected with the described second secondary signal input from latch cicuit.

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