CN102394106B - Programmable double-level converter based on phase change storage unit and implementation method thereof - Google Patents
Programmable double-level converter based on phase change storage unit and implementation method thereof Download PDFInfo
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- CN102394106B CN102394106B CN201110331505.2A CN201110331505A CN102394106B CN 102394106 B CN102394106 B CN 102394106B CN 201110331505 A CN201110331505 A CN 201110331505A CN 102394106 B CN102394106 B CN 102394106B
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Abstract
The invention discloses a programmable double-level converter based on a phase change storage unit and an implementation method thereof. The programmable double-level converter based on the phase change storage unit comprises a level conversion circuit and four conversion voltage control circuits, wherein the level conversion circuit is connected with outputs of the conversion voltage control circuits; the conversion voltage control circuits control a high level and a low level which are output to the level conversion circuit; and conversion of a high level signal and a low level signal as well as control of an output level are realized according to an input signal input into the level conversion circuit and voltages output by the conversion voltage control circuits. The double-level converter is high in integration degree and has functions of programming and continuously adjusting the voltage.
Description
Technical field
The present invention relates to a kind of level translator that regulates electric variable, especially relate to a kind of able to programme pair of voltage level shifter and its implementation based on phase-change memory cell.
Background technology
In design of electronic circuits of new generation, along with the introducing of low logic voltage, usually there is the inharmonic problem of I/O logic in internal system, thereby improved the complicacy of system.For example, in the time that the digital circuit of 1. 1V communicates with the mimic channel that is operated in 3. 3V, need to first solve the transfer problem of two kinds of level, at this moment just need level translator.
Along with continuing to bring out of the various integrated circuit of different operating voltage, the raising of chip integration, technique is constantly progressive.The necessity of logic level transition is more outstanding, and level conversion mode also changes the difference of the form with logic voltage, data bus and message transmission rate.Although now many logic chips can realize higher logic level to compared with the conversion of low logic level (as by 5V level conversion to 3V level), rarely logic circuit chip lower logic level transition can be become higher logic level (as by 3V logical transition to 5V logic).In addition, although level translator also can with transistor even the combination of resistance and diode realize, because being subject to the impact of stray capacitance, these methods have limited the transfer rate of data greatly.Although the commercialization of the level translator of wide byte, these devices have larger package dimension, more number of pins and I/ O direction control pin, thereby are not suitable for the bus of small-sized serial or Peripheral Interface and higher rate.If there is the conversion between multiple level, the system complexity forming with these devices also can be higher.And do not possess the able to programme and high feature of integrated level.
A lot of electronic systems continue to shift to lower level voltage signal.This trend power is behind the raising to reducing the demand of power consumption and the increase of microprocessor function and speed.The progress of the aspects such as commutating speed and reduction signal noise faster had both facilitated deviser, had also proposed new challenge to them.Microprocessor is taken the lead in the process marching to lower voltage levvl.Processor I/O voltage is just transferred to 1.5V from 1.8V, and core voltage can be lower than 1V.Microprocessor of future generation even will adopt lower voltage.Although the voltage of peripheral device component is also reducing, level lags behind processor generation left and right conventionally.The key difficult problem that the development inequality of lower voltage aspect has brought system designer to solve---how between signal level, to change reliably.Correct signal level can ensure the reliably working of system, they can prevent responsive integrated circuit because of too high or too low voltage conditions impaired.Level conversion is divided into unidirectional conversion and bi-directional conversion at present, also has single supply and dual power supply conversion, and dual power supply conversion adopts double track scheme to have the requirement that meets various aspects of performance.
The present invention has overcome in prior art and has not possessed programmable functions, the discontinuous not high defect of integrated level that is in harmonious proportion of voltage, has proposed a kind of able to programme pair of voltage level shifter and its implementation based on phase-change memory cell.Integrated level of the present invention is high, and has possessed able to programme, the continuously adjustable function of voltage.The phase-change memory cell of applying in the present invention has non-volatile memory function, though power down, the regulated value of low and high level of setting before still can recording, therefore to have level adjustable continuously for circuit, with CMOS process compatible, non-volatile and programmable feature.
Summary of the invention
The present invention proposes a kind of Programmable double-level converter based on phase-change memory cell, it is characterized in that, comprise level shifting circuit; Four changing voltage control circuits, described level shifting circuit is connected with the output of described changing voltage control circuit; The control of described changing voltage control circuit exports the low and high level of described level shifting circuit to; Realize the conversion of high low voltage signal and the control of output level by being input to input signal in described level shifting circuit and the output voltage of described changing voltage control circuit.
Wherein, described level shifting circuit comprises two nmos pass transistors, two PMOS transistors, phase inverter, low-voltage signal input end and two output terminals.The source electrode of described nmos pass transistor is connected with described changing voltage control circuit, the grid of described nmos pass transistor is connected with described low-voltage signal input end, the grid of described nmos pass transistor is connected with described low-voltage signal input end by described phase inverter, the drain electrode of described nmos pass transistor is connected with described output terminal, and the drain electrode of described nmos pass transistor is connected with described output terminal.The transistorized source electrode of described PMOS is connected with described changing voltage control circuit, and the transistorized grid of described PMOS is connected with described output terminal, and drain electrode is connected with described output terminal; The transistorized grid of described PMOS is connected with described output terminal, and drain electrode is connected with described output terminal.
Wherein, described changing voltage control circuit comprises phase-change memory cell, nmos pass transistor and signal input part; One end of described phase-change memory cell is connected with power supply, and the other end is connected with the drain electrode of described nmos pass transistor; The source ground of described nmos pass transistor, drain electrode is connected with described level shifting circuit, and grid is connected with described signal input part.
Wherein, described power supply is high-voltage power supply.
Wherein, the material of described phase-change memory cell comprises Ge-Sb-Te, silicon antimony tellurium, aluminium antimony tellurium.
Wherein, described nmos pass transistor can replace with PMOS transistor.
The present invention also proposes a kind of implementation method of the Programmable double-level converter based on phase-change memory cell, it is characterized in that, comprises the following steps:
Step 1, by controlling the grid of the described nmos pass transistor in described changing voltage control circuit, regulates the electric current of described phase-change memory cell, controls the size of the resistance value of described phase-change memory cell;
Step 2, controls the logical signal of the low-voltage signal input end in described level shifting circuit, regulates the low and high level output of described output terminal.
Wherein, in described step 2, in described level shifting circuit, the logical signal of described low-voltage signal input end is 1 o'clock, described nmos pass transistor conducting, described nmos pass transistor cut-off, described PMOS transistor turns, described PMOS transistor cut-off, described output terminal output low level, described output terminal output high level; The logical signal of described low-voltage signal input end is 0 o'clock, described nmos pass transistor cut-off, described nmos pass transistor conducting, described PMOS transistor cut-off, described PMOS transistor turns, described output terminal output high level, described output terminal output low level.
The present invention obtains target switching levels by the resistance states that changes phase-change memory cell in circuit, and it comprises a level shifting circuit and four changing voltage control circuits.Level shifting circuit can be realized the conversion of input low voltage signal to output HIGH voltage signal.Changing voltage control circuit can be realized the control to output signal low and high level.The resistance of phase-change memory cell can regulate by the current impulse that applies different sizes, thereby obtains the adjustable continuously of output low and high level.In addition phase-change memory cell has non-volatile memory function, though power down, the regulated value of low and high level of setting before still can recording, therefore to have level adjustable continuously for circuit, with CMOS process compatible, non-volatile and programmable feature.
Brief description of the drawings
Fig. 1 is the schematic diagram that the present invention is based on embodiment in the Programmable double-level converter of phase-change memory cell and its implementation.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail, and protection content of the present invention is not limited to following examples.Do not deviating under the spirit and scope of inventive concept, variation and advantage that those skilled in the art can expect are all included in the present invention, and taking appending claims as protection domain.
As Fig. 1, 2-NMOS transistor, 4-nmos pass transistor, 6-PMOS transistor, 8-PMOS transistor, 10-phase inverter, 12-nmos pass transistor, 14-nmos pass transistor, 16-changing voltage control circuit, 18-changing voltage control circuit, 20-level shifting circuit, 24-low-voltage signal input end, 26-signal input part, 28-signal input part, 30-output terminal, 32-output terminal, 34-phase-change memory cell, 36-phase-change memory cell, 37-NMOS transistor, 38-power supply, 40-ground connection, 42-NMOS transistor, 44-phase-change memory cell, 46-changing voltage control circuit, 48-changing voltage control circuit, 50-signal input part, 52-phase-change memory cell, 54-signal input part.
The present embodiment provides a kind of circuit of realizing of the Programmable double-level converter based on phase-change memory cell.As shown in Figure 1, the present invention includes 20, four changing voltage control circuits of a level shifting circuit 18,48,46,16.Level shifting circuit 20 comprises two nmos pass transistors 2,4, two PMOS transistors 6,8, phase inverter 10, low-voltage signal input end 24 and two output terminals 30,32.Changing voltage control circuit 18 comprises nmos pass transistor 12, phase-change memory cell 34 and signal input part 28.One end of phase-change memory cell 34 connects the drain electrode of nmos pass transistor 12, and the other end connects power supply 38.The drain electrode of nmos pass transistor 12 connects the source electrode of PMOS transistor 8, source ground 40, and grid connects input signal 28.Changing voltage control circuit 48 comprises nmos pass transistor 42, phase-change memory cell 44 and signal input part 50.One end of phase-change memory cell 44 connects the drain electrode of nmos pass transistor 42, and one end connects power supply 38, and power supply 38 is high-voltage power supply.The drain electrode of nmos pass transistor 42 connects the source electrode of PMOS transistor 6, source ground 40, and grid connects input signal 50.Changing voltage control circuit 16 comprises nmos pass transistor 14, phase-change memory cell 36 and signal input part 26.Phase-change memory cell 36 one end connect the drain electrode of nmos pass transistor 14, and one end connects power supply 38, and the drain electrode of nmos pass transistor 14 connects the source electrode of nmos pass transistor 2, source ground 40, and grid connects input signal 26.Changing voltage control circuit 46 comprises nmos pass transistor 37, phase-change memory cell 52 and signal input part 54.Phase-change memory cell 52 one end connect the drain electrode of nmos pass transistor 37, and the other end connects power supply 38, and the drain electrode of nmos pass transistor 37 connects the source electrode of nmos pass transistor 4, source ground 40, and grid connects input signal 54.Low-voltage signal input end 24 is input to grid and the phase inverter 10 of nmos pass transistor 2, and the output terminal of phase inverter 10 is connected to the grid of nmos pass transistor 4.The power supply of phase inverter 10 is low-tension supply.The drain electrode of nmos pass transistor 4 is connected to the grid of PMOS transistor 8 and the drain electrode of PMOS transistor 6 and output terminal 32, and the source electrode of nmos pass transistor 4 connects the drain electrode of nmos pass transistor 37.The drain electrode of nmos pass transistor 2 is connected to the grid of PMOS transistor 6 and the drain electrode of PMOS transistor 8 and output terminal 30.The source electrode of PMOS transistor 6 connects the drain electrode of nmos pass transistor 4.For transforming voltage control circuit the 18,48,16, the 46th, formed by phase-change memory cell 34,44,36,52 and nmos pass transistor 12,42,14,37, by controlling the resistance value of phase-changing memory unit 34,44,36,52 and the gate voltage of nmos pass transistor 12,42,14,37, transform the forward voltage that voltage control circuit 18,16,48,26 can reach nmos pass transistor 2,4 and PMOS transistor 6,8, and then the voltage of control output end 30 and 32.
Table one is for the present invention is based on the duty table of embodiment in the programmable levels converter of phase-change memory cell and its implementation.As shown in table 1, the logical signal " 1 " of inputting low pressure when low-voltage signal input end 24 makes nmos pass transistor 2 conductings, nmos pass transistor 4 ends, the output low level of output terminal 30, its magnitude of voltage is controlled by changing voltage control circuit 16, and the low level of output makes 6 conductings of PMOS transistor, and output terminal 32 is exported high level, its magnitude of voltage is controlled by changing voltage control circuit 48, and now PMOS transistor 8 ends.When making nmos pass transistor 2, end low-voltage signal input end 24 input logic signals " 0 ".After phase inverter 10, make nmos pass transistor 4 conductings, output terminal 32 output low levels, its magnitude of voltage is controlled by changing voltage control circuit 46, the low level of output makes 8 conductings of PMOS transistor, output terminal 30 is exported high level, and its magnitude of voltage is controlled by changing voltage control circuit 18, and now PMOS transistor 6 ends.The magnitude of voltage of the high level of output terminal 30 is to be determined by the resistance dividing potential drop of the resistance of phase-change memory cell 34 and transistor 12, and input signal 28 can regulate the conducting state of nmos pass transistor 12.The low level magnitude of voltage of output terminal 30 is determined by phase-change memory cell 36 and nmos pass transistor 14 equally, and input signal 26 can regulate the conducting state of nmos pass transistor 14.The magnitude of voltage of the high level of output terminal 32 is to be determined by the resistance dividing potential drop of the resistance of phase-change memory cell 44 and nmos pass transistor 42, input signal 50 can regulate the conducting state of nmos pass transistor 42. and the low level magnitude of voltage of same output terminal 30 is by phase-change memory cell 52 and 37 decisions, and input signal 54 can regulate the conducting state of nmos pass transistor 37.
In changing voltage control circuit 16,46,18,48, phase-change memory cell 36,52,34,44 has programmable functions, for the programming of phase-change memory cell 34, can realize by the grid of nmos pass transistor 12, give a pulse signal and control the program current by phase-change memory cell, and then control the size of its programming resistors value.Same, for the programming of phase-change memory cell 44,36,52, all can realize by the grid of controlling nmos pass transistor 42,14,37.In size when programming of controlling its programming resistors value, level shifting circuit 20 does not have DC channel, and input signal 24 can be 0 can be also 1.Due to the characteristic of phase-change material, phase-change memory cell 36,44,52,34 has the ability of repeatedly programming and preserving resistance states, the output low and high level that is output terminal 30 and 32 can require to programme according to difference in the same time not, and its programming resistors value still can be saved after system power failure.
Claims (6)
1. the Programmable double-level converter based on phase-change memory cell, is characterized in that, comprises level shifting circuit (20); Four changing voltage control circuits (16,18,46,48), described level shifting circuit (20) is connected with the output of described changing voltage control circuit (16,18,46,48); Described changing voltage control circuit (16,18,46,48) is controlled the low and high level that exports described level shifting circuit (20) to; Realize the conversion of high low voltage signal and the control of output level by being input to input signal in described level shifting circuit (20) and the output voltage of described changing voltage control circuit (16,18,46,48);
Wherein, described level shifting circuit (20) comprises the first nmos pass transistor (2) and the second nmos pass transistor (4), a PMOS transistor (6) and the 2nd PMOS transistor (8), phase inverter (10), low-voltage signal input end (24) and the first output terminal (30) and the second output terminal (32);
Described the first and second nmos pass transistors (2, 4) source electrode respectively with first and the 3rd described changing voltage control circuit (16, 46) connect, the grid of described the first nmos pass transistor (2) is connected with described low-voltage signal input end (24), the grid of described the second nmos pass transistor (4) is connected with described low-voltage signal input end (24) by described phase inverter (10), the drain electrode of described the first nmos pass transistor (2) is connected with described the first output terminal (30), the drain electrode of described the second nmos pass transistor (4) is connected with described the second output terminal (32), the source electrode of described the first and second PMOS transistors (6,8) is connected with second and the 4th described changing voltage control circuit (48,18) respectively, the grid of a described PMOS transistor (6) is connected with described the first output terminal (30), and the drain electrode of a described PMOS transistor (6) is connected with described the second output terminal (32), the grid of described the 2nd PMOS transistor (8) is connected with described the second output terminal (32), and the drain electrode of described the 2nd PMOS transistor (8) is connected with described the first output terminal (30),
Wherein, described changing voltage control circuit (16,18,46,48) comprises that the first phase-change memory cell (36), the second phase-change memory cell (34), third phase become storage unit (52) and the 4th phase-change memory cell (44), the 3rd nmos pass transistor (14), the 4th nmos pass transistor (12), the 5th nmos pass transistor (37) and the 6th nmos pass transistor (42) and first signal input end (26), secondary signal input end (28), the 3rd signal input part (54) and the 4th signal input part (50);
One end of described the first phase-change memory cell (36) is connected with power supply, and the other end is connected with the drain electrode of described the 3rd nmos pass transistor (14); One end of described the second phase-change memory cell (34) is connected with power supply, and the other end is connected with the drain electrode of described the 4th nmos pass transistor (12); One end that described third phase becomes storage unit (52) is connected with power supply, and the other end is connected with the drain electrode of described the 5th nmos pass transistor (37); One end of described the 4th phase-change memory cell (44) is connected with power supply, and the other end is connected with the drain electrode of described the 6th nmos pass transistor (42);
The source ground of described the 3rd nmos pass transistor (14), drain electrode is connected with described level shifting circuit (20), and grid is connected with described first signal input end (26); The source ground of described the 4th nmos pass transistor (12), drain electrode is connected with described level shifting circuit (20), and grid is connected with described secondary signal input end (28); The source ground of described the 5th nmos pass transistor (37), drain electrode is connected with described level shifting circuit (20), and grid is connected with described the 3rd signal input part (54); The source ground of described the 6th nmos pass transistor (42), drain electrode is connected with described level shifting circuit (20), and grid is connected with described the 4th signal input part (50).
2. the Programmable double-level converter based on phase-change memory cell as claimed in claim 1, is characterized in that, described power supply (38) is high-voltage power supply.
3. the Programmable double-level converter based on phase-change memory cell as claimed in claim 1, is characterized in that, the material of described first to fourth phase-change memory cell (34,36,44,52) comprises Ge-Sb-Te, silicon antimony tellurium or aluminium antimony tellurium.
4. the Programmable double-level converter based on phase-change memory cell as claimed in claim 1, it is characterized in that, in described changing voltage control circuit, the described nmos pass transistor of (16,18,46,48) (12,14,37,42) also can replace with PMOS transistor.
5. the implementation method of the Programmable double-level converter based on phase-change memory cell as described in any one in claim 1-4, is characterized in that, comprises the following steps:
Step 1, by controlling the grid of the described nmos pass transistor (12,14,37,42) in described changing voltage control circuit (16,18,46,48), regulate the electric current of described first to fourth phase-change memory cell (36,34,42,44), control the size of the resistance value of described first to fourth phase-change memory cell (36,34,42,44);
Step 2, controls the logical signal of the low-voltage signal input end (24) in described level shifting circuit (20), regulates the low and high level output of described the first and second output terminals (30,32).
6. the implementation method of the Programmable double-level converter based on phase-change memory cell as claimed in claim 5, it is characterized in that, in described step 2, in described level shifting circuit (20), the logical signal of described low-voltage signal input end (24) is 1 o'clock, described the first nmos pass transistor (2) conducting, described the second nmos pass transistor (4) cut-off, described PMOS transistor (6) conducting, described the 2nd PMOS transistor (8) cut-off, described the first output terminal (30) output low level, described the second output terminal (32) output high level; The logical signal of described low-voltage signal input end (24) is 0 o'clock, described the first nmos pass transistor (2) cut-off, described the second nmos pass transistor (4) conducting, described PMOS transistor (6) cut-off, described the 2nd PMOS transistor (8) conducting, described the first output terminal (30) output high level, described the second output terminal (32) output low level.
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| CN101325413A (en) * | 2007-06-14 | 2008-12-17 | 旺宏电子股份有限公司 | Power supply switching circuit |
| CN101442307A (en) * | 2007-11-22 | 2009-05-27 | 联发科技股份有限公司 | Level shifter |
| CN101546999A (en) * | 2008-03-24 | 2009-09-30 | 瑞鼎科技股份有限公司 | level conversion circuit |
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| US7804327B2 (en) * | 2007-10-12 | 2010-09-28 | Mediatek Inc. | Level shifters |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101325413A (en) * | 2007-06-14 | 2008-12-17 | 旺宏电子股份有限公司 | Power supply switching circuit |
| CN101442307A (en) * | 2007-11-22 | 2009-05-27 | 联发科技股份有限公司 | Level shifter |
| CN101546999A (en) * | 2008-03-24 | 2009-09-30 | 瑞鼎科技股份有限公司 | level conversion circuit |
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