CN204576334U - Output impedance Circuit tuning in a kind of interface circuit - Google Patents
Output impedance Circuit tuning in a kind of interface circuit Download PDFInfo
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- CN204576334U CN204576334U CN201520304624.2U CN201520304624U CN204576334U CN 204576334 U CN204576334 U CN 204576334U CN 201520304624 U CN201520304624 U CN 201520304624U CN 204576334 U CN204576334 U CN 204576334U
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Abstract
The utility model provides the Circuit tuning of the output impedance in a kind of interface circuit, and it comprises the first control module, the second control module, is connected to the driving resistance replication module between the first voltage end and the second voltage end and built-in calibrated resistance successively.Drive resistance replication module to copy first of interface circuit and export driving resistance unit; Built-in calibrated resistance is placed in the wafer of described interface circuit place; First control module regulates the resistance and first driving resistance replication module to export the resistance driving resistance unit based on the voltage synchronous of the first connected node driven between resistance replication module and built-in calibrated resistance; Second control module exports based on first the voltage-regulation second driving resistance unit and second to export the second connected node driven between resistance unit and exports the resistance driving resistance unit.Compared with prior art, the utility model can, when without plug-in calibrated resistance, adopt built-in calibrated resistance to drive resistance to carry out impedance adjustment to output.
Description
[technical field]
The utility model relates to interface circuit design technical field, the output impedance Circuit tuning particularly in a kind of interface circuit.
[background technology]
DDR (Double Data Rate, Double Data Rate) output interface driving circuit usually by CMOS tube formed export drive resistance, or by CMOS tube add resistance be combined to form export drive resistance, along with the progressively raising of operating rate, needing to drive resistance to regulate to output, to drive the resistance of resistance to control in certain scope by exporting, reducing its change with technique, temperature and voltage, strengthen the impedance matching with chip exterior circuit, reduce reflection.
The interfaces such as existing DDR3/LPDDR2/LPDDR3 need plug-in precise resistances, the resistance of this plug-in precise resistances is not substantially with technique, temperature and change in voltage, adjust the impedance of the output driving resistance of ddr interface for standard with plug-in precise resistances, thus reduce pull-up output driving resistance and the change of drop-down output driving resistance at different process, voltage and temperature, realize impedance matching, but plug-in precise resistances adds the holistic cost of product to a certain extent.
Therefore, be necessary to provide a kind of technical scheme of improvement to solve the problems referred to above.
[utility model content]
The purpose of this utility model is to provide the Circuit tuning of the output impedance in a kind of interface circuit, and it when without plug-in calibrated resistance, can adopt built-in calibrated resistance to drive resistance to carry out impedance adjustment to output, thus save cost of products.
In order to solve the problem, the utility model provides the Circuit tuning of the output impedance in a kind of interface circuit, it is characterized in that, it comprises the first control module, second control module, is connected to the driving resistance replication module between the first voltage end and the second voltage end and built-in calibrated resistance successively.Described driving resistance replication module copies first of described interface circuit and exports driving resistance unit; Described built-in calibrated resistance is placed in the wafer of described interface circuit place; Described first control module regulates the resistance and first driving resistance replication module to export the resistance driving resistance unit based on the voltage synchronous of the first connected node driven between resistance replication module and built-in calibrated resistance, makes to drive the resistance of resistance replication module and first to export the resistance driving the resistance of resistance unit to be equal to described built-in calibrated resistance; Described second control module exports based on first the voltage-regulation second driving resistance unit and second to export the second connected node driven between resistance unit and exports the resistance driving resistance unit, the second output is made to drive the resistance of resistance unit to equal the resistance of the first output driving resistance unit, wherein, the first output drives resistance unit and the second output to drive resistance unit to be connected to successively between described first voltage end and the second voltage end.
Further, described built-in calibrated resistance comprises the first sub-resistance of positive temperature coefficient (PTC) and the second sub-resistance of negative temperature coefficient, and this built-in calibrated resistance entirety presents zero-temperature coefficient.
Further, described driving resistance replication module and described first exports and drives resistance unit to include several metal-oxide-semiconductors; Described first control module exports the first control signal based on the voltage of described first connected node, to control the conducting number of the metal-oxide-semiconductor in described driving resistance replication module, the voltage of described first connected node is made to equal (V1+V2)/2, wherein, V1 is the magnitude of voltage of the first voltage end, and V2 is the magnitude of voltage of the second voltage end; Described first control module drives the control of the metal-oxide-semiconductor in resistance unit identical to the control of the metal-oxide-semiconductor in described driving resistance replication module with it based on described first control signal to described first output.
Further, described second output drives resistance unit to comprise several metal-oxide-semiconductors; Described second control module exports the second control signal based on the voltage of described second connected node, to control the conducting number that described second exports the metal-oxide-semiconductor driven in resistance unit, the voltage of described second connected node is made to equal (V1+V2)/2, wherein, V1 is the magnitude of voltage of the first voltage end, and V2 is the magnitude of voltage of the second voltage end.
Further, the output impedance Circuit tuning in described interface circuit also comprises the 3rd control module and change-over switch.A link of described change-over switch is connected with described first connected node, and its second link is connected with one end of described built-in calibrated resistance, and the other end of described built-in calibrated resistance is connected with the second voltage end; The input end of described 3rd control module is connected with described first connected node, and its output terminal is connected with the control end of described change-over switch, and when described first connected node is not connected with plug-in calibrated resistance, described 3rd control module controls change-over switch conducting; When described first connected node is connected with one end of plug-in calibrated resistance, when the other end of plug-in calibrated resistance is connected with the second voltage end, described 3rd control module controls change-over switch and turns off.
Further, described interface circuit is ddr interface, described first voltage end is power end, described second voltage end is earth terminal, described first output drives resistance unit to be pulling drive resistance unit, first exports driving resistance unit and drives the metal-oxide-semiconductor in resistance replication module to be PMOS, and described second output drives resistance unit to be drop-down driving resistance unit, and the second output drives the metal-oxide-semiconductor in resistance unit to be NMOS tube.
Further, described 3rd control module comprises comparer, an input end of described comparer is connected with the first connected node as the input end of described 3rd control module, another input end of described comparer is connected with a reference voltage, and the output terminal of described comparer is connected with the control end of described change-over switch as the output terminal of described 3rd control module.When described first connected node is not connected with plug-in calibrated resistance, the voltage of the first connected node is greater than described reference voltage, and described comparer exports the first logic level, controls change-over switch conducting; When described first connected node is connected with plug-in calibrated resistance, the voltage of the first connected node is less than described reference voltage, and described comparer exports the second logic level, controls change-over switch and turns off.
Further, described pulling drive resistance unit also comprises the first resistance, several PMOS transistor described of described first resistance and parallel connection are series between power end and the second connected node, the sub-control signal that the grid of each PMOS transistor is all corresponding with the first control signal is connected, and is controlled conducting or the shutoff of several PMOS transistor described by the sub-control signal of correspondence.Described driving resistance replication module copies described pulling drive resistance unit, the first resistance in described driving resistance replication module and several PMOS transistor described parallel with one another are series between power end and the second connected node, the sub-control signal that the grid of each PMOS transistor is all corresponding with the first control signal is connected, and can be controlled conducting or the shutoff of several PMOS transistor described by the sub-control signal of correspondence.
Further, described interface circuit is ddr interface, described second voltage end is power end, described first voltage end is earth terminal, described first output drives resistance unit to be drop-down driving resistance unit, described second output drives resistance unit to be pulling drive resistance unit, and the first output drives the metal-oxide-semiconductor in resistance unit and driving resistance replication module to be NMOS tube, and the described second metal-oxide-semiconductor exported in driving resistance unit is PMOS.
Further, described drop-down driving resistance unit also comprises the second resistance, several nmos pass transistors described of described second resistance and parallel connection are series between the second connected node and earth terminal, the sub-control signal that the grid of each nmos pass transistor is all corresponding with the first control signal is connected, and can be controlled conducting or the shutoff of several nmos pass transistors described by the sub-control signal of correspondence.Described driving resistance replication module copies described drop-down driving resistance unit, described second resistance in described driving resistance replication module and several nmos pass transistors of parallel connection are series between the second connected node and earth terminal, the sub-control signal that the grid of each nmos pass transistor is all corresponding with the first control signal is connected, and is controlled conducting or the shutoff of several nmos pass transistors described by the sub-control signal of correspondence.
Compared with prior art, the utility model by interface circuit the built-in calibrated resistance of built-in and plug-in calibrated resistance equivalent effect in the chips, with when without plug-in calibrated resistance, adopt the output of built-in calibrated resistance interface circuit to drive resistance to carry out impedance adjustment, thus save cost of products.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the circuit diagram of the output impedance Circuit tuning in the utility model interface circuit in one embodiment;
Fig. 2 is the circuit diagram of the output impedance Circuit tuning in the utility model interface circuit in another embodiment;
Fig. 3 a and 3b is circuit diagram corresponding to the output impedance Circuit tuning corresponding module in a specific embodiment in the interface circuit shown in Fig. 2;
Fig. 4 a and 4b is circuit diagram corresponding to the corresponding module of output impedance Circuit tuning in another specific embodiment in the interface circuit shown in Fig. 2;
Fig. 5 is pull-up resistor driver element of the present utility model circuit diagram in one embodiment;
Fig. 6 is pull down resistor driver element of the present utility model circuit diagram in one embodiment.
[embodiment]
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in further detail the utility model below in conjunction with the drawings and specific embodiments.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the utility model.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.
Please refer to shown in Fig. 1, it is the circuit diagram of the output impedance Circuit tuning in the utility model interface circuit in one embodiment.
The output impedance Circuit tuning of the interface circuit in Fig. 1 comprises the first output be series at successively between the first voltage end V1 and the second voltage end V2 and drives resistance unit 110 and second to export driving resistance unit 120, and calibration circuit 130.Calibration circuit 130 in Fig. 1 comprises the first control module 132, second control module 134, is connected to driving resistance replication module 136 between the first voltage end V1 and the second voltage end V2 and built-in calibrated resistance ZQRC successively.Described interface circuit can be ddr interface circuit, also can be other interface circuits.First exports the output driving resistance unit 110 and the second output to drive resistance unit 120 to form described interface circuit drives resistance.
Described driving resistance replication module 136 copies described first and exports driving resistance unit 110, and described driving resistance replication module 136 and described first exports and drives resistance unit 110 to include several MOS (MetalOxide Semiconductor) pipe.
Described built-in calibrated resistance (it is also known as built-in precise resistances) ZQRC is placed in the wafer of described interface circuit place, and described built-in calibrated resistance ZQRC can provide resistance value relatively accurately, not variation with temperature and changing.Described built-in calibrated resistance ZQRC comprises the first sub-resistance of positive temperature coefficient (PTC) and the second sub-resistance of negative temperature coefficient, to offset the change in resistance that Yin Wendu causes, namely it is overall in zero-temperature coefficient, the change in resistance simultaneously caused due to voltage is little, thus this built-in calibrated resistance ZQRC can provide the resistance of certain degree of accuracy.
Described first control module 132 is based on the voltage of the first connected node DQ driven between resistance replication module 136 and built-in calibrated resistance ZQRC, adjusted in concert drives the resistance of resistance replication module 136 and first to export the resistance driving resistance unit 110, makes the resistance of driving resistance replication module 136 and first export the resistance driving the resistance of resistance unit 110 to be equal to described built-in calibrated resistance ZQRC.Be specially, described first control module 132 exports the first control signal CO1 based on the voltage of described first connected node DQ, to control the conducting number of the metal-oxide-semiconductor in described driving resistance replication module 136, the voltage of described first connected node DQ is made to equal (V1+V2)/2, wherein, V1 is the magnitude of voltage of the first voltage end, and V2 is the magnitude of voltage of the second voltage end; Described first control module 132 drives the control of the metal-oxide-semiconductor in resistance unit 110 identical to the control of the metal-oxide-semiconductor in described driving resistance replication module 136 with it based on described first control signal CO1 to described first output.
Under the control of the first control module 132, after the resistance driving the resistance of resistance replication module 136 and first to export driving resistance unit 110 has been calibrated, described second control module 134 exports based on first and drives resistance unit 110 and the second voltage-regulation second exporting the second connected node DQC driven between resistance unit 120 to export the resistance driving resistance unit 120, makes the second output drive the resistance of resistance unit 120 to equal described first and exports the resistance driving resistance unit 110.Concrete, described second exports driving resistance unit 120 comprises several metal-oxide-semiconductors; Described second control module 134 exports the second control signal CO2 based on the voltage of described second connected node DQC, to control the number that described second exports the conducting of the metal-oxide-semiconductor driven in resistance unit 120, the voltage of described second connected node DQC is made to equal (V1+V2)/2, wherein, V1 is the magnitude of voltage of the first voltage end, and V2 is the magnitude of voltage of the second voltage end.
In summary, the utility model is by the built-in calibrated resistance at interface circuit place built-in chip type and plug-in calibrated resistance (or plug-in precise resistances) equivalent effect, when without plug-in calibrated resistance, based on the voltage of the first connected node DQ driven between resistance replication module 136 and built-in calibrated resistance ZQRC, adjusted in concert drives the resistance of resistance replication module 136 and first to export the resistance driving resistance unit 110, the resistance of driving resistance replication module 136 and first is exported drive the resistance of resistance unit 110 be equal to described built-in calibrated resistance ZQRC resistance (namely with built-in calibrated resistance ZQRC for standard, the resistance and first driving resistance replication module 136 is regulated to export the resistance driving resistance unit 110), exporting based on first drives resistance unit 110 and the second voltage-regulation second exporting the second connected node DQC driven between resistance unit 120 to export the resistance driving resistance unit 120, make the second output drive the resistance of resistance unit 120 to equal described first output and drive the resistance of resistance unit 110 (namely exporting with first drives resistance unit 110 to be the resistance that standard adjustment second exports driving resistance unit 120), thus realize with built-in calibrated resistance ZQRC as standard, regulate first to export and drive resistance unit 110 and second to export the resistance (or impedance) driving resistance unit 120, like this, can regulate to take into account impedance simultaneously and save the requirement that plug-in calibrated resistance saves cost two aspect.
In order to the situation making the output impedance Circuit tuning in interface circuit of the present utility model namely be applicable to plug-in calibrated resistance, be applicable to again the situation without plug-in calibrated resistance, need the output impedance Circuit tuning in the interface circuit described in Fig. 1 be improved.Specifically please refer to shown in Fig. 2, it is the circuit diagram of the output impedance Circuit tuning in the utility model interface circuit in another embodiment.In Fig. 2 first exports and drives resistance unit 210, second to export to drive resistance unit 220, first control module 232, second control module 234, drives resistance replication module 236 and built-in calibrated resistance ZQRC, exports respectively to drive resistance unit 110, second to export to drive resistance unit 120, first control module 132, second control module 134, drive resistance replication module 136 identical with built-in calibrated resistance ZQRC with first in Fig. 1.The difference of Fig. 2 and Fig. 1 is, adds the 3rd control module 238; Between the first connected node DQ and described built-in calibrated resistance ZQRC, set up one switched K switch 1.
A link of described change-over switch K1 is connected with described first connected node DQ, another link of described change-over switch K1 is connected with one end of described built-in calibrated resistance ZQRC, and the other end of described built-in calibrated resistance ZQRC is connected with the second voltage end V2.
The input end of described 3rd control module 238 is connected with described first connected node DQ, and its output terminal is connected with the control end of described change-over switch K1.Change-over switch K1 acquiescence in calibration circuit 230 in interface circuit turns off, when described first connected node DQ is not connected with plug-in calibrated resistance ZQR (during without plug-in calibrated resistance), the voltage of the first connected node DQ is close to the voltage of the first voltage end V1, the 3rd control signal CO3 that described 3rd control module 238 exports controls change-over switch K1 conducting, now, by the first control module 232, second control module 234, resistance replication module 236 and built-in calibrated resistance ZQRC is driven to form the first output impedance Circuit tuning, thus with built-in calibrated resistance ZQRC for standard drives resistance unit 210 and the second output to drive resistance unit 220 to carry out impedance adjustment to the first output, specific works process identical with the course of work of the output impedance Circuit tuning in the interface circuit shown in Fig. 1 (specifically referring to above to the introduction of the course of work of the output impedance Circuit tuning in the interface circuit in Fig. 1), when described first connected node DQ is connected with one end of plug-in calibrated resistance ZQR, when the other end of plug-in calibrated resistance ZQR is connected with the second voltage end V2 (when having plug-in calibrated resistance), the voltage of the first connected node DQ is close to the voltage of the second voltage end V2, the 3rd control signal CO3 that described 3rd control module 238 exports controls change-over switch K1 and turns off, now, by the first control module 232, second control module 234, resistance replication module 236 and plug-in calibrated resistance ZQR is driven to form the second output impedance Circuit tuning, thus with plug-in calibrated resistance ZQR for standard drives resistance unit 210 and the second output to drive resistance unit 220 to carry out impedance adjustment to the first output, specific works process is with built-in calibrated resistance ZQRC, for standard exports first, to drive resistance unit 210 and second to export to drive resistance unit 220 to carry out the principle of work of impedance adjustment identical, do not repeat them here.
Please refer to shown in Fig. 3 a and Fig. 3 b, it is circuit diagram corresponding to the output impedance Circuit tuning corresponding module in a specific embodiment in the interface circuit shown in Fig. 2.
In the embodiment shown in Fig. 3 a and Fig. 3 b, described first voltage end V1 is power end VIN; Described second voltage end V2 is earth terminal GND; First output drives resistance unit 310 to be pulling drive resistance unit PD240, and they several MOS transistor comprised are PMOS transistor, and the desired value of its resistance adjustment is 240 ohm; Second output drives resistance unit 320 to be drop-down driving resistance unit ND240, and they several MOS transistor comprised are nmos pass transistor, and the desired value of its resistance adjustment is 240 ohm; Described driving resistance replication module 336 copies pulling drive resistance unit PD240 completely; Described built-in calibrated resistance ZQRC has the resistance of certain degree of accuracy to be the built-in calibrated resistance of 240 ohm, and its resistance does not vary with temperature substantially, and also little with the change of voltage; Described plug-in calibrated resistance ZQR is that its resistance is not substantially with technique, temperature and change in voltage substantially not with the plug-in calibrated resistance that the resistance of technique, temperature and change in voltage is 240 ohm.
The 3rd control module shown in Fig. 3 b comprises comparer, an input end of this comparer is connected with described first connected node DQ as the input end of described 3rd control module, its another input end is connected with a reference resistance VR, and the output terminal of described comparer is connected with the control end of described change-over switch K1 as the output terminal CO3 of the 3rd control module.When described first connected node DQ is not connected with plug-in calibrated resistance ZQR, the voltage of the first connected node DQ is close to the voltage of power end VIN, now, the voltage of the first connected node DQ is greater than described reference voltage VR, the 3rd control signal CO3 that described comparer exports is the first logic level, and it controls change-over switch K1 conducting; When described first connected node DQ is connected with one end of plug-in calibrated resistance ZQR, when the other end of plug-in calibrated resistance ZQR is connected with the second voltage end V2, the voltage of the first connected node DQ is close to the voltage of earth terminal GND, now, the voltage of the first connected node DQ is less than described reference voltage VR, the 3rd control signal CO3 that described comparer exports is the second logic level, and it controls change-over switch K1 and turns off.
Due in the embodiment shown in Fig. 3 a and Fig. 3 b, described driving resistance replication module 336 copies pulling drive resistance unit PD240 completely, therefore, output impedance Circuit tuning in interface circuit in this embodiment is with described built-in calibrated resistance ZQRC or plug-in calibrated resistance ZQR for standard, and synchronous adjustment drives the resistance of resistance replication module 336 and the resistance of pulling drive resistance unit PD240; With the resistance of pulling drive resistance unit PD240 drop-down driving resistance unit ND240 for standard adjusts, thus the resistance of the resistance of pulling drive resistance unit PD240 and drop-down driving resistance unit ND240 is finally made to be equal to the resistance of built-in calibrated resistance ZQRC or plug-in calibrated resistance ZQR.
Please refer to shown in Fig. 4 a and Fig. 4 b, it is circuit diagram corresponding to the corresponding module of output impedance Circuit tuning in another specific embodiment in the interface circuit shown in Fig. 2.
In the embodiment shown in Fig. 4 a and Fig. 4 b, described first voltage end V1 is earth terminal GND; Described second voltage end V2 is power end VIN; First output drives resistance unit 410 to be drop-down driving resistance unit ND240, and they several MOS transistor comprised are nmos pass transistor, and the desired value of its resistance adjustment is 240 ohm; Second output drives resistance unit 420 to be pulling drive resistance unit PD240, and they several CMOS transistor comprised are PMOS transistor, and the desired value of its resistance adjustment is 240 ohm; Described driving resistance replication module 436 copies drop-down driving resistance unit ND240 completely; The resistance of described built-in calibrated resistance ZQRC is 240 ohm, and its resistance does not vary with temperature substantially, and also little with the change of voltage; The resistance of described plug-in calibrated resistance ZQR is 240 ohm, and its resistance is not substantially with technique, temperature and change in voltage.
The 3rd control module shown in Fig. 4 b comprises comparer, an input end of this comparer is connected with described first connected node DQ as the input end of described 3rd control module, its another input end is connected with a reference resistance VR, and the output terminal of described comparer is connected with the control end of described change-over switch K1 as the output terminal CO3 of the 3rd control end.When described first connected node DQ is not connected with plug-in calibrated resistance ZQR, the voltage of the first connected node DQ is close to the voltage of earth terminal GND, now, the voltage of the first connected node DQ is less than described reference voltage VR, the 3rd control signal CO3 that described comparer exports is the first logic level, and it controls change-over switch K1 conducting; When described first connected node DQ is connected with one end of plug-in calibrated resistance ZQR, when the other end of plug-in calibrated resistance ZQR is connected with power end VIN, the voltage of the first connected node DQ is close to the voltage of power end VIN, now, the voltage of the first connected node DQ is greater than described reference voltage VR, the 3rd control signal CO3 that described comparer exports is the second logic level, and it controls change-over switch K1 and turns off.
The difference of the embodiment shown in the embodiment shown in Fig. 4 a and Fig. 4 b and Fig. 3 a and Fig. 3 b is, described driving resistance copied cells 436 in embodiment shown in Fig. 4 a and Fig. 4 b copies drop-down driving resistance unit ND240 completely, therefore, output impedance Circuit tuning in interface circuit in this embodiment is with described built-in calibrated resistance ZQRC or plug-in calibrated resistance ZQR for standard, and synchronous adjustment drives the resistance of resistance replication module 436 and the resistance of drop-down driving resistance unit ND240; With the resistance of drop-down driving resistance unit ND240 for standard adjustment pulling drive resistance unit PD240, thus the resistance of the resistance of pulling drive resistance unit PD240 and drop-down driving resistance unit ND240 is finally made to be equal to the resistance of built-in calibrated resistance ZQRC or plug-in calibrated resistance ZQR.
In addition, due to the limitation of CMOS (Complementary Metal Oxide Semiconductor) pipe itself, usually CMOS tube resistance in series is needed to make junior unit to improve the linearity of resistance, then the quantity by adjusting junior unit further reaches the size of required resistance, such as, small resistor unit is made by CMOS tube resistance in series, junior unit is according to technique, the change of temperature and voltage adjusts the large resistance unit of 240 ohm, large resistance unit needs to be configured to 34.4 according to real work, 40, the different outputs such as 48 ohm drive resistance.So arrange and will cause junior unit One's name is legion, thus cause chip area shared by CMOS tube and resistance excessive, be unfavorable for chip miniaturization.Therefore, the utility model also improves the structure of pulling drive resistance unit and drop-down driving resistance unit, by by series with a resistor again after several CMOS tube parallel connections, formed and drive resistance unit, driving resistance unit needs to be configured to different output according to real work and drives resistance, like this, can ensure to export under the prerequisite driving resistance sizes requirement and resistance linearity, significantly reduce the chip area shared by it, save cost.
Please refer to shown in Fig. 5, it is pulling drive resistance unit 310 circuit diagram in one embodiment in Fig. 3 a.This pulling drive resistance unit 310 comprises PMOS (the P-channel Metal OxideSemiconductor) transistor of the first resistance R1 and M the parallel connection be series between power end VIN and the second connected node DQC, the sub-control signal that the grid of each PMOS transistor is all corresponding with the first control signal CO1 is connected, can the conducting of a control M PMOS transistor or shutoff by the sub-control signal of correspondence, wherein M be greater than 1 natural number.
In the embodiment shown in fig. 5, a described M PMOS transistor is respectively PMOS transistor MP
1, MP
2..., MP
m-1, MP
m.The source electrode of M PMOS transistor is all connected with power end VIN, and the drain electrode of M PMOS transistor is all connected with one end of described first resistance R1, and the other end of described first resistance R1 is connected with the second connected node DQC.In another embodiment, also the annexation of the PMOS transistor of the first resistance R1 and M in Fig. 5 parallel connection can be exchanged, namely the drain electrode of M PMOS transistor is all connected with the second connected node DQC, the source electrode of M PMOS transistor is all connected with one end of described first resistance R1, and the other end of described first resistance R1 is connected with power end VIN.Because described driving resistance replication module 336 copies described pulling drive resistance unit 310, therefore, corresponding described driving resistance replication module 336 comprises the PMOS transistor of the first resistance R1 and M the parallel connection be series between power end VIN and the first connected node DQ, the sub-control signal that the grid of each PMOS transistor is all corresponding with the first control signal CO1 is connected, wherein M be greater than 1 natural number.
Please refer to shown in Fig. 6, it is drop-down driving resistance unit 320 circuit diagram in one embodiment in Fig. 3 a.This drop-down driving resistance unit 320 comprises the nmos pass transistor being series at the second resistance R2 between the second connected node DQC and earth terminal GND and N number of parallel connection, the sub-control signal that the grid of each nmos pass transistor is all corresponding with the second control signal CO2 is connected, conducting or the shutoff of N number of nmos pass transistor can be controlled by the sub-control signal of correspondence, wherein N be greater than 1 natural number.
In the embodiment shown in fig. 6, described N number of nmos pass transistor, is respectively nmos pass transistor MN
1, MN
2..., MN
n-1, MN
n.The source electrode of N number of nmos pass transistor is all connected with earth terminal GND, and the drain electrode of N number of nmos pass transistor is all connected with one end of described second resistance R2, and the other end of described second resistance R2 is connected with the second connected node DQC.In another embodiment, the annexation of the nmos pass transistor of the second resistance R2 in Fig. 6 and N number of parallel connection can be exchanged, namely the drain electrode of N number of nmos pass transistor all with the second connected node DQC, the source electrode of N number of nmos pass transistor is all connected with one end of described second resistance R2, and the other end of described second resistance R2 is connected with earth terminal GND.
In like manner, the pulling drive resistance unit 420 in Fig. 4 a can be identical with the circuit structure of the drop-down driving resistance unit shown in Fig. 6 with the pulling drive resistance unit shown in Fig. 5 respectively with the circuit structure of drop-down driving resistance unit 410.It should be noted that, first, the sub-control signal that the grid of each PMOS transistor in the pulling drive resistance unit 420 in Fig. 4 a is all corresponding with the second control signal CO2 is connected, can the conducting of a control M PMOS transistor or shutoff by the sub-control signal of correspondence; The sub-control signal that the grid of each nmos pass transistor in the drop-down driving resistance unit 410 in Fig. 4 a is all corresponding with the first control signal CO1 is connected, and can be controlled conducting or the shutoff of N number of nmos pass transistor by the sub-control signal of correspondence; 3rd, pulling drive resistance unit 420 is copied completely owing to driving resistance replication module 436, therefore, corresponding described driving resistance replication module 436 comprises the nmos pass transistor being series at the second resistance R2 between the first connected node DQ and earth terminal GND and N number of parallel connection, the sub-control signal that the grid of each nmos pass transistor is all corresponding with the first control signal CO1 is connected, wherein, N be greater than 1 natural number.
Known based on Fig. 5 and Fig. 6, the utility model passes through in series with a resistor again after several CMOS tube parallel connections, resistance unit is driven to be formed, drive resistance unit to need combination to be configured to different output according to real work and drive resistance, like this, ensureing to export under the prerequisite driving resistance sizes requirement and resistance linearity, significantly resistance in series quantity can be reduced, thus reduce the chip area of this output driving shared by resistance, save chip cost.
In the utility model, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that embodiment of the present utility model is done all do not departed to claims of the present utility model.Correspondingly, the scope of claim of the present utility model is also not limited only to previous embodiment.
Claims (10)
1. the output impedance Circuit tuning in interface circuit, is characterized in that, it comprises the first control module, the second control module, is connected to the driving resistance replication module between the first voltage end and the second voltage end and built-in calibrated resistance successively,
Described driving resistance replication module copies first of described interface circuit and exports driving resistance unit;
Described built-in calibrated resistance is placed in the wafer of described interface circuit place;
Described first control module regulates the resistance and first driving resistance replication module to export the resistance driving resistance unit based on the voltage synchronous of the first connected node driven between resistance replication module and built-in calibrated resistance, makes to drive the resistance of resistance replication module and first to export the resistance driving the resistance of resistance unit to be equal to described built-in calibrated resistance;
Described second control module exports based on first the voltage-regulation second driving resistance unit and second to export the second connected node driven between resistance unit and exports the resistance driving resistance unit, the second output is made to drive the resistance of resistance unit to equal the resistance of the first output driving resistance unit
Wherein, the first output drives resistance unit and the second output to drive resistance unit to be connected to successively between described first voltage end and the second voltage end.
2. the output impedance Circuit tuning in interface circuit according to claim 1, it is characterized in that, described built-in calibrated resistance comprises the first sub-resistance of positive temperature coefficient (PTC) and the second sub-resistance of negative temperature coefficient, and this built-in calibrated resistance entirety presents zero-temperature coefficient.
3. the output impedance Circuit tuning in interface circuit according to claim 2, is characterized in that,
Described driving resistance replication module and described first exports and drives resistance unit to include several metal-oxide-semiconductors;
Described first control module exports the first control signal based on the voltage of described first connected node, to control the conducting number of the metal-oxide-semiconductor in described driving resistance replication module, the voltage of described first connected node is made to equal (V1+V2)/2, wherein, V1 is the magnitude of voltage of the first voltage end, and V2 is the magnitude of voltage of the second voltage end;
Described first control module drives the control of the metal-oxide-semiconductor in resistance unit identical to the control of the metal-oxide-semiconductor in described driving resistance replication module with it based on described first control signal to described first output.
4. the output impedance Circuit tuning in interface circuit according to claim 3, is characterized in that,
Described second exports driving resistance unit comprises several metal-oxide-semiconductors;
Described second control module exports the second control signal based on the voltage of described second connected node, to control the conducting number that described second exports the metal-oxide-semiconductor driven in resistance unit, the voltage of described second connected node is made to equal (V1+V2)/2, wherein, V1 is the magnitude of voltage of the first voltage end, and V2 is the magnitude of voltage of the second voltage end.
5. the output impedance Circuit tuning in interface circuit according to claim 2, is characterized in that, it also comprises the 3rd control module and change-over switch,
A link of described change-over switch is connected with described first connected node, and its second link is connected with one end of described built-in calibrated resistance, and the other end of described built-in calibrated resistance is connected with the second voltage end;
The input end of described 3rd control module is connected with described first connected node, and its output terminal is connected with the control end of described change-over switch, and when described first connected node is not connected with plug-in calibrated resistance, described 3rd control module controls change-over switch conducting; When described first connected node is connected with one end of plug-in calibrated resistance, when the other end of plug-in calibrated resistance is connected with the second voltage end, described 3rd control module controls change-over switch and turns off.
6., according to the output impedance Circuit tuning in the arbitrary described interface circuit of claim 1-5, it is characterized in that,
Described interface circuit is ddr interface, described first voltage end is power end, described second voltage end is earth terminal, described first output drives resistance unit to be pulling drive resistance unit, first exports driving resistance unit and drives the metal-oxide-semiconductor in resistance replication module to be PMOS, described second output drives resistance unit to be drop-down driving resistance unit, and the second metal-oxide-semiconductor exported in driving resistance unit is NMOS tube.
7. the output impedance Circuit tuning in interface circuit according to claim 6, is characterized in that,
Described 3rd control module comprises comparer, an input end of described comparer is connected with the first connected node as the input end of described 3rd control module, another input end of described comparer is connected with a reference voltage, the output terminal of described comparer is connected with the control end of described change-over switch as the output terminal of described 3rd control module
When described first connected node is not connected with plug-in calibrated resistance, the voltage of the first connected node is greater than described reference voltage, and described comparer exports the first logic level, controls change-over switch conducting; When described first connected node is connected with plug-in calibrated resistance, the voltage of the first connected node is less than described reference voltage, and described comparer exports the second logic level, controls change-over switch and turns off.
8. the output impedance Circuit tuning in interface circuit according to claim 6, is characterized in that,
Described pulling drive resistance unit also comprises the first resistance, several PMOS transistor described of described first resistance and parallel connection are series between power end and the second connected node, the sub-control signal that the grid of each PMOS transistor is all corresponding with the first control signal is connected, conducting or the shutoff of several PMOS transistor described is controlled by the sub-control signal of correspondence
Described driving resistance replication module copies described pulling drive resistance unit, the first resistance in described driving resistance replication module and several PMOS transistor described parallel with one another are series between power end and the second connected node, the sub-control signal that the grid of each PMOS transistor is all corresponding with the first control signal is connected, and can be controlled conducting or the shutoff of several PMOS transistor described by the sub-control signal of correspondence.
9., according to the output impedance Circuit tuning in the arbitrary described interface circuit of claim 1-5, it is characterized in that,
Described interface circuit is ddr interface, described second voltage end is power end, described first voltage end is earth terminal, described first output drives resistance unit to be drop-down driving resistance unit, described second output drives resistance unit to be pulling drive resistance unit, first exports driving resistance unit and drives the metal-oxide-semiconductor in resistance replication module to be NMOS tube, and described second output drives the metal-oxide-semiconductor in resistance unit to be PMOS.
10. the output impedance Circuit tuning in interface circuit according to claim 9, is characterized in that,
Described drop-down driving resistance unit also comprises the second resistance, several nmos pass transistors described of described second resistance and parallel connection are series between the second connected node and earth terminal, the sub-control signal that the grid of each nmos pass transistor is all corresponding with the first control signal is connected, conducting or the shutoff of several nmos pass transistors described can be controlled by the sub-control signal of correspondence
Described driving resistance replication module copies described drop-down driving resistance unit, described second resistance in described driving resistance replication module and several nmos pass transistors of parallel connection are series between the second connected node and earth terminal, the sub-control signal that the grid of each nmos pass transistor is all corresponding with the first control signal is connected, and is controlled conducting or the shutoff of several nmos pass transistors described by the sub-control signal of correspondence.
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| CN201520304624.2U CN204576334U (en) | 2015-05-13 | 2015-05-13 | Output impedance Circuit tuning in a kind of interface circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834341A (en) * | 2015-05-13 | 2015-08-12 | 灿芯半导体(上海)有限公司 | Output impedance regulation circuit in interface circuit |
| CN109087673A (en) * | 2018-08-01 | 2018-12-25 | 灿芯半导体(上海)有限公司 | The method of ddr interface circuit adjust automatically reference level VREF |
-
2015
- 2015-05-13 CN CN201520304624.2U patent/CN204576334U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104834341A (en) * | 2015-05-13 | 2015-08-12 | 灿芯半导体(上海)有限公司 | Output impedance regulation circuit in interface circuit |
| CN104834341B (en) * | 2015-05-13 | 2016-07-06 | 灿芯半导体(上海)有限公司 | A kind of output impedance adjustment circuit in interface circuit |
| CN109087673A (en) * | 2018-08-01 | 2018-12-25 | 灿芯半导体(上海)有限公司 | The method of ddr interface circuit adjust automatically reference level VREF |
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