CN102368661B - Switching power supply with power factor correction and its control device and method - Google Patents

Abstract

The invention discloses a switching power supply with power factor correction and its control device. The switching power supply control device includes a power factor corrector and a total harmonic distortion optimizer. The output end of the power factor corrector is connected to the The power tube is used to determine the turn-on time and turn-off time of the power tube. The input terminal of the total harmonic distortion optimizer inputs the AC input voltage, and the output terminal is connected to a power factor corrector, which can dynamically track the AC input signal, and reduce the peak current of the inductance of the switching power supply when the AC input voltage increases, Compensate the current that the AC grid charges the filter capacitor of the switching power supply; when the AC input voltage decreases, increase the peak current of the inductance of the switching power supply, and compensate the current that the AC grid discharges to the filter capacitor of the switching power supply. The control device proposed by the invention can reduce the total harmonic distortion of the AC input current caused by the filter capacitor, and improve the power factor of the switching power supply.

Description

Switching power supply with power factor correction and its control device and method

technical field

The invention relates to the field of switching power supplies, in particular to switching power supply control technology with power factor correction (Power Factor Correction, PFC).

Background technique

Converting from 220V AC (Alternating Current, AC) grid to DC (Direct Current, DC) is a basic conversion device that is widely used in power electronics technology and electronic instruments, such as computers, TVs, monitors, fluorescent lamps, etc. Commonly used electrical equipment will use AC-DC switching power supply for power supply.

At present, the commonly used AC-DC switching power supply is generally composed of a power factor correction (PFC) device and a DC-DC converter, wherein the power factor corrector is used as a pre-regulator to control the AC input current, forcing the AC input current waveform to track the AC Inputting a sinusoidal voltage waveform can make the AC input current waveform close to a sine wave.

On the one hand, the power factor corrector reduces the harmonic component of the AC input current, and the harmonic component in the AC input current will flow backwards and enter the AC grid, thereby causing harmonic pollution to the AC grid; on the other hand, it reduces the AC The total harmonic distortion (Total Harmonic Distortion, THD) of the input current improves the power factor of the switching power supply, and can make the power factor PF value close to 1.

The power factor corrector is implemented using a boost converter, which is one of the most commonly used topologies for such power factor correctors. The boost topology can work in power-demanding modes, such as continuous conduction mode (CCM), discontinuous conduction mode (DCM) and critical conduction mode (TM).

Due to the simple structure of the power factor corrector in TM mode, it is widely used in low and medium power applications. Generally speaking, the power factor corrector in TM mode can be realized in the following two ways: one is the power factor corrector in TM mode based on constant on-time control; the other is the power factor corrector in TM mode based on multiplier. These two technologies are generally considered to provide essentially the same level of performance.

As an example, as shown in FIG. 1 , a traditional switching power supply topology of a multiplier-based TM mode power factor corrector is provided. The exemplary switching power supply 100 includes a boost converter and a power factor correction device 101 . The power factor corrector is based on the TM mode structure of the multiplier.

The boost converter includes a diode full-wave rectifier bridge 103, referred to as a rectifier bridge for short. The input signal of the rectifier bridge is an AC input voltage. One end of a high-frequency filter capacitor Cin is connected to the rectifier bridge, and the other end of the filter capacitor Cin is grounded. An inductor L1 is connected to the common end of the filter capacitor Cin and the rectifier bridge, the other end of the inductor L1 is connected to the drain end of a power transistor M1, and the source end of the power transistor M1 is connected to a grounded sampling resistor Rs. The anode of a diode D1 is connected to the common end of the inductor L1 and the power transistor M1, the cathode is connected to one end of a capacitor Cbulk, and the other end of the capacitor Cbulk is grounded. The boost converter generates a DC output voltage on the capacitor Cbulk that is much greater than the maximum peak voltage of the AC input, typically 400V, and the DC output voltage is provided to a subsequent DC-DC converter.

The power factor corrector includes:

Error amplifier 104, the error amplifier compares two input signals: the input signal at its inverting input terminal is the divided voltage generated by the DC output voltage of the boost converter through resistor Rfa and resistor Rfb; the input signal at its non-inverting input terminal is the internal reference voltage VREF. The misamplification output signal Se is an amplified signal of the error between the two input signals. There is a compensation network 102 between the inverting input terminal and the output terminal of the error amplifier, which is used to determine the bandwidth of the error amplifier. If the bandwidth of the error amplifier is sufficiently narrow (for example lower than 20 Hz), the misamplified output signal Se has a DC value within a half cycle of a given AC input voltage.

A multiplier 105 to which the misplaced output signal Se is provided. The other input signal of the multiplier is the divided voltage Vi generated by the AC input voltage after being rectified by the rectifier bridge, and then passed through the resistor R1a and the resistor R1b, referred to as the rectified divided voltage signal Vi. The output signal Sm of the multiplier is the product of the two input signals. As an example, the output signal Sm of the multiplier is a voltage waveform similar to a sinusoidal full-wave rectification.

A current sense comparator 106, the output signal Sm of said multiplier is supplied to said current sense comparator as one of its input signals. The other input of the current sensing comparator is the voltage Srs generated on the sampling resistor Rs by the current flowing through the power tube, referred to as the current sampling signal Srs. In some implementations, when the current sense comparator determines that the voltages on the two inputs are equal, the current sense comparator resets the flip-flop 108 and turns off the power transistor M1. After being processed by the power factor corrector, the inductor L1 peak current of the boost converter is enveloped by a rectified sinusoidal waveform. It can be shown that the power factor corrector produces a constant on-time during a half cycle of the input AC voltage.

After power transistor M1 is turned off, diode D1 is forward biased due to current continuity. As part of the boost topology, the inductor L1 will release its stored energy to the load of the switching power supply. When the current of the inductor L1 drops to zero, the zero current detector 107 detects the zero current state of the inductor through the coupling coil L2. The output of the zero current detector is connected to the set terminal of the flip-flop. The zero current detector causes the flip-flop to be set when the zero current detector detects zero current. When the flip-flop is set, the power transistor M1 starts to conduct. During the operation of the switching power supply, the flip-flop is repeatedly set and reset.

In order to meet EMI requirements, a small high-frequency filter capacitor Cin is added behind the rectifier bridge 103 in the switching power supply. Due to the existence of the filter capacitor Cin, the switching power supply encounters the problem of crossover distortion, which increases the harmonic component of the AC input current and increases the distortion, thereby reducing the power factor of the switching power supply.

The traditional approach assumes that crossover distortion occurs during AC input voltage transitions. More specifically, crossover distortion often occurs when the AC input voltage drops near zero volts. When the AC input voltage drops close to 0 volts, the diodes of the rectifier bridge are reverse biased due to the residual residual voltage on the filter capacitor Cin, which is associated with the filter capacitor Cin and the rectifier bridge . During this period, no AC input current flows from the rectifier bridge. As a result, the waveform of the AC input current may exhibit crossover distortion effects. When the AC input voltage drops to close to 0, the voltage on the filter capacitor Cin usually deviates from the ideal value within a short period of time.

As shown in Figure 2, due to the existence of the filter capacitor Cin, distortion occurs when the rectified AC input voltage crosses zero, which will lead to distortion of the AC input current when it crosses zero, thereby increasing the distortion of the AC input current. big.

In order to reduce the effect of crossover distortion, the traditional method is to prolong the conduction time of the power transistor when the AC input voltage is very close to zero, and discharge more charges on the filter capacitor, so that The voltage distortion on the filter capacitor is reduced, so as to achieve the purpose of optimizing the total harmonic distortion of the AC input current.

However, the traditional method has some deficiencies, mainly because its analysis of the influence of the filter capacitor Cin on the total harmonic distortion of the AC input current is somewhat one-sided and not detailed enough. In fact, the main reason for the total harmonic distortion generated by the AC input current is that the filter capacitor Cin generates charging and discharging currents. This current is superimposed on the input terminal, so that the actual AC input current and the AC input voltage cannot be completely in phase. In addition, when the current provided by the filter capacitor is just able to be supplied to the output circuit when the filter capacitor is discharged, the AC grid can no longer input current, resulting in a so-called conduction dead angle.

The current above the filter capacitor is:

I _Cin ＝Cin×U ₀ ×ω×cosωt (1)

Where U ₀ is the amplitude of the AC input voltage, ω is the frequency of the input signal, and Cin is the capacitance of the filter capacitor.

When the discharge current of the filter capacitor exceeds the output current _I0 , the AC grid can no longer input current. Therefore, the conduction dead angle is:

α＝arccos(I _O /(Cin×U ₀ ×ω)) (2)

It can be seen from the formula that there is a relationship between the conduction dead angle and the AC input voltage, the filter capacitor and the output current.

As shown in FIG. 2 , the filter capacitor Cin is charged during a rising half cycle of the AC input voltage, and discharged during a falling half cycle of the AC input voltage. When the AC input voltage crosses zero, the charging and discharging current of the filter capacitor reaches the maximum value, and the current distortion generated thereby is also the maximum.

The traditional method does not take into account that the filter capacitor changes from the maximum discharge current to the maximum charge current when the voltage crosses zero, so the traditional method only prolongs the time when the AC input voltage is very close to zero. The conduction time of the power tube is to release more charge on the filter capacitor, which cannot fully compensate the charge and discharge current distortion caused by the filter capacitor, but can only compensate for the maximum discharge current of the filter capacitor. distortion.

When the filter capacitor is charging:

I _IN ＝I _CC +I _L (3)

And when the filter capacitor is discharged:

I _IN + I _CD = I _L (4)

Wherein I _IN is the AC input current, I _L is the peak current of the inductor, I _CC is the charging current of the filter capacitor, and I _CD is the discharge current of the filter current.

Since the current waveform distortion is caused by the charging and discharging of the filter capacitor, in order to optimize the total harmonic distortion, the current waveform distortion caused by the charging and discharging of the filter capacitor must be compensated.

Contents of the invention

The invention aims to solve the shortcomings of the current total harmonic distortion optimization method of the power factor corrector, and provides a switching power supply controller with power factor correction and a control method thereof. At the same time, the invention also provides a switching power supply with power factor correction.

Switching power supplies with power factor correction include:

A switching power converter converts an AC input voltage into a DC output signal. The switching power converter includes a high frequency filter capacitor, an inductor and a power tube;

A switching power supply control device, the switching power supply control device includes a power factor corrector and a total harmonic distortion optimizer, the output end of the power factor corrector is connected to the power tube to determine the conduction of the power tube time and off time. The input terminal of the total harmonic distortion optimizer inputs the AC input voltage, and the output terminal is connected to a power factor corrector, which can dynamically track the AC input signal, and when the AC input voltage increases, the peak current of the inductor is reduced to compensate The current charged by the AC grid to the filter capacitor; when the AC input voltage decreases, the peak current of the inductor is increased to compensate the current discharged by the AC grid to the filter capacitor.

The power factor corrector includes:

An error amplifier, the inverting input terminal of the error amplifier is a voltage divider of the DC output voltage of the switching power supply, and the non-inverting input terminal of the error amplifier is a reference voltage;

A multiplier, one input of the multiplier is a rectified and divided voltage signal of the AC input voltage; the other input of the multiplier is from the output signal of the error amplifier;

A current sensing comparator, which compares the output signal of the multiplier with the current sampling signal, the output of the current sensing comparator is connected to a trigger, and the output signal of the current sensing comparator determines the turn-off time of the power tube;

A zero-current detector, used to detect the zero-current state in the inductor in the switching power converter, the output of the zero-current comparator is connected to the flip-flop, and the output signal of the zero-current comparator determines the turn-on time;

A flip-flop, the output of the flip-flop is connected to the driving circuit;

A drive circuit, the output of the drive circuit is connected to the power tube.

Wherein, the current sampling signal is the voltage generated by the current of the power tube on the sampling resistor Rs;

Further, the total harmonic distortion optimizer can dynamically track the AC input signal, and reduce the value of the output signal of the multiplier or increase the value of the current sampling signal when the AC input voltage increases; When the AC input voltage decreases, the value of the output signal of the multiplier is increased, or the value of the current sampling signal is decreased.

A control method for a switching power supply with power factor correction, including:

Step 1, the AC input signal is converted into a DC output signal;

Step 2, comparing the DC output signal with the first reference signal to generate an error amplification signal;

Step 3, multiplying the error amplification signal and the AC input signal to generate a product signal;

Step 4, comparing the product signal with the sampling signal, when the sampling signal is equal to or greater than the product signal, generating a power tube shutdown signal to stop absorbing current from the inductor;

Step 5, comparing the detection signal with a second reference signal, and when the detection signal is equal to or smaller than the second reference signal, a power transistor conduction signal is generated to start absorbing current from the inductor.

When the AC input signal increases, reduce the peak current of the inductor to compensate the current charged by the AC grid to the filter capacitor; when the AC input signal decreases, increase the peak current of the inductor to compensate the AC The current discharged by the power grid to the filter capacitor.

Wherein, the sampling signal represents the current sampling signal is the voltage generated by the current of the power tube on the sampling resistor; wherein, the detection signal represents the zero current state of the inductor detected by the coupling coil.

The switching power supply and its control device proposed by the present invention can reduce the total harmonic distortion of the AC input current caused by the filter capacitor and improve the power factor of the switching power supply.

Description of drawings

Fig. 1 is the topological structure of the switching power supply of traditional power factor correction based on the TM mode of the multiplier;

Figure 2 is the input current, voltage and filter capacitor charge and discharge waveforms of the switching power supply shown in Figure 1

Fig. 3 is the topological structure of the switching power supply device with power factor correction proposed by the present invention;

Fig. 4 is the first specific embodiment of the total harmonic distortion optimizer of the present invention;

Fig. 5 is the second specific embodiment of the total harmonic distortion optimizer of the present invention;

Figure 6 is a topology of a voltage rise or fall detector;

Fig. 7 is the third specific embodiment of the total harmonic distortion optimizer of the present invention;

Fig. 8 is the 4th specific embodiment of total harmonic distortion optimizer of the present invention;

FIG. 9 is a possible topological structure of the analog circuit for charging and discharging the filter capacitor in the present invention.

Detailed ways

The essence of the invention and specific technical solutions of the present invention will be further described below in conjunction with the accompanying drawings.

Fig. 3 is a switching power supply with power factor correction proposed by the present invention, the switching power supply is based on a multiplier-based TM mode topology.

The switching power supply 300 in FIG. 3 includes a boost converter and a switching power supply control device 301:

The boost converter includes a diode full-wave rectifier bridge 303, referred to as a rectifier bridge for short. The input signal of the rectifier bridge is an AC input voltage. One end of a high-frequency filter capacitor Cin is connected to the rectifier bridge, and the other end of the filter capacitor Cin is grounded. An inductor L1 is connected to the common end of the filter capacitor Cin and the rectifier bridge, the other end of the inductor L1 is connected to the drain end of a power transistor M1, and the source end of the power transistor M1 is connected to a grounded sampling resistor Rs. The anode of a diode D1 is connected to the common end of the inductor L1 and the power transistor M1, the cathode is connected to one end of a capacitor Cbulk, and the other end of the capacitor Cbulk is grounded. The switching power converter generates a DC output voltage on the capacitor Cbulk that is much greater than the maximum peak voltage of the AC input, typically 400V, and the DC output voltage is provided to a subsequent DC-DC converter.

The switching power supply control device 301 includes a power factor corrector 311 and a total harmonic distortion optimizer 310

The power factor corrector includes:

An error amplifier 304, the error amplifier compares two input signals: the input signal at its inverting input terminal is the divided voltage generated by the DC output voltage of the switching power converter through resistor Rfa and resistor Rfb; the input signal at its non-inverting input terminal The signal is the internal reference voltage VREF. The misamplification output signal Se is an amplified signal of the error between the two input signals. There is a compensation network 302 between the inverting input and the output of the error amplifier.

A multiplier 305, the misplaced output signal Se is provided to the multiplier 305, and another input signal of the multiplier 305 is that the AC input voltage is rectified by the rectifier bridge, and then passed through the resistor R1a and the resistor R1b The generated divided voltage Vi is referred to as the rectified divided voltage signal, and the output signal Sm of the multiplier is the product of the two input signals.

A current sensing comparator 306, the output signal Sm of the multiplier is provided to the current sensing comparator as one of its input signals; the other input of the current sensing comparator is the current flowing through the power tube The voltage Srs generated on the sampling resistor Rs is called the current sampling signal for short. The output of the current sensing comparator is connected to the trigger 308, and the output signal of the current sensing comparator determines the turn-off time of the power transistor.

A zero current detector 307 is used to detect the zero current state in the inductor in the switching power converter, the output of the zero current comparator 307 is connected to the flip-flop, and the output signal of the zero current comparator determines the power tube conduction time.

A driving circuit 309, the input of the driving circuit is the output signal of the flip-flop, and the output of the driving circuit is connected to the power transistor M1.

After being processed by the power factor corrector, the inductor L1 peak current of the switching power converter is enveloped by a rectified sinusoidal waveform. For example, it can be shown that the power factor corrector produces a constant on-time during a half cycle of the input AC voltage.

After power transistor M1 is turned off, diode D1 is forward biased due to current continuity. As part of the boost topology, the inductor L1 will release its stored energy to the load of the switching power supply. When the current of the inductor L1 drops to zero, the zero current detector detects the zero current state of the inductor through the coupling coil L2. The output of the zero current detector is connected to the set terminal of the flip-flop. The zero current detector causes the flip-flop to be set when the zero current detector detects zero current. When the flip-flop is set, the power transistor M1 starts to conduct. During the operation of the switching power supply, the flip-flop is repeatedly set and reset.

The total harmonic distortion optimizer 310 receives the rectified and divided voltage signal Vi, and outputs a total harmonic distortion (THD) optimized signal Ctrl. Can dynamically track the AC input signal, when the AC input voltage increases, reduce the value of the output signal Sm of the multiplier 305, or increase the value of the current sampling signal Srs; when the AC input voltage decreases , increase the value of the output signal Sm of the multiplier 305, or decrease the value of the current sampling signal Srs. The total harmonic distortion optimizer can reduce the total harmonic distortion of the AC input current caused by the filter capacitor and improve the power factor of the switching power supply.

The switching power supply control device is a chip.

Fig. 4 is the first specific embodiment of described total harmonic distortion optimizer, and described total harmonic distortion optimizer comprises:

A subtractor 401, after subtracting the rectified and divided voltage signal Vi from a constant signal A1, passes through a weighter 402 to generate an offset compensation signal Vi1;

A voltage rise or fall detector 403, the voltage rise or fall detector judges whether the rectified and divided voltage signal Vi is in an increasing state or a decreasing state according to the rectified and divided voltage signal Vi. When the rectified and divided voltage signal Vi increases, the output total harmonic distortion (THD) optimization signal Ctrl of the voltage rising or falling detector is equal to the negative offset compensation signal Vi1; when the rectified and divided voltage signal Vi When decreasing, the output total harmonic distortion (THD) optimization signal Ctrl of the voltage rise or fall detector is equal to the positive offset compensation signal Vi1;

An adder 404 adds the total harmonic distortion (THD) optimized signal Ctrl from the output signal Sm of the multiplier 305 to the inverting input terminal of the current sense comparator 306 .

Fig. 5 is a second specific embodiment of the THD optimizer. The THD optimizer includes:

A subtractor 501, after subtracting the rectified and divided voltage signal Vi from a constant signal A1, passes through a weighter 502 to generate an offset compensation signal Vi1;

A voltage rise or fall detector 503, the voltage rise or fall detector judges whether the rectified and divided voltage signal Vi is increasing or decreasing according to the rectified and divided voltage signal Vi. When the rectified and divided voltage signal Vi increases, the output total harmonic distortion (THD) optimization signal Ctrl of the voltage rising or falling detector is equal to the negative offset compensation signal Vi1; when the rectified and divided voltage signal Vi When decreasing, the output total harmonic distortion (THD) optimization signal Ctrl of the voltage rise or fall detector is equal to the positive offset compensation signal Vi1;

A subtractor 504 subtracts the total harmonic distortion (THD) optimization signal Ctrl from the current sampling signal Srs, and provides the non-inverting input terminal of the current sense comparator 306 .

FIG. 6 is a specific embodiment of the voltage rise or fall detector shown in FIG. 4 or FIG. 5 . The basic idea of the voltage rise or fall detector 600 is to use a sample-and-hold circuit to compare with the current value to detect rising and falling waveforms: when the rising voltage is higher than a certain value (assuming 50mV) of the holding voltage, the rising edge is sampled; When the voltage is lower than a certain value of the hold voltage (assumed to be 50mV), the falling edge is sampled; when the deviation between the rising and falling voltage and the hold voltage is within a certain value (assumed to be 50mV), no sampling is performed.

The rectified and divided voltage signal Vi is provided to the level shift module 601 . The level shift module generates three level shift signals respectively: the first level shift signal V0 is equal to the rectified and divided voltage signal Vi; the second level shifted signal Va is equal to the rectified and divided voltage signal Vi plus one Deviation Δ; the third level-shifted signal Vb is equal to the rectified and divided voltage signal Vi minus a deviation Δ. The second level-shifted signal Va is provided to the down-sampling comparator 602 ; the third level-shifted signal Vb is provided to the up-sampling comparator 603 . The holding signal Vsamp on the capacitor 607 is simultaneously provided to the up-sampling comparator and the down-sampling comparator.

The down-sampling comparator compares the second level-shifted signal Va with the holding signal Vsamp, generates a down-sampling signal Vc, and provides the down-sampling signal Vc to the RS flip-flop 605 and the sampling pulse generator 604 . The up-sampling comparator compares the third level-shifted signal Vb with the holding signal Vsamp, generates an up-sampling signal Vd, and provides it to the RS flip-flop and the sampling pulse generator. The sampling pulse generator controls the switch 606 to perform sampling when the switch is closed, and the holding signal Vsamp is equal to the first level shift signal V0, that is, the rectified and divided voltage signal Vi; When on, due to the existence of the capacitor 607, it enters the hold phase. The RS flip-flop generates a judgment signal Ve.

The function of the sampling pulse generator is to output a high-level pulse with a fixed pulse width when one of the down-sampling signal Vc or the up-sampling signal Vd transitions from low to high, and close the switch. Enter the sampling phase.

The working process of the voltage increase or decrease detector is as follows: in the initial stage, the sampling pulse generator does not act, so the switch is turned off. If the rectified and divided voltage signal Vi rises, the down-sampled signal Vc is always zero. Therefore, as long as the up-sampling comparator goes high once, the judgment signal Ve is always 1, indicating that the rectified and divided voltage signal Vi is in a rising state. As long as the third level shift signal Vb is higher than the holding signal Vsamp, the up sampling comparator jumps, causing the sampling pulse generator to output a high level fixed pulse width signal to control the When the switch is closed, the rectified and divided voltage signal Vi will be sampled to the capacitor 607 . Therefore, during the rising process of the rectified and divided voltage signal Vi, the maximum difference between the signal Vsamp and the rectified and divided voltage signal Vi is kept less than Δ.

If the voltage of the rectified and divided voltage signal Vi drops, the up-sampling signal Vd is always zero. Therefore, as long as the down-sampling comparator goes high once, the judgment signal Ve is always 0, indicating that the rectified and divided voltage signal Vi is in a falling state. As long as the second level-shift signal Va is lower than the hold signal Vsamp, the down-sampling comparator jumps, causing the sampling pulse generator to output a high-level signal with a fixed pulse width to control the When the switch is closed, the voltage of the rectified and divided voltage signal Vi is sampled to the capacitor 607 . Therefore, during the falling process of the rectified and divided voltage signal Vi, the maximum difference between the signal Vsamp and the rectified and divided voltage signal Vi is kept less than Δ. The purpose of Δ setting is to prevent malfunction of the circuit.

The voltage increases or decreases the judgment signal Ve generated by the detector. That is, when the rectified and divided voltage signal Vi rises (Ve is 1), it represents the charging stage of the filter capacitor Cin, reduces the peak current of the inductor, and compensates the current for charging the filter capacitor by the AC grid; the rectified and divided voltage When the signal Vi decreases (Ve is 0), it represents the discharge stage of the filter capacitor Cin, and the peak current of the inductor is increased to compensate the current discharged by the AC grid to the filter capacitor.

Fig. 7 is the third specific embodiment of described total harmonic distortion optimizer, and described total harmonic distortion optimizer comprises:

A filter capacitor charging and discharging simulation circuit 702, which can simulate the charging and discharging process of the filter capacitor Cin according to the rectified voltage divider signal Vi and the capacitor C1 to generate a total harmonic distortion (THD) optimization signal Ctrl;

An adder 703 adds a total harmonic distortion (THD) optimization signal Ctrl from the output signal Sm of the multiplier, and provides it to the inverting input terminal of the current sense comparator 306 .

Fig. 8 is the 4th specific embodiment of described total harmonic distortion optimizer, described total harmonic distortion optimizer comprises:

A filter capacitor charging and discharging simulation circuit 802, which can simulate the charging and discharging process of the filter capacitor Cin according to the rectified voltage division signal Vi and the capacitor C1 to generate a total harmonic distortion (THD) optimization signal Ctrl;

A subtractor 803 subtracts the total harmonic distortion (THD) optimization signal Ctrl from the current sampling signal Srs, and provides it to the non-inverting input terminal of the current sense comparator 306 .

FIG. 9 is a possible topological structure of the filter capacitor charging and discharging simulation circuit shown in FIG. 7 or 8 . The base input signal of the first NPN transistor Q1 is a rectified and divided voltage signal (Vi), the collector of the first NPN transistor Q1 is connected to the power supply, and the emitter of the first NPN transistor Q1 is connected to a grounded constant current source I2. The base of the four PNP transistors Q4 is connected to the common terminal of the first NPN transistor Q1 and the constant current source I2; the base input signal of the second PNP transistor Q2 is the rectified and divided voltage signal Vi, and the collector of the second PNP transistor Q2 is connected to Ground, the emitter of the second PNP transistor Q2 is connected to a constant current source I1 connected to the power supply, the base of the third NPN transistor Q3 is connected to the common end of the second PNP transistor Q2 and the constant current source I1; the third NPN transistor Q3 The emitter of the third NPN transistor Q3 is connected to the emitter of the fourth PNP transistor Q4, connected to the first capacitor C1, and the other end of the first capacitor C1 is grounded; the collector of the third NPN transistor Q3 is connected to the first PMOS transistor M1 and The input stage of the current mirror composed of the second PMOS transistor M2; the collector of the fourth PNP transistor Q4 is connected to the input stage of the current mirror composed of the third NMOS transistor M3 and the fourth NMOS transistor M4, and the two current mirrors The output stage is connected to output the THD optimization signal (Ctrl)

The invention discloses a switching power supply device with power factor control capable of reducing crossover distortion, and describes the specific implementation and effects of the invention with reference to the accompanying drawings. It should be understood that the above-mentioned embodiments are only descriptions of the present invention, rather than limitations of the present invention, any inventions that do not exceed the scope of the spirit of the present invention, including total harmonic distortion optimizer, voltage rise or fall detector, filter Changes to the capacitance charging and discharging analog circuit and other non-substantial replacements or modifications all fall within the protection scope of the present invention.

Claims (17)

1. the Switching Power Supply with power factor correction, comprising:

One switch power converter, converts AC-input voltage to direct-flow output signal, and described switch power converter comprises rectifier bridge, fly-wheel diode, shunt capacitance, high-frequency filter capacitor, an inductance and a power tube; With a Switching Power Supply control device;

Described Switching Power Supply control device comprises a power factor corrector and a total harmonic distortion optimization device, the output of described power factor corrector connects described power tube, determine ON time and the turn-off time of described power tube, the input input AC input voltage of described total harmonic distortion optimization device, output connects power factor corrector, can dynamically follow the tracks of ac input signal, when AC-input voltage increases, reduce the peak current of described inductance, the electric current of compensation AC network to described filter capacitor charging; When AC-input voltage reduces, increase the peak current of described inductance, the electric current of compensation AC network to described filter capacitor electric discharge;

It is characterized in that, described total harmonic distortion optimization device is a kind of in following manner:

(1) described total harmonic distortion optimization device comprises:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state: when described rectification and voltage division signal Vi increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal (Vi) reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

One adder, adds the above total harmonic distortion (THD) optimization signal (Ctrl) from the output signal Sm the inside of multiplier, offers the inverting input of electric current induction comparator;

Or (2) described total harmonic distortion optimization device comprises:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state, when described rectification and voltage division signal (Vi) increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal Vi reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

A subtracter, deducts total harmonic distortion (THD) from current sampling signal (Srs) the inside and optimizes signal (Ctrl), offers the normal phase input end of electric current induction comparator.

2. there is as claimed in claim 1 the Switching Power Supply of power factor correction, it is characterized in that described power factor corrector comprises:

One error amplifier, the inverting input of described error amplifier is the dividing potential drop of the VD of Switching Power Supply, the normal phase input end of described error amplifier is reference voltage, amplifies the dividing potential drop of described VD and the error between reference voltage;

One multiplier, the rectification and voltage division signal that an input of described multiplier is AC-input voltage; Another input of described multiplier is from the output signal of described error amplifier, and multiplier is by the signal multiplication of two input;

One electric current induction comparator, the output signal of more described multiplier and current sampling signal, the output of described electric current induction comparator connects trigger, and the output signal of electric current induction comparator has determined the turn-off time of described power tube;

One zero current detector, the zero current condition in the inductance being used in sense switch power supply changeover device, the output of described zero current comparator connects described trigger, and the output signal of zero current comparator has determined the ON time of described power tube;

One trigger, the output of described trigger connects drive circuit;

One drive circuit, the output of described drive circuit connects described power tube.

3. there is as claimed in claim 2 the Switching Power Supply of power factor correction, it is characterized in that described current sampling signal is the voltage that the electric current of described power tube produces on sampling resistor.

4. there is as claimed in claim 2 the Switching Power Supply of power factor correction, it is characterized in that described total harmonic distortion optimization device, can dynamically follow the tracks of ac input signal, when AC-input voltage increases, reduce the value of the output signal of described multiplier, or increase the value of described current sampling signal; When AC-input voltage reduces, increase the value of the output signal of described multiplier, or reduce the value of described current sampling signal.

5. there is as claimed in claim 1 the Switching Power Supply of power factor correction, it is characterized in that described voltage rises or the implementation of decline detector is: described rectification and voltage division signal (Vi) is provided for to level shift module, and described level shift module produces three level shift signals respectively: the first level shift signal (V0) equals described rectification and voltage division signal (Vi), second electrical level displacement signal (Va) equals described rectification and voltage division signal (Vi) and adds a deviation delta, the 3rd level shift signal (Vb) equals described rectification and voltage division signal (Vi) and deducts a deviation delta, and described second electrical level displacement signal (Va) offers lower down-sampled comparator, described the 3rd level shift signal (Vb) offers up-samples comparator, and the inhibit signal Vsamp above electric capacity is simultaneously provided to described up-samples comparator and described lower down-sampled comparator, the described more described second electrical level displacement signal of lower down-sampled comparator (Va) and described inhibit signal (Vsamp), produce decline sampled signal (Vc) and offer rest-set flip-flop and sampling pulse generator, the 3rd level shift signal (Vb) and described inhibit signal (Vsamp) that described up-samples comparator is relatively more described, produce up-samples signal (Vd) and offer described rest-set flip-flop and described sampling pulse generator, described sampling pulse generator control switch, when described switch is closed, sample, described inhibit signal (Vsamp) equals described the first level shift signal (V0), described rectification and voltage division signal (Vi) namely, when described switch disconnects, because electric capacity exists, enter the maintenance stage, described rest-set flip-flop produces judgement signal Ve.

6. there is as claimed in claim 1 the Switching Power Supply of power factor correction, it is characterized in that the base input signal that filter capacitor discharges and recharges a NPN pipe Q1 of analog circuit is rectification and voltage division signal (Vi), the collector electrode of the one NPN pipe Q1 is received power supply, the emitter of the one NPN pipe Q1 is received the constant-current source I2 of a ground connection, and the base stage of the 4th PNP pipe Q4 is received the common port of a NPN pipe Q1 and constant-current source I2; The base input signal of the 2nd PNP pipe Q2 is rectification and voltage division signal Vi, the collector electrode of the 2nd PNP pipe Q2 is received ground, the emitter of the 2nd PNP pipe Q2 is received a constant-current source I1 who connects power supply, and the base stage of the 3rd NPN pipe Q3 is received the common port of the 2nd PNP pipe Q2 and constant-current source I1; The emitter of the 3rd NPN pipe Q3 is connected with the emitter of the 4th PNP pipe Q4, receives other one end ground connection of the first capacitor C 1, the first capacitor C 1; The collector electrode of the 3rd NPN pipe Q3 is received the input stage of the current mirror being comprised of a PMOS pipe M1 and the 2nd PMOS pipe M2; The collector electrode of the 4th PNP pipe Q4 is received the input stage of the current mirror being comprised of the 3rd NMOS pipe M3 and the 4th NMOS pipe M4, and the output stage of two current mirrors is connected, and exports described total harmonic distortion optimization signal (Ctrl).

7. the control device with the Switching Power Supply of power factor correction, comprise a power factor corrector and a total harmonic distortion optimization device: the power tube of the output connecting valve power supply of described power factor corrector, determines ON time and the turn-off time of described power tube; The input input AC input voltage of described total harmonic distortion optimization device, output connects power factor corrector, can dynamically follow the tracks of ac input signal, when AC-input voltage increases, reduce the peak current of inductance, the electric current of compensation AC network to the filter capacitor charging of Switching Power Supply; When AC-input voltage reduces, increase the peak current of Switching Power Supply inductance, the electric current of compensation AC network to the filter capacitor electric discharge of Switching Power Supply;

It is characterized in that: described total harmonic distortion optimization device is a kind of in following manner;

(1) described total harmonic distortion optimization device comprises:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state: when described rectification and voltage division signal Vi increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal (Vi) reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

One adder, adds the above total harmonic distortion (THD) optimization signal (Ctrl) from the output signal Sm the inside of multiplier, offers the inverting input of electric current induction comparator;

Or (2) described total harmonic distortion optimization device comprises:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state, when described rectification and voltage division signal (Vi) increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal Vi reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

A subtracter, deducts total harmonic distortion (THD) from current sampling signal (Srs) the inside and optimizes signal (Ctrl), offers the normal phase input end of electric current induction comparator.

8. there is as claimed in claim 7 the control device of the Switching Power Supply of power factor correction, it is characterized in that described power factor corrector comprises:

One error amplifier, the inverting input of described error amplifier is the dividing potential drop of the VD of Switching Power Supply, the normal phase input end of described error amplifier is reference voltage, amplifies the dividing potential drop of described VD and the error between reference voltage;

One multiplier, the rectification and voltage division signal that an input of described multiplier is AC-input voltage; Another input of described multiplier is from the output signal of described error amplifier, and multiplier is by the signal multiplication of two input;

One electric current induction comparator, the output signal of more described multiplier and current sampling signal, the output of described electric current induction comparator connects trigger, and the output signal of electric current induction comparator has determined the turn-off time of described power tube;

One zero current detector, the zero current condition in the inductance being used in sense switch power supply changeover device, the output of described zero current comparator connects described trigger, and the output signal of zero current comparator has determined the ON time of described power tube;

One trigger, the output of described trigger connects drive circuit;

One drive circuit, the output of described drive circuit connects described power tube.

9. there is as claimed in claim 8 the control device of the Switching Power Supply of power factor correction, it is characterized in that described current sampling signal is the voltage that the electric current of described power tube produces on sampling resistor.

10. there is as claimed in claim 8 the control device of the Switching Power Supply of power factor correction, it is characterized in that described total harmonic distortion optimization device, can dynamically follow the tracks of ac input signal, when AC-input voltage increases, reduce the value of the output signal of multiplier, or increase the value of described current sampling signal; When AC-input voltage reduces, increase the value of the output signal of described multiplier, or reduce the value of described current sampling signal.

11. have the control device of the Switching Power Supply of power factor correction as claimed in claim 7, it is characterized in that described voltage rises or the implementation of decline detector is: described rectification and voltage division signal (Vi) is provided for to level shift module, described level shift module produces three level shift signals respectively: the first level shift signal (V0) equals described rectification and voltage division signal (Vi), second electrical level displacement signal (Va) equals described rectification and voltage division signal (Vi) and adds a deviation delta, the 3rd level shift signal (Vb) equals described rectification and voltage division signal (Vi) and deducts a deviation delta, and described second electrical level displacement signal (Va) offers lower down-sampled comparator, described the 3rd level shift signal (Vb) offers up-samples comparator, and the inhibit signal above electric capacity (Vsamp) is simultaneously provided to described up-samples comparator and described lower down-sampled comparator, the described more described second electrical level displacement signal of lower down-sampled comparator (Va) and described inhibit signal (Vsamp), produce decline sampled signal (Vc) and offer rest-set flip-flop and sampling pulse generator, the 3rd level shift signal (Vb) and described inhibit signal (Vsamp) that described up-samples comparator is relatively more described, produce up-samples signal (Vd) and offer described rest-set flip-flop and described sampling pulse generator, described sampling pulse generator control switch, when described switch is closed, sample, described inhibit signal Vsamp equals described the first level shift signal (V0), described rectification and voltage division signal (Vi) namely, when described switch disconnects, because electric capacity exists, enter the maintenance stage, described rest-set flip-flop produces judgement signal (Ve).

12. have the control device of the Switching Power Supply of power factor correction as claimed in claim 7, it is characterized in that the base input signal that filter capacitor discharges and recharges a NPN pipe Q1 of analog circuit is rectification and voltage division signal (Vi), the collector electrode of the one NPN pipe Q1 is received power supply, the emitter of the one NPN pipe Q1 is received the constant-current source I2 of a ground connection, and the base stage of the 4th PNP pipe Q4 is received the common port of a NPN pipe Q1 and constant-current source I2; The base input signal of the 2nd PNP pipe Q2 is rectification and voltage division signal Vi, the collector electrode of the 2nd PNP pipe Q2 is received ground, the emitter of the 2nd PNP pipe Q2 is received a constant-current source I1 who connects power supply, and the base stage of the 3rd NPN pipe Q3 is received the common port of the 2nd PNP pipe Q2 and constant-current source I1; The emitter of the 3rd NPN pipe Q3 is connected with the emitter of the 4th PNP pipe Q4, receives other one end ground connection of the first capacitor C 1, the first capacitor C 1; The collector electrode of the 3rd NPN pipe Q3 is received the input stage of the current mirror being comprised of a PMOS pipe M1 and the 2nd PMOS pipe M2; The collector electrode of the 4th PNP pipe Q4 is received the input stage of the current mirror being comprised of the 3rd NMOS pipe M3 and the 4th NMOS pipe M4, and the output stage of two current mirrors is connected, and exports described total harmonic distortion optimization signal (Ctrl).

13. total harmonic distortion optimization devices, is characterized in that comprising:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state, when described rectification and voltage division signal (Vi) increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal Vi reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

One adder, adds the above total harmonic distortion (THD) optimization signal (Ctrl), then output from the output signal Sm the inside of multiplier.

14. total harmonic distortion optimization devices, is characterized in that comprising:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state, when described rectification and voltage division signal Vi increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal (Vi) reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

A subtracter, deducts total harmonic distortion (THD) from current sampling signal Srs the inside and optimizes signal (Ctrl), then output.

15. as described in claim 13 or 14 total harmonic distortion optimization device, it is characterized in that described voltage rises or the implementation of decline detector is: described rectification and voltage division signal (Vi) is provided for to level shift module, described level shift module produces three level shift signals respectively: the first level shift signal (V0) equals described rectification and voltage division signal (Vi), second electrical level displacement signal (Va) equals described rectification and voltage division signal (Vi) and adds a deviation delta, the 3rd level shift signal (Vb) equals described rectification and voltage division signal (Vi) and deducts a deviation delta, and described second electrical level displacement signal (Va) offers lower down-sampled comparator, described the 3rd level shift signal (Vb) offers up-samples comparator, and the inhibit signal above electric capacity (Vsamp) is simultaneously provided to described up-samples comparator and described lower down-sampled comparator, the described more described second electrical level displacement signal of lower down-sampled comparator (Va) and described inhibit signal (Vsamp), produce decline sampled signal (Vc) and offer rest-set flip-flop and sampling pulse generator, the 3rd level shift signal (Vb) and described inhibit signal (Vsamp) that described up-samples comparator is relatively more described, produce up-samples signal (Vd) and offer described rest-set flip-flop and described sampling pulse generator, described sampling pulse generator control switch, when described switch is closed, sample, described inhibit signal (Vsamp) equals described the first level shift signal (V0), described rectification and voltage division signal (Vi) namely, when described switch disconnects, because electric capacity exists, enter the maintenance stage, described rest-set flip-flop produces judgement signal (Ve).

16. have the control method of the Switching Power Supply of power factor correction, comprise the steps:

Step 1, ac input signal converts direct-flow output signal to;

Step 2, compares described direct-flow output signal and the first reference signal, produces an error amplification signal;

Step 3, multiplies each other described error amplification signal and described ac input signal to produce a product signal;

Step 4, compares described product signal and sampled signal, when described sampled signal is equal to or greater than described product signal, produces a power tube cut-off signals, stops from inductance Absorption Current;

Step 5, compares detection signal and the second reference signal, when described detection signal is equal to or less than described the second reference signal, produces a power tube Continuity signal, starts from described inductance Absorption Current;

When ac input signal increases, reduce the peak current of described inductance, the electric current of compensation AC network to filter capacitor charging; When ac input signal reduces, increase the peak current of described inductance, the electric current of compensation AC network to described filter capacitor electric discharge;

The described Switching Power Supply with power factor correction, is characterized in that: comprise a total harmonic distortion optimization device, described total harmonic distortion optimization device is a kind of in following manner;

(1) described total harmonic distortion optimization device comprises:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state: when described rectification and voltage division signal Vi increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal (Vi) reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

One adder, adds the above total harmonic distortion (THD) optimization signal (Ctrl) from the output signal Sm the inside of multiplier, offers the inverting input of electric current induction comparator;

Or (2) described total harmonic distortion optimization device comprises:

One subtracter, from a constant signal (A1), deducts rectification and voltage division signal (Vi) afterwards, through a weighter, produces an offset compensation signal (Vi1);

One voltage rises or decline detector, described voltage rising or decline detector are according to rectification and voltage division signal (Vi), judge that described rectification and voltage division signal (Vi) is in enlarging state, still reduce state, when described rectification and voltage division signal (Vi) increases, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals negative offset compensation signal (Vi1); When described rectification and voltage division signal Vi reduces, described voltage rises or the output total harmonic distortion (THD) of decline detector is optimized signal (Ctrl), equals positive offset compensation signal (Vi1);

A subtracter, deducts total harmonic distortion (THD) from current sampling signal (Srs) the inside and optimizes signal (Ctrl), offers the normal phase input end of electric current induction comparator.

17. methods as claimed in claim 16, is characterized in that:

Described sampled signal represents that current sampling signal is the voltage that the electric current of described power tube produces on sampling resistor;

Described detection signal represents that coupling coil detects the zero current condition of described inductance.

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