CN102931828B - Circuit of power factor correction and improve the method for power factor - Google Patents
Circuit of power factor correction and improve the method for power factor Download PDFInfo
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- CN102931828B CN102931828B CN201210318706.3A CN201210318706A CN102931828B CN 102931828 B CN102931828 B CN 102931828B CN 201210318706 A CN201210318706 A CN 201210318706A CN 102931828 B CN102931828 B CN 102931828B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
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Abstract
The invention provides a kind of circuit of power factor correction and improve the method for power factor, described circuit of power factor correction comprises: main circuit; Error amplifier, carries out producing the first signal after error is amplified to the output current/voltage of described main circuit; Signal tracking circuit, for generation of secondary signal, the half-sinusoid signal that in described secondary signal and described main circuit, rectifier produces is with homophase frequently; Add circuit, produces the 3rd signal after described first signal and secondary signal being added; Drive pulse signal circuit for generating, produce drive pulse signal according to described 3rd signal, described drive pulse signal is for controlling the ON/OFF of the switching tube in described main circuit.The present invention can improve the power factor of circuit of power factor correction.
Description
Technical field
The present invention relates to a kind of circuit of power factor correction and improve the method for power factor.
Background technology
At present, non-linear element in most of power consumption equipment and energy-storage travelling wave tube can make input AC current waveform generation Severe distortion, cause net side input power factor very low, in order to meet the harmonic requirement of international standard IEC61000-3-2, power factor correcting (PFC) must be added in these power consumption equipments.Traditional APFC generally adopts boosting (Boost) topology, buck (Buck-boost) topology or voltage-dropping type (Buck) topology.Wherein, Boost topology has control easily, and drive simple and can carry out the features such as switch in whole power frequency period, the power factor of input current can close to 1.But Boost topology has the high shortcoming of output voltage, and under wide region input (90Vac-265Vac) condition, can 1-3% lower than high pressure section (220Vac-265Vac) in the efficiency of low-voltage section (90Vac-110Vac).
Buck topology can keep greater efficiency in whole input voltage range, therefore has certain advantage in non-isolated application scenario, and therefore Buck type pfc circuit also receives increasing concern in recent years.But Buck topology is applied to pfc circuit, the input voltage V after rectification
inbe less than output voltage V
ointerval in, inductive current i
lwith input current i
acbe zero, as shown in Figure 1.This section of Dead Time adds Harmonics of Input largely, have impact on net side input power factor.Especially, when input voltage is lower, Buck topological circuit harmonic content is comparatively large, compares and is difficult to by some international standards.A kind of control technology being applicable to Buck-PFC of improvement is disclosed in prior art, harmonic content can be reduced, but this circuit needs to increase the voltage waveform that an auxiliary winding gathers inductance on the inductance of Buck circuit, add the design complexities of inductance, thus add circuit cost.
In isolation applications occasion, especially middle low power application scenario, the Buck-boost(Flyback of isolated form) pfc circuit is most widely used a kind of structure.If adopt discontinuous mode control mode, can realize in theory exchanging inlet wire input power factor is 1, but discontinuous mode control mode current stress is large, and main circuit switch is operated in hard switching state, and loss is larger.Therefore, what current application was more is that critical continuous conduction mode controls, the control mode that wherein can realize critical continuous conduction mode control has two kinds substantially, a kind of Power Factor Correction Control being band multiplier and input and feedovering, and another kind of control mode is that employing constant turn-on time controls.No matter the critical discontinuous mode Buck-boost(Flyback adopting which kind of control mode to realize) circuit structure, the normalized input current waveform in its half power frequency period all as shown in Figure 2, wherein s=V
o'/V
ac, V
o' be amplitude after output voltage converts transformer primary side, V
acbe AC-input voltage effective value, s is the two ratio coefficient.As seen from Figure 2, along with s diminishes, namely input voltage amplitude increases, and the wave distortion of input current is more severe, and power factor is lower.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of circuit of power factor correction and improves the method for power factor, the power factor of circuit of power factor correction can be improved, this technical scheme can either be applicable to Buck type circuit of power factor correction, is applicable to again Buck-Boost(or Flyback of critical continuous conduction mode) type circuit of power factor correction.
For solving the problems of the technologies described above, the invention provides a kind of circuit of power factor correction, comprising:
Main circuit;
Error amplifier, carries out producing the first signal after error is amplified to the output current/voltage of described main circuit;
Signal tracking circuit, for generation of secondary signal, the half-sinusoid signal that in described secondary signal and described main circuit, rectifier produces is with homophase frequently;
Add circuit, produces the 3rd signal after described first signal and secondary signal being added;
Drive pulse signal circuit for generating, produce drive pulse signal according to described 3rd signal, described drive pulse signal is for controlling the ON/OFF of the switching tube in described main circuit.
Alternatively, described signal tracking circuit comprises:
Peak-detector circuit, for the peak envelope line that obtains the electric current flowing through described switching tube using as described secondary signal.
Alternatively, described peak-detector circuit comprises:
First switch, its input is as the positive input terminal of described peak-detector circuit, and its output is as the output of described peak-detector circuit;
First electric capacity, its first end connects the output of described first switch, its second end ground connection as the negative input end of described peak-detector circuit.
Alternatively, described peak-detector circuit comprises:
First diode, its anode is as the positive input terminal of described peak-detector circuit, and its negative electrode is as the output of described peak-detector circuit;
Second electric capacity, its first end connects the negative electrode of described first diode, its second end ground connection as the negative input end of described peak-detector circuit.
Alternatively, described signal tracking circuit comprises: low pass filter, for the mean value that obtains the electric current flowing through described switching tube using as described secondary signal.
Alternatively, described low pass filter comprises the resistance-capacitance low-pass filter circuit of one-level or plural serial stage.
Alternatively, described signal tracking circuit comprises:
Low pass filter, its positive input terminal receives described drive pulse signal, its negative input end ground connection;
Peak-detector circuit, its positive input terminal connects the output of described low pass filter, its negative input end ground connection;
First resistance, its first end connects the output of described low pass filter;
Second resistance, its first end connects the output of described peak-detector circuit;
3rd resistance, its first end connects the second end of described second resistance, its second end ground connection;
First operational amplifier, its positive input terminal connects the second end of described first resistance, its negative input end connects the second end of described second resistance, and its output connects the negative input end of described first operational amplifier via the 4th resistance, and its output exports described secondary signal.
Alternatively, described circuit of power factor correction also comprises: ratio circuit, and described secondary signal transfers to described add circuit after zooming in or out via described ratio circuit.
Alternatively, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
Second diode, its negative electrode connects the output of described switching tube, and its anode connects the negative output terminal of described rectifier bridge;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connects the second end of described sampling resistor;
Output capacitance, its first end connects the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge.
Alternatively, described error amplifier comprises:
5th resistance, its first end connects the output of described switching tube;
Second operational amplifier, its negative input end connects the second end of described 5th resistance, and its output connects the negative input end of described second operational amplifier via the 4th electric capacity, and its output exports described first signal;
First reference voltage source, its one end connects the positive input terminal of described second operational amplifier, other end ground connection.
Alternatively, state drive pulse signal circuit for generating to comprise:
Zero cross detection circuit, its input connects the first end of described output capacitance, carries out zero passage detection to the voltage at described output capacitance two ends;
Saw-tooth wave generating circuit, for generation of sawtooth signal;
First comparator, its negative input end receives the 3rd signal that described add circuit exports, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described first comparator, and its positive output end is connected to the control end of described switching tube via driver module.
Alternatively, described zero cross detection circuit comprises:
6th resistance, its first end connects the first end of described output capacitance;
7th resistance, its first end connects the second end of described 6th resistance, its second end ground connection;
Second comparator, its negative input end connects the second end of described 6th resistance, and its output connects the set input of described rest-set flip-flop;
Second reference voltage source, its one end connects the positive input terminal of described second comparator, other end ground connection.
Alternatively, described saw-tooth wave generating circuit comprises:
Current source;
5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop.
Alternatively, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its vice-side winding;
Switching tube, its input connects the different name end of described former limit winding,
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
3rd diode, its anode connects the different name end of the vice-side winding of described transformer;
Output capacitance, its first end connects the negative electrode of described 3rd diode, its second end ground connection.
Alternatively, described error amplifier comprises:
8th resistance, its first end connects the first end of described output capacitance;
9th resistance, its first end connects the second end of described 8th resistance, its second end ground connection;
Tenth resistance, its first end connects the first end of described output capacitance;
6th electric capacity, its first end connects the second end of described 8th resistance;
Three end adjustable shunt reference sources, its plus earth, its negative electrode connects the second end of described 6th electric capacity, and its control end connects the second end of described 8th resistance;
Optocoupler, its first pin connects the second end of described tenth resistance, and its crus secunda connects the second end of described 6th electric capacity, and its tripod exports described first signal, its 4th pin ground connection.
Alternatively, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
Input voltage sample circuit, samples to the half-sinusoid signal that described rectifier bridge exports;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described 3rd signal;
3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module.
Alternatively, described zero cross detection circuit comprises:
11 resistance, its first end connects the different name end of the ancillary coil of described transformer;
12 resistance, its first end connects the second end of described 11 resistance, its second end ground connection;
4th comparator, its negative input end connects the second end of described 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described 3rd reference voltage source.
Alternatively, described input voltage sample circuit comprises:
13 resistance, its first end connects the positive output end of described rectifier bridge, and its second end connects the first input end of described multiplier;
14 resistance, its first end connects the second end of described 13 resistance, its second end ground connection.
Present invention also offers a kind of method improving the power factor of circuit of power factor correction, described circuit of power factor correction comprises: main circuit; Error amplifier, carries out producing the first signal after error is amplified to the output current/voltage of described main circuit; Drive pulse signal circuit for generating, for generation of drive pulse signal, described drive pulse signal is for controlling the ON/OFF of the switching tube in described main circuit; Described method comprises:
Obtain the secondary signal of the same homophase frequently of the half-sinusoid signal produced with rectifier in described main circuit;
Described first signal is superposed generation the 3rd signal with secondary signal;
By described 3rd Signal transmissions to described drive pulse signal circuit for generating, produce according to described 3rd signal to make described drive pulse signal.
Alternatively, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
Second diode, its negative electrode connects the output of described switching tube, and its anode connects the negative output terminal of described rectifier bridge;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connects the second end of described sampling resistor;
Output capacitance, its first end connects the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge;
Described error amplifier comprises:
5th resistance, its first end connects the output of described switching tube;
Second operational amplifier, its negative input end connects the second end of described 5th resistance, and its output connects the negative input end of described second operational amplifier via the 4th electric capacity, and its output exports described first signal;
First reference voltage source, its one end connects the positive input terminal of described second operational amplifier, other end ground connection;
Wherein, the inductive current flowing through described inductance transfers to described error amplifier, compare with the output voltage of described first reference voltage source, error between the mean value of described inductive current and the output voltage of described first reference voltage source produces described first signal after being exaggerated, when output current diminishes, the corresponding reduction of mean value of described inductive current, described first signal becomes large, the 3rd Signal transmissions produced after described first signal superposes with secondary signal is to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating regulates, the duty ratio of the drive pulse signal of the switch controlled end transferring to described main circuit is increased, described output current is increased, otherwise when described output current becomes large, the duty ratio of described drive pulse signal reduces, described output current is reduced.
Alternatively, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, carries out zero passage detection to the voltage at described output capacitance two ends;
Saw-tooth wave generating circuit, for generation of sawtooth signal;
First comparator, its negative input end receives the 3rd signal that described add circuit exports, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described first comparator, and its positive output end is connected to the control end of described switching tube via driver module;
Described saw-tooth wave generating circuit comprises:
Current source;
5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop;
Wherein, when described sawtooth signal rises to described 3rd signal, the output level of described first comparator turn to high level by low level, the drive pulse signal that the positive output end of described rest-set flip-flop exports is reset to low level, the high level that the negative output terminal of described rest-set flip-flop exports simultaneously controls described switching tube conducting, by the charge discharging resisting to 0 on described 5th electric capacity, the level at described 5th electric capacity two ends is lower than described 3rd signal, the output level of described first comparator turn to low level by high level, through twice upset, the output signal of described first comparator is a narrow pulse signal.
Alternatively, described zero cross detection circuit comprises:
6th resistance, its first end connects the first end of described output capacitance;
7th resistance, its first end connects the second end of described 6th resistance, its second end ground connection;
Second comparator, its negative input end connects the second end of described 6th resistance, and its output connects the set input of described rest-set flip-flop;
Second reference voltage source, its one end connects the positive input terminal of described second comparator, other end ground connection;
Wherein, interval in the shutoff of described switching tube, described inductive current declines, inductive drop is high level, when described inductive current drops to after zero, described inductive drop declines, described inductive drop is transferred to the voltage that the negative input end of described second comparator and described second reference voltage source export and compares after described 6th resistance and the 7th electric resistance partial pressure, when the voltage that the inductive drop after described 6th resistance and the 7th electric resistance partial pressure exports lower than described second reference voltage source, the output level of described second comparator turn to high level by low level, and be high level by the positive output end set of described rest-set flip-flop, make described switching tube conducting, when the voltage that the inductive drop after described 6th resistance and the 7th electric resistance partial pressure exports higher than described second reference voltage source, the output level of described second comparator turn to low level by high level, and the output pulse signal of described rest-set flip-flop is transferred to the control end of described switching tube Q1 after driver module amplifies.
Alternatively, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its vice-side winding;
Switching tube, its input connects the different name end of described former limit winding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
3rd diode, its anode connects the different name end of the vice-side winding of described transformer;
Output capacitance, its first end connects the negative electrode of described 3rd diode, its second end ground connection;
Wherein, when output voltage diminishes, the first signal that described error amplifier exports becomes large, the 3rd Signal transmissions produced after described first signal and secondary signal superpose with secondary signal is to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating regulates, the duty ratio of described drive pulse signal is increased, described output voltage is increased; Otherwise, when described output voltage becomes large, after described drive pulse signal circuit for generating regulates, the duty ratio of described drive pulse signal is reduced, described output voltage is reduced.
Alternatively, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
Input voltage sample circuit, samples to the half-sinusoid signal that described rectifier bridge exports;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described 3rd signal;
3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module;
Wherein, the voltage signal produced after the electric current of described former limit winding flows through described sampling resistor reaches the output signal of described multiplier, the output level of described 3rd comparator turn to high level by low level, the drive pulse signal that the positive output end of rest-set flip-flop exports is reset to low level, the electric current of described former limit winding declines afterwards, the voltage signal produced after the electric current of described former limit winding flows through described sampling resistor is lower than the output signal of described multiplier, the output level of described 3rd comparator turn to low level by high level, through twice upset, the output signal of described 3rd comparator is a narrow pulse signal.
Alternatively, described zero cross detection circuit comprises:
11 resistance, its first end connects the different name end of the ancillary coil of described transformer;
12 resistance, its first end connects the second end of described 11 resistance, its second end ground connection;
4th comparator, its negative input end connects the second end of described 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described 3rd reference voltage source;
Wherein, interval in the shutoff of the switching tube of described main circuit, the electric current of described vice-side winding declines, the voltage of the auxiliary winding of described transformer is high level, when the electric current of described vice-side winding drops to after zero, the voltage of described auxiliary winding is transferred to the voltage that the negative input end of described 4th comparator and described 3rd reference voltage source export and compares after described 11 resistance and the 12 electric resistance partial pressure, when the voltage that the voltage of voltage after described 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding exports lower than described 3rd reference voltage source, the output level of described 4th comparator turn to high level by low level, and be high level by the positive output end set of rest-set flip-flop, make the switching tube conducting of described main circuit, as the voltage Vdc that the voltage of voltage after described 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding exports higher than described 3rd reference voltage source, the output level of described 4th comparator turn to low level by high level, and the drive pulse signal that described rest-set flip-flop exports transfers to the control end of described main circuit switch pipe after driver module amplifies.
Compared with prior art, the present invention has the following advantages:
The circuit of power factor correction of the embodiment of the present invention and improve in the method for power factor, first the half-sinusoid signal obtained and produce after main circuit rectification is with the secondary signal of frequency homophase, afterwards the first Signal averaging that this secondary signal and error amplifier produce is produced the 3rd signal, and use the 3rd signal to replace the output signal of traditional power factor correction circuit medial error amplifier, by the 3rd Signal transmissions to drive pulse signal circuit for generating, the drive pulse signal controlling main circuit switch pipe ON/OFF is produced based on the 3rd signal, and the first signal that unconventional error amplifier exports.The technical scheme of the embodiment of the present invention can improve the power factor of circuit of power factor correction, and can be applicable to Buck-Boos(or Flyback of Buck type and critical continuous conduction mode) type circuit of power factor correction.
Accompanying drawing explanation
Fig. 1 is the working waveform figure of a kind of Buck type circuit of power factor correction in prior art;
Fig. 2 is Buck-Boost(or Flyback of a kind of critical continuous conduction mode in prior art) normalized input current waveform figure in half power frequency period of type circuit of power factor correction;
Fig. 3 is the input current waveform comparison diagram of the Buck type circuit of power factor correction after traditional Buck type circuit of power factor correction and the embodiment of the present invention are improved;
Fig. 4 is Buck-Boost(or Flyback of traditional critical continuous conduction mode) type circuit of power factor correction and the embodiment of the present invention improve after Buck-Boost(or Flyback of critical continuous conduction mode) the input current waveform comparison diagram of type circuit of power factor correction;
Fig. 5 shows a kind of signal tracking circuit of the embodiment of the present invention;
Fig. 6 shows a kind of circuit structure of the peak-detector circuit shown in Fig. 5;
Fig. 7 shows the another kind of circuit structure of the peak-detector circuit shown in Fig. 5;
Fig. 8 shows the another kind of signal tracking circuit of the embodiment of the present invention;
Fig. 9 shows a kind of circuit structure of the low pass filter shown in Fig. 8;
Figure 10 shows the another kind of circuit structure of the low pass filter shown in Fig. 8;
Figure 11 shows the third signal tracking circuit of the embodiment of the present invention;
Figure 12 is the circuit diagram of the circuit of power factor correction of first embodiment of the invention;
Figure 13 is the working waveform figure of the circuit of power factor correction shown in Figure 12;
Figure 14 is the circuit diagram of the circuit of power factor correction of second embodiment of the invention.
Figure 15 is the working waveform figure of the circuit of power factor correction shown in Figure 14.
Embodiment
Below in conjunction with specific embodiments and the drawings, the invention will be further described, but should not limit the scope of the invention with this.
Present embodiments provide a kind of method improving the power factor of circuit of power factor correction, wherein circuit of power factor correction comprises main circuit, error amplifier and drive pulse signal circuit for generating, error amplifier to the output voltage/electric current of main circuit carry out error amplify after produce the first signal, drive pulse signal circuit for generating for generation of drive pulse signal to control the ON/OFF of the switching tube in main circuit.In traditional circuit of power factor correction, the first signal that error amplifier exports is directly inputted into drive pulse signal circuit for generating in order to produce drive pulse signal, and in the method for the improvement power factor of the present embodiment, first secondary signal is obtained, this secondary signal and the interior half-sinusoid signal produced after over commutation of main circuit are with frequency homophase, afterwards the first Signal averaging that secondary signal and error amplifier export is produced the 3rd signal, again by the 3rd Signal transmissions to drive pulse signal circuit for generating, in order to produce drive pulse signal, namely the 3rd signal is adopted to replace the first Signal transmissions to drive pulse signal circuit for generating.
Are the network side current waveform adopting traditional circuit to obtain with reference to curve 30 in figure 3 and Fig. 4, Fig. 3, curve 31 is network side current waveform that the circuit of power factor correction after adopting the method for the improvement power factor of the present embodiment to improve obtains; In Fig. 4, curve 40 is the network side current waveform adopting traditional circuit to obtain, and curve 41 is network side current waveform that the circuit of power factor correction after adopting the method for the improvement power factor of the present embodiment to improve obtains.From Fig. 3 and Fig. 4, adopt the method for the improvement power factor of the present embodiment, Buck-Boost(Flyback for Buck type circuit of power factor correction and critical continuous conduction mode) type circuit of power factor correction, current waveform can both be changed, make net side input current waveform (especially when low input) closer to sine wave, thus the harmonic content reduced in electric current, improve net side power factor.
Furthermore, signal tracking circuit is adopted in the present embodiment to obtain the secondary signal of the same homophase frequently of the half-sinusoid signal produced with rectification in main circuit.With reference to figure 5, in a specific embodiment, this signal tracking circuit can comprise peak-detector circuit 101, for the peak envelope line that obtains the current i p flowing through main circuit switch pipe using as secondary signal vs, such as this peak-detector circuit 101 can be connected to the two ends of sampling resistor Rsen, and this sampling resistor Rsen connects with switching tube.Wherein, the current i p flowing through main circuit switch pipe can be former limit switching current in Flyback type circuit of power factor correction, can be the electric current flowing through switching tube or flow through inductance in Buck type and Buck-Boost type circuit of power factor correction.
Show a kind of particular circuit configurations of peak-detector circuit 101 with reference to figure 6, Fig. 6, comprising: the first switch S c, its input is as the positive input terminal of peak-detector circuit 101, and its output is as the output of peak-detector circuit 101; First electric capacity Cc, its first end connects the output of the first switch S c, its second end ground connection, and as the negative input end of peak-detector circuit 101.
Show the another kind of particular circuit configurations of peak-detector circuit 101 with reference to figure 7, Fig. 7, comprising: the first diode Dc, its anode is as the positive input terminal of peak-detector circuit 101, and its negative electrode is as the output of peak-detector circuit 101; Second electric capacity Cc, its first end connects the negative electrode of the first diode Dc, its second end ground connection, and as the negative input end of peak-detector circuit 101.
With reference to figure 8, in another specific embodiment, signal tracking circuit can comprise: low pass filter 102, for obtaining the mean value of the electric current of the switching tube flowing through main circuit, using as secondary signal Vs.Such as low pass filter 102 can be connected to sampling resistor Rsen two ends, and this sampling resistor Rsen connects with switching tube.The current i p wherein flowing through switching tube can be the former limit switching current in Flyback type circuit of power factor correction, or flows through the electric current of switching tube or flow through the electric current of inductance in Buck type and Buck-Boost type circuit of power factor correction.
With reference to figure 9, Fig. 9 shows a kind of particular circuit configurations of low pass filter 102, comprise stage resistive-capacitor low pass wave circuit, more specifically, this resistance-capacitance low-pass filter circuit comprises: resistance RL, its first end is the positive input terminal of low pass filter 102, and its second end connects the first end of electric capacity CL; Electric capacity CL, second end of its first end contact resistance RL, its second end ground connection as the negative input end of low pass filter 102.
Show the another kind of particular circuit configurations of low pass filter 102 with reference to Figure 10, Figure 10, comprise two-stage resistance-capacitance low-pass filter circuit, more specifically, this low pass filter 102 comprises: resistance RL1, and its first end is the positive input terminal of low pass filter 102; Electric capacity CL1, its first end connects second end of described resistance RL1, its second end ground connection as the negative input end of low pass filter 102; Resistance RL2, second end of its first end contact resistance RL1, its second end is as the output of low pass filter 102; Electric capacity CL2, second end of its first end contact resistance RL2, its second end ground connection.
Low pass filter 102 shown in Fig. 9 and Figure 10 comprises one-level and two-stage resistance-capacitance low-pass filter circuit respectively, but it will be appreciated by those skilled in the art that low pass filter 102 also can comprise the resistance-capacitance low-pass filter circuit of more multistage mutual cascade.
With reference to Figure 11, in another specific embodiment, signal tracking circuit can comprise: low pass filter 104, and its positive input terminal receives the drive pulse signal Vg being supplied to main circuit switch pipe control end, its negative input end ground connection; Peak-detector circuit 103, its positive input terminal connects the output of low pass filter 104, its negative input end ground connection; First resistance Rs1, its first end connects the output of low pass filter 104; Second resistance Rs2, its first end connects the output of peak-detector circuit 103; 3rd resistance Rs3, its first end connects second end of the second resistance Rs2, its second end ground connection; First operational amplifier Us, its positive input terminal connects second end of the first resistance Rs1, and its negative input end connects second end of the second resistance Rs2, and its output is via the negative input end of the 4th resistance Rs4 concatenation operation amplifier Us, and its output exports secondary signal Vs.
Its operation principle is as follows, drive pulse signal Vg is after low pass filter 104 filtering, obtain with rectification in main circuit after half-sinusoid signal with frequently, anti-phase low frequency signal, this low frequency signal obtains the maximum of this low frequency signal after peak-detector circuit 103, first resistance Rs1, second resistance Rs2, 3rd resistance Rs3, 4th resistance Rs4 and the first operational amplifier Us forms differential amplifier circuit, the output signal of low pass filter 104 and peak-detector circuit 103 is after this differential amplifier circuit, obtain with main circuit rectification after half-sinusoid signal with frequently, the secondary signal Vs of homophase.
Wherein, the particular circuit configurations of low pass filter 104 and peak-detector circuit 103 can reference diagram 6, Fig. 7, Fig. 9 and Figure 10, repeat no more here.
The secondary signal that signal tracking circuit produces transfers to add circuit, and produce tertiary circuit after the first Signal averaging produced with error amplifier, wherein add circuit can be the adder of any one structure in prior art.In addition, signal tracking circuit produce secondary signal can first zoom in or out via ratio circuit, transfer to again after the amplitude of secondary signal is adjusted to suitable scope in add circuit with the first Signal averaging.
With reference to Figure 12, Figure 12 shows the circuit structure of the circuit of power factor correction of the first embodiment, this circuit of power factor correction is Buck type, comprises main circuit, error amplifier 201, signal tracking circuit 204, ratio circuit 205, add circuit 206, drive pulse signal circuit for generating.
Wherein, main circuit comprises: AC power Vac; Rectifier bridge 200, carries out rectification to input signal and produces half-sinusoid signal Vin; Switching tube Q
1, its input connects the positive output end of rectifier bridge 200, and its control end receives drive pulse signal; Second diode Do, the output of its negative electrode connecting valve pipe Q1, its anode connects the negative output terminal of rectifier bridge 200; Sampling resistor Rsen, the output of its first end connecting valve pipe Q1, its second end ground connection; Inductance L, its first end connects second end of sampling resistor Rsen; Output capacitance Co, its first end connects the second end of inductance L, and its second end connects the negative output terminal of rectifier bridge 200, and output capacitance Co is configured in parallel with load Rload.
Rectifier bridge 200 comprises: diode D
1, D
2, D
3and D
4, wherein, diode D
1anode connect the positive pole of AC power Vac, the input of its negative pole connecting valve pipe Q1; Diode D
2anode connect the negative pole of AC power Vac, the input of its negative pole connecting valve pipe Q1; Diode D
3negative electrode connect the positive pole of AC power Vac; Diode D
4negative electrode connect the negative pole of AC power Vac, its anode connects diode D
3anode, and as the negative output terminal of rectifier bridge 200.
Error amplifier 201 comprises: the 5th resistance Rf, the output of its first end connecting valve pipe Q1; Second operational amplifier Uf, its negative input end connects second end of the 5th resistance Rf, and its output connects the negative input end of this second operational amplifier Uf via the 4th electric capacity Cf, and its output exports the first signal Vcomp; First reference voltage source Vref, its one end connects the positive input terminal of the second operational amplifier Uf, other end ground connection.
Drive pulse signal circuit for generating comprises: zero cross detection circuit 202, and its input connects the first end of output capacitance Co, carries out zero passage detection to the voltage at output capacitance Co two ends; Saw-tooth wave generating circuit 203, for generation of sawtooth signal Vsaw; First comparator Uc1, its negative input end receives the 3rd signal Vcomp2 that add circuit 206 exports, and its positive input terminal receives sawtooth signal Vsaw; Rest-set flip-flop U
rS, its set input connects the output of zero cross detection circuit 202, and its RESET input connects the output of the first comparator Uc1, and its positive output end is connected to the control end of switching tube Q1 via driver module Drv.
Wherein, zero cross detection circuit 202 comprises: the 6th resistance R
k2, its first end connects the first end of output capacitance Co; 7th resistance R
k1, its first end connects the 6th resistance R
k2the second end, its second end ground connection; Second comparator U
c2, its negative input end connects the 6th resistance R
k2the second end, its output connects rest-set flip-flop U
rSset input; Second reference voltage source Vdc, its one end connects the second comparator U
c2positive input terminal, other end ground connection.
Saw-tooth wave generating circuit 203 comprises: current source I
1; 5th electric capacity C
1, its first end connects current source I
1output, its second end ground connection; Second switch S
1, with the 5th electric capacity C
1parallel connection, its control end connects rest-set flip-flop U
rSnegative output terminal.
In the present embodiment, signal tracking circuit 204 comprises low pass filter, its positive input terminal connecting valve pipe Q
1output, its negative input end ground connection, low pass filter export secondary signal Vs zoom in or out via ratio circuit 205 after transfer to add circuit 206.Wherein the concrete structure of low pass filter 204 please refer to previously described content.
The working waveform figure of this circuit of power factor correction as shown in figure 13, is described in detail to the operation principle of this circuit of power factor correction below in conjunction with Figure 12 and Figure 13.
Error amplifier 201 is used for realizing the current constant control of output current: the inductive current ip flowing through main circuit inductance L transfers to error amplifier 201, compare with the first reference voltage source Vref of setting, the error between the mean value of inductive current ip and the first reference voltage source Vref exports error signal (i.e. the first signal) Vcomp of amplification after error amplifier 201 amplifies.Because the mean value of inductive current ip equals output current, when output current diminishes, the mean value of inductive current ip also can correspondingly reduce, error between the reference voltage V ref that the mean value of inductive current ip and the first reference voltage source Vref export is amplified through error amplifier 201, the output signal Vcomp of error amplifier 201 is made to become large, after drive pulse signal circuit for generating regulates, the duty ratio of the gate driving pulse signal of main circuit switch pipe Q1 is increased, thus output current is increased, complete closed-loop adjustment, otherwise, when output current becomes large, through the closed-loop adjustment of error amplifier 201 and drive pulse signal circuit for generating, output current can be made equally to turn down.
Low pass filter 204 and ratio circuit 205 are mainly used to produce the 3rd signal improving circuit power factor: inductive current ip is after low pass filter 204 filtering, obtain half-sinusoid signal (i.e. secondary signal) Vs of the voltage Vin after rectifier bridge 200 rectification formed with diode D1, D2, D3 and D4 with frequency, homophase, the error signal Vcomp exported with error amplifier 201 after ratio circuit 103 zooms in or out produces the 3rd signal Vcomp2 after add circuit 206 superposes.
Saw-tooth wave generating circuit 203 mainly produces sawtooth signal Vsaw: current source I1 and produces sawtooth signal Vsaw to the 5th electric capacity C1 charging, touches the 3rd signal Vcomp2, the first comparator U when sawtooth signal Vsaw rises to
c1output level turn to high level by low level, by rest-set flip-flop U
rSthe drive pulse signal that exports of anode (Q end) be reset to low level, U simultaneously
rSnegative terminal (
end) the high level control switch pipe Q1 conducting that exports, by the 5th electric capacity C
1on charge discharging resisting to 0, the 5th electric capacity C
1the level at two ends lower than the 3rd signal Vcomp2, the first comparator U
c1output level turn to low level by high level; Therefore through twice switching process, the first comparator U
c1output signal be a narrow pulse signal.
Zero cross detection circuit 202 is used for detecting the zero crossing of output current, and at the near zero-crossing point of output current by open-minded for the switching tube Q1 of main circuit: interval in the shutoff of main circuit switch pipe Q1, inductive current ip declines, inductive drop u
lfor high level, as shown in figure 13.When inductive current ip drops to after zero, inductive drop u
ldecline, the voltage u at the inductance L two ends of main circuit
lthrough resistance R
k2with resistance R
k1the second comparator U is transferred to after dividing potential drop
c2negative input end and the voltage that exports of reference voltage source Vdc compare, when through resistance R
k2with resistance R
k1inductive drop u after dividing potential drop
llower than the voltage Vdc that reference voltage source Vdc exports, comparator U
c2output level turn to high level by low level, and by rest-set flip-flop U
rSpositive output end (Q end) set be high level, make main circuit switch pipe Q1 open-minded; When through resistance R
k2with resistance R
k1the voltage Vdc that inductive drop after dividing potential drop exports higher than reference voltage source Vdc, the second comparator U
c2output level turn to low level by high level; Rest-set flip-flop U
rSoutput pulse signal through driver module Drv amplify after be transferred to the grid (i.e. control end) of main circuit switch pipe Q1 as drive pulse signal.
As shown in Figure 12 and Figure 13, if there is no low pass filter 204, ratio circuit 205 and add circuit 206, circuit shown in Figure 12 is the Buck type circuit of power factor correction of the critical continuous conduction mode that traditional constant turn-on time controls, basic power factor emendation function can be realized equally, but the net side input current iac obtained is as shown in the i ' ac in Figure 13, i ' ac has larger harmonic content, causes net side power factor lower.Adopt the circuit structure of the present embodiment, by introducing low pass filter 204, ratio circuit 205 and add circuit 206, the signal compared with saw-tooth wave generating circuit 203 is made to become the 3rd signal Vcomp2 by the first signal Vcomp, drive pulse signal makes the mode of operation of switching tube Q1 be no longer constant turn-on time, but along with input voltage waveform change, at crest place, there is larger ON time, the net side input current iac now obtained is as shown in the iac in Figure 13, current waveform is comparatively close to sinusoidal, current harmonic content is lower, net side power factor is improved.
Although in the first embodiment shown in Figure 12, what signal tracking circuit adopted is low pass filter 204, it will be appreciated by those skilled in the art that the signal tracking circuit shown in Fig. 5, Fig. 8 and Figure 11 is all applicable to the circuit of power factor correction shown in Figure 12.
Figure 14 shows the circuit diagram of the circuit of power factor correction of the second embodiment, this circuit of power factor correction is the single-stage flyback power factor correction circuit that critical continuous conduction mode controls, and comprises main circuit, error amplifier 301, signal tracking circuit 304, ratio circuit 305, add circuit 306, drive pulse signal circuit for generating.
Wherein, main circuit comprises: rectifier bridge B
1, rectification is carried out to input signal and produces half-sinusoid signal; Input capacitance Cin, its one end connects rectifier bridge B
1positive output end, the other end connects rectifier bridge B
1negative output terminal; Transformer T, the Same Name of Ends of its former limit winding connects rectifier bridge B
1positive output end, the Same Name of Ends ground connection of its vice-side winding; Switching tube Q
1, its input connects the different name end of former limit winding; Sampling resistor Rsen, its first end connecting valve pipe Q
1output, its second end ground connection; 3rd diode Do, the different name end of the vice-side winding of its anode connection transformer; Output capacitance Co, its first end connects the negative electrode of the 3rd diode Do, and its second end ground connection, output capacitance Co is configured in parallel with load Rload.
Error amplifier 301 comprises: the 8th resistance R
h1, its first end connects the first end of output capacitance Co; 9th resistance R
h2, its first end connects the 8th resistance R
h1the second end, its second end ground connection; Tenth resistance R
h3, its first end connects the first end of output capacitance Co; 6th electric capacity C
k1, its first end connects the 8th resistance R
h1the second end; Three end adjustable shunt reference source TL, its plus earth, its negative electrode connects the 6th electric capacity C
k1the second end, its control end connect the 8th resistance R
h1the second end, in the present embodiment, the model of three end adjustable shunt reference source TL is TL431; Optocoupler U
k1, its first pin connects the tenth resistance R
h3the second end, its crus secunda connect the 6th electric capacity C
k1the second end, its tripod exports the first signal Vcomp, its 4th pin ground connection.
Drive pulse signal circuit for generating comprises: zero cross detection circuit 303, and its input is connected with the different name end of the auxiliary winding of transformer T, the Same Name of Ends ground connection of this auxiliary winding; Input voltage sample circuit 302, to rectifier bridge B
1the half-sinusoid signal exported is sampled; Multiplier U
k2, its first input end connects the output of input voltage sample circuit 302, and the second input receives the 3rd signal Vcomp2 that add circuit 306 exports; 3rd comparator U
c1, its negative input end connects multiplier U
k2output, the output of its positive input terminal connecting valve pipe Q1; Rest-set flip-flop U
rS, its RESET input connects the 3rd comparator U
c1output, its set input connects the output of zero cross detection circuit 303, and its positive output end is via driver module Drv connecting valve pipe Q
1control end.
Zero cross detection circuit 303 comprises: the 11 resistance R
k2, the different name end of the ancillary coil of its first end connection transformer T; 12 resistance R
k1, its first end connects the 11 resistance R
k2the second end, its second end ground connection; 4th comparator U
c2, its negative input end connects the 11 resistance R
k2the second end, its positive input terminal connects the first end of the 3rd reference voltage source Vdc, and its output connects rest-set flip-flop U
rSset input, the second end ground connection of the 3rd reference voltage source Vdc.
Input voltage sample circuit 302 comprises: the 13 resistance R
t1, its first end connects rectifier bridge B
1positive output end, its second end connects multiplier U
k2first input end; 14 resistance R
t2, its first end connects the 13 resistance R
t1the second end, its second end ground connection.
In this embodiment, signal tracking circuit 304 comprises peak-detector circuit, its positive input terminal connecting valve pipe Q
1output, its negative input end ground connection, peak-detector circuit 304 export secondary signal Vs zoom in or out via ratio circuit 305 after transfer to add circuit 306.Wherein the concrete structure of peak-detector circuit 304 please refer to previously described content.
The working waveform figure of the circuit of power factor correction shown in Figure 14 as shown in figure 15, is described in detail to the operation principle of this circuit of power factor correction below in conjunction with Figure 14 and Figure 15.
In fig. 14, error amplifier 301 is used for detecting output voltage, and the change of output voltage amplification is used for voltage stabilizing control.Peak-detector circuit 304 is used for obtaining the envelope of primary current peak value, and error amplification signal (i.e. the first signal) Vcomp exported with error amplifier 301 through ratio circuit 305 scale amplifying or the secondary signal Vs that obtains after reducing is undertaken superposing by add circuit 306 and obtains the 3rd signal Vcomp2.Input voltage sample circuit 302 is used for obtaining the rectifier bridge B of main circuit
1half-sinusoid signal after rectification; Multiplier U
k2the 3rd signal Vcomp2 that the half-sinusoid signal exported by input voltage sample circuit 302 and add circuit 306 export is multiplied, and obtains the reference signal multi that primary current signal ip follows.
Primary current signal ip flows through the output signal multi that voltage signal that sampling resistor Rsen induces reaches multiplier Uk2, the 3rd comparator U
c1output level turn to high level by low level, by rest-set flip-flop U
rSthe drive pulse signal that exports of anode (Q end) be reset to low level, after this primary current signal ip declines, when primary current signal ip flows through voltage signal that sampling resistor Rsen the induces output signal multi lower than multiplier Uk2, the 3rd comparator U
c1output level turn to low level by high level; Therefore through twice switching process, the 3rd comparator U
c1output signal be a narrow pulse signal.
Zero cross detection circuit 303 is used for detecting the zero crossing of output current, and at the near zero-crossing point of output current by open-minded for the switching tube Q1 of main circuit: interval in the shutoff of main circuit switch pipe Q1, secondary current is declines, the auxiliary winding voltage u of transformer
auxfor high level, as shown in figure 15.When secondary current is drops to after zero, transformer auxiliary winding voltage u
auxthrough resistance R
k2with resistance R
k1the 4th comparator U is transferred to after dividing potential drop
c2negative input end and the voltage that exports of reference voltage source Vdc compare, as auxiliary winding voltage u
auxthrough resistance R
k2with resistance R
k1the voltage Vdc that voltage after dividing potential drop exports lower than reference voltage source Vdc, the 4th comparator U
c2output level turn to high level by low level, and by rest-set flip-flop U
rSpositive output end (Q end) set be high level, make main circuit switch pipe Q1 open-minded; As auxiliary winding voltage u
auxthrough resistance R
k2with resistance R
k1the voltage Vdc that inductive drop after dividing potential drop exports higher than reference voltage source Vdc, the 4th comparator U
c2output level turn to low level by high level; Rest-set flip-flop U
rSoutput pulse signal through driver module Drv amplify after be transferred to the grid (i.e. control end) of main circuit switch pipe Q1 as drive pulse signal.
When output voltage diminishes, the output signal Vcomp of error amplifier 301 becomes large, after drive pulse signal circuit for generating regulates, the duty ratio of the drive pulse signal of the grid of the switching tube Q1 of main circuit is increased, thus output voltage is increased, complete closed-loop adjustment; Otherwise, when output voltage becomes large, through the closed-loop adjustment of error amplifier 301 and drive pulse signal circuit for generating, output voltage can be made equally to diminish.
As shown in figure 14, if there is no peak-detector circuit 304, ratio circuit 305 and add circuit 306, circuit shown in Figure 14 is the flyback pfc circuit of traditional critical continuous conduction mode, basic power factor emendation function can be realized equally, but when input voltage is lower, net side input current i ' ac will have larger harmonic content, causes net side power factor lower, as shown in figure 15.Adopt the circuit structure of the present embodiment, by introducing peak-detector circuit 304, ratio circuit 305 and add circuit 306, can make net side input current iac waveform especially when input voltage is lower closer to sine wave, thus reduction current harmonic content, improve net side power factor, as shown in figure 15.
Although in the second embodiment shown in Figure 14, what signal tracking circuit adopted is peak-detector circuit 204, but it will be appreciated by those skilled in the art that the signal tracking circuit shown in Fig. 5, Fig. 8 and Figure 11 is all applicable to the circuit of power factor correction shown in Figure 14.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (25)
1. a circuit of power factor correction, is characterized in that, comprising:
Main circuit;
Error amplifier, carries out producing the first signal after error is amplified to the output current/voltage of described main circuit;
Signal tracking circuit, for generation of secondary signal, described secondary signal is the half-sinusoid signal of the same homophase frequently of half-sinusoid signal produced with rectifier in described main circuit;
Add circuit, produces the 3rd signal after described first signal and secondary signal being added;
Drive pulse signal circuit for generating, produce drive pulse signal according to described 3rd signal, described drive pulse signal is for controlling the ON/OFF of the switching tube in described main circuit.
2. circuit of power factor correction according to claim 1, is characterized in that, described signal tracking circuit comprises:
Peak-detector circuit, for the peak envelope line that obtains the electric current flowing through described switching tube using as described secondary signal.
3. circuit of power factor correction according to claim 2, is characterized in that, described peak-detector circuit comprises:
First switch, its input is as the positive input terminal of described peak-detector circuit, and its output is as the output of described peak-detector circuit;
First electric capacity, its first end connects the output of described first switch, its second end ground connection as the negative input end of described peak-detector circuit.
4. circuit of power factor correction according to claim 2, is characterized in that, described peak-detector circuit comprises:
First diode, its anode is as the positive input terminal of described peak-detector circuit, and its negative electrode is as the output of described peak-detector circuit;
Second electric capacity, its first end connects the negative electrode of described first diode, its second end ground connection as the negative input end of described peak-detector circuit.
5. circuit of power factor correction according to claim 1, is characterized in that, described signal tracking circuit comprises:
Low pass filter, for the mean value that obtains the electric current flowing through described switching tube using as described secondary signal.
6. circuit of power factor correction according to claim 5, is characterized in that, described low pass filter comprises the resistance-capacitance low-pass filter circuit of one-level or plural serial stage.
7. circuit of power factor correction according to claim 1, is characterized in that, described signal tracking circuit comprises:
Low pass filter, its positive input terminal receives described drive pulse signal, its negative input end ground connection;
Peak-detector circuit, its positive input terminal connects the output of described low pass filter, its negative input end ground connection;
First resistance, its first end connects the output of described low pass filter;
Second resistance, its first end connects the output of described peak-detector circuit;
3rd resistance, its first end connects the second end of described second resistance, its second end ground connection;
First operational amplifier, its positive input terminal connects the second end of described first resistance, its negative input end connects the second end of described second resistance, and its output connects the negative input end of described first operational amplifier via the 4th resistance, and its output exports described secondary signal.
8. circuit of power factor correction according to any one of claim 1 to 7, is characterized in that, also comprises:
Ratio circuit, described secondary signal transfers to described add circuit after zooming in or out via described ratio circuit.
9. circuit of power factor correction according to claim 1, is characterized in that, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
Second diode, its negative electrode connects the output of described switching tube, and its anode connects the negative output terminal of described rectifier bridge;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connects the second end of described sampling resistor;
Output capacitance, its first end connects the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge.
10. circuit of power factor correction according to claim 9, is characterized in that, described error amplifier comprises:
5th resistance, its first end connects the output of described switching tube;
Second operational amplifier, its negative input end connects the second end of described 5th resistance, and its output connects the negative input end of described second operational amplifier via the 4th electric capacity, and its output exports described first signal;
First reference voltage source, its one end connects the positive input terminal of described second operational amplifier, other end ground connection.
11. circuit of power factor correction according to claim 9, is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, carries out zero passage detection to the voltage at described output capacitance two ends;
Saw-tooth wave generating circuit, for generation of sawtooth signal;
First comparator, its negative input end receives the 3rd signal that described add circuit exports, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described first comparator, and its positive output end is connected to the control end of described switching tube via driver module.
12. circuit of power factor correction according to claim 11, is characterized in that, described zero cross detection circuit comprises:
6th resistance, its first end connects the first end of described output capacitance;
7th resistance, its first end connects the second end of described 6th resistance, its second end ground connection;
Second comparator, its negative input end connects the second end of described 6th resistance, and its output connects the set input of described rest-set flip-flop;
Second reference voltage source, its one end connects the positive input terminal of described second comparator, other end ground connection.
13. circuit of power factor correction according to claim 11, is characterized in that, described saw-tooth wave generating circuit comprises:
Current source;
5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop.
14. circuit of power factor correction according to claim 1, is characterized in that, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its vice-side winding;
Switching tube, its input connects the different name end of described former limit winding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
3rd diode, its anode connects the different name end of the vice-side winding of described transformer;
Output capacitance, its first end connects the negative electrode of described 3rd diode, its second end ground connection.
15. circuit of power factor correction according to claim 14, is characterized in that, described error amplifier comprises:
8th resistance, its first end connects the first end of described output capacitance;
9th resistance, its first end connects the second end of described 8th resistance, its second end ground connection;
Tenth resistance, its first end connects the first end of described output capacitance;
6th electric capacity, its first end connects the second end of described 8th resistance;
Three end adjustable shunt reference sources, its plus earth, its negative electrode connects the second end of described 6th electric capacity, and its control end connects the second end of described 8th resistance;
Optocoupler, its first pin connects the second end of described tenth resistance, and its crus secunda connects the second end of described 6th electric capacity, and its tripod exports described first signal, its 4th pin ground connection.
16. circuit of power factor correction according to claim 14, is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
Input voltage sample circuit, samples to the half-sinusoid signal that described rectifier bridge exports;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described 3rd signal;
3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module.
17. circuit of power factor correction according to claim 16, is characterized in that, described zero cross detection circuit comprises:
11 resistance, its first end connects the different name end of the ancillary coil of described transformer;
12 resistance, its first end connects the second end of described 11 resistance, its second end ground connection;
4th comparator, its negative input end connects the second end of described 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described 3rd reference voltage source.
18. circuit of power factor correction according to claim 16, is characterized in that, described input voltage sample circuit comprises:
13 resistance, its first end connects the positive output end of described rectifier bridge, and its second end connects the first input end of described multiplier;
14 resistance, its first end connects the second end of described 13 resistance, its second end ground connection.
19. 1 kinds of methods improving the power factor of circuit of power factor correction, described circuit of power factor correction comprises: main circuit; Error amplifier, carries out producing the first signal after error is amplified to the output current/voltage of described main circuit; Drive pulse signal circuit for generating, for generation of drive pulse signal, described drive pulse signal is for controlling the ON/OFF of the switching tube in described main circuit; It is characterized in that, described method comprises:
Obtain secondary signal, described secondary signal is the half-sinusoid signal of the same homophase frequently of half-sinusoid signal produced with rectifier in described main circuit;
Described first signal is superposed generation the 3rd signal with secondary signal;
By described 3rd Signal transmissions to described drive pulse signal circuit for generating, produce according to described 3rd signal to make described drive pulse signal.
20. methods according to claim 19, is characterized in that, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Switching tube, its input connects the positive output end of described rectifier bridge, and its control end receives described drive pulse signal;
Second diode, its negative electrode connects the output of described switching tube, and its anode connects the negative output terminal of described rectifier bridge;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
Inductance, its first end connects the second end of described sampling resistor;
Output capacitance, its first end connects the second end of described inductance, and its second end connects the negative output terminal of described rectifier bridge;
Described error amplifier comprises:
5th resistance, its first end connects the output of described switching tube;
Second operational amplifier, its negative input end connects the second end of described 5th resistance, and its output connects the negative input end of described second operational amplifier via the 4th electric capacity, and its output exports described first signal;
First reference voltage source, its one end connects the positive input terminal of described second operational amplifier, other end ground connection;
Wherein, the inductive current flowing through described inductance transfers to described error amplifier, compare with the output voltage of described first reference voltage source, error between the mean value of described inductive current and the output voltage of described first reference voltage source produces described first signal after being exaggerated, when output current diminishes, the corresponding reduction of mean value of described inductive current, described first signal becomes large, the 3rd Signal transmissions produced after described first signal superposes with secondary signal is to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating regulates, the duty ratio of the drive pulse signal of the switch controlled end transferring to described main circuit is increased, described output current is increased, otherwise when described output current becomes large, the duty ratio of described drive pulse signal reduces, described output current is reduced.
21. methods according to claim 19, is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input connects the first end of described output capacitance, carries out zero passage detection to the voltage at described output capacitance two ends;
Saw-tooth wave generating circuit, for generation of sawtooth signal;
First comparator, its negative input end receives described 3rd signal, and its positive input terminal receives described sawtooth signal;
Rest-set flip-flop, its set input connects the output of described zero cross detection circuit, and its RESET input connects the output of described first comparator, and its positive output end is connected to the control end of described switching tube via driver module;
Described saw-tooth wave generating circuit comprises:
Current source;
5th electric capacity, its first end connects the output of described current source, its second end ground connection;
Second switch, with described 5th Capacitance parallel connection, its control end connects the negative output terminal of described rest-set flip-flop;
Wherein, when described sawtooth signal rises to described 3rd signal, the output level of described first comparator turn to high level by low level, the drive pulse signal that the positive output end of described rest-set flip-flop exports is reset to low level, the high level that the negative output terminal of described rest-set flip-flop exports simultaneously controls described switching tube conducting, by the charge discharging resisting to 0 on described 5th electric capacity, the level at described 5th electric capacity two ends is lower than described 3rd signal, the output level of described first comparator turn to low level by high level, through twice upset, the output signal of described first comparator is a narrow pulse signal.
22. methods according to claim 21, is characterized in that, described zero cross detection circuit comprises:
6th resistance, its first end connects the first end of described output capacitance;
7th resistance, its first end connects the second end of described 6th resistance, its second end ground connection;
Second comparator, its negative input end connects the second end of described 6th resistance, and its output connects the set input of described rest-set flip-flop;
Second reference voltage source, its one end connects the positive input terminal of described second comparator, other end ground connection;
Wherein, interval in the shutoff of described switching tube, inductive current declines, inductive drop is high level, when described inductive current drops to after zero, described inductive drop declines, described inductive drop is transferred to the voltage that the negative input end of described second comparator and described second reference voltage source export and compares after described 6th resistance and the 7th electric resistance partial pressure, when the voltage that the inductive drop after described 6th resistance and the 7th electric resistance partial pressure exports lower than described second reference voltage source, the output level of described second comparator turn to high level by low level, and be high level by the positive output end set of described rest-set flip-flop, make described switching tube conducting, when the voltage that the inductive drop after described 6th resistance and the 7th electric resistance partial pressure exports higher than described second reference voltage source, the output level of described second comparator turn to low level by high level, and the output pulse signal of described rest-set flip-flop is transferred to the control end of described switching tube Q1 after driver module amplifies.
23. methods according to claim 19, is characterized in that, described main circuit comprises:
Rectifier bridge, carries out rectification to input signal and produces described half-sinusoid signal;
Transformer, the Same Name of Ends of its former limit winding connects the positive output end of described rectifier bridge, the Same Name of Ends ground connection of its vice-side winding;
Switching tube, its input connects the different name end of described former limit winding;
Sampling resistor, its first end connects the output of described switching tube, its second end ground connection;
3rd diode, its anode connects the different name end of the vice-side winding of described transformer;
Output capacitance, its first end connects the negative electrode of described 3rd diode, its second end ground connection;
Wherein, when output voltage diminishes, the first signal that described error amplifier exports becomes large, the 3rd Signal transmissions produced after described first signal and secondary signal superpose with secondary signal is to described drive pulse signal circuit for generating, after described drive pulse signal circuit for generating regulates, the duty ratio of described drive pulse signal is increased, described output voltage is increased; Otherwise, when described output voltage becomes large, after described drive pulse signal circuit for generating regulates, the duty ratio of described drive pulse signal is reduced, described output voltage is reduced.
24. methods according to claim 23, is characterized in that, described drive pulse signal circuit for generating comprises:
Zero cross detection circuit, its input is connected with the different name end of the auxiliary winding of described transformer, the Same Name of Ends ground connection of described auxiliary winding;
Input voltage sample circuit, samples to the half-sinusoid signal that described rectifier bridge exports;
Multiplier, its first input end connects the output of described input voltage sample circuit, and the second input receives described 3rd signal;
3rd comparator, its negative input end connects the output of described multiplier, and its positive input terminal connects the output of described switching tube;
Rest-set flip-flop, its RESET input connects the output of described 3rd comparator, and its set input connects the output of described zero cross detection circuit, and its positive output end connects the control end of described switching tube via driver module;
Wherein, the voltage signal produced after the electric current of described former limit winding flows through described sampling resistor reaches the output signal of described multiplier, the output level of described 3rd comparator turn to high level by low level, the drive pulse signal that the positive output end of rest-set flip-flop exports is reset to low level, the electric current of described former limit winding declines afterwards, the voltage signal produced after the electric current of described former limit winding flows through described sampling resistor is lower than the output signal of described multiplier, the output level of described 3rd comparator turn to low level by high level, through twice upset, the output signal of described 3rd comparator is a narrow pulse signal.
25. methods according to claim 24, is characterized in that, described zero cross detection circuit comprises:
11 resistance, its first end connects the different name end of the ancillary coil of described transformer;
12 resistance, its first end connects the second end of described 11 resistance, its second end ground connection;
4th comparator, its negative input end connects the second end of described 11 resistance, and its positive input terminal connects the first end of the 3rd reference voltage source, and its output connects the set input of described rest-set flip-flop, the second end ground connection of described 3rd reference voltage source;
Wherein, interval in the shutoff of the switching tube of described main circuit, the electric current of described vice-side winding declines, the voltage of the auxiliary winding of described transformer is high level, when the electric current of described vice-side winding drops to after zero, the voltage of described auxiliary winding is transferred to the voltage that the negative input end of described 4th comparator and described 3rd reference voltage source export and compares after described 11 resistance and the 12 electric resistance partial pressure, when the voltage that the voltage of voltage after described 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding exports lower than described 3rd reference voltage source, the output level of described 4th comparator turn to high level by low level, and be high level by the positive output end set of rest-set flip-flop, make the switching tube conducting of described main circuit, as the voltage Vdc that the voltage of voltage after described 11 resistance and the 12 electric resistance partial pressure of described auxiliary winding exports higher than described 3rd reference voltage source, the output level of described 4th comparator turn to low level by high level, and the drive pulse signal that described rest-set flip-flop exports transfers to the control end of described main circuit switch pipe after driver module amplifies.
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| CN103280964B (en) * | 2013-05-27 | 2015-10-28 | 奇瑞汽车股份有限公司 | A kind of circuit of power factor correction |
| CN104716836B (en) * | 2013-12-12 | 2017-04-05 | 杭州士兰微电子股份有限公司 | The control circuit and control method of switching power converters |
| CN105338681B (en) * | 2014-06-20 | 2018-03-02 | 中航（重庆）微电子有限公司 | Current stabilization drive device |
| CN104518657B (en) * | 2014-12-26 | 2017-03-01 | 深圳市宝安任达电器实业有限公司 | Three-phase full digital power factor correction method and circuit |
| US9768686B2 (en) * | 2014-12-31 | 2017-09-19 | Dialog Semiconductor Inc. | Feedback scheme for non-isolated power supply |
| CN104617761B (en) * | 2015-01-21 | 2017-04-05 | 江苏银河电子股份有限公司 | A kind of buck power factor correction converter of High Power Factor |
| CN105827123B (en) * | 2016-05-20 | 2018-08-21 | 杰华特微电子（杭州）有限公司 | Power converting circuit and its drive control circuit |
| CN106329906A (en) * | 2016-09-18 | 2017-01-11 | 浙江芯迈电子科技有限公司 | Voltage conversion circuit realizing automatic power factor correction |
| CN111800000B (en) * | 2020-08-05 | 2025-03-11 | 成都锐能科技有限公司 | A power factor adjustment circuit for aircraft |
| CN112290898B (en) * | 2020-09-15 | 2022-12-20 | 复旦大学 | A Down-Sampling and Control Circuit Applied to Envelope Tracking Power Supply Modulator |
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