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CN102339808B - Packaging lead frame structure - Google Patents

Packaging lead frame structure Download PDF

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Publication number
CN102339808B
CN102339808B CN 201110332730 CN201110332730A CN102339808B CN 102339808 B CN102339808 B CN 102339808B CN 201110332730 CN201110332730 CN 201110332730 CN 201110332730 A CN201110332730 A CN 201110332730A CN 102339808 B CN102339808 B CN 102339808B
Authority
CN
China
Prior art keywords
chip
molybdenum sheet
dao
coated
glue layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN 201110332730
Other languages
Chinese (zh)
Other versions
CN102339808A (en
Inventor
侯友良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Red Microelectronics Co ltd
Original Assignee
Wuxi Red Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Red Microelectronics Co ltd filed Critical Wuxi Red Microelectronics Co ltd
Priority to CN 201110332730 priority Critical patent/CN102339808B/en
Publication of CN102339808A publication Critical patent/CN102339808A/en
Application granted granted Critical
Publication of CN102339808B publication Critical patent/CN102339808B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a packaging lead frame structure, which enables a packaged chip not to be easily broken in a high-temperature environment due to the difference of thermal expansion coefficients of materials and a frame at the bottom, ensures the effectiveness of a product and improves the one-time processing yield. The lead wire structure comprises a frame bottom plate, a base island, a chip, a lead wire and an outer pin, wherein the base island is arranged on the frame bottom plate, the chip is positioned in the region of the base island, and the lead wire is connected with the chip and the outer pin, and is characterized in that: the heat conduction glue layer is coated on the base island, the bottom of the molybdenum sheet is bonded with the heat conduction glue layer, the upper surface of the molybdenum sheet is coated with the conductive glue layer, the bottom of the chip is bonded with the conductive glue layer, and the outer edge of the chip is located inside the outer edge of the molybdenum sheet.

Description

The package leadframe shelf structure
Technical field
The present invention relates to the technical field of semiconductor packages, be specially the package leadframe shelf structure.
Background technology
Existing TO-3P encapsulating structure is by conducting resinl/or insulating cement bonding chip at the TO-3P framework, chip is sealed epoxy resin outward again, because the packaged chip size of this technology is bigger, the encapsulation back is owing to thermal expansion coefficient difference between chip and two kinds of materials of framework is bigger, easily cause back heating seal and use in because temperature is too high, make chip rupture, make product failure, and present heating is sealed and is easily caused chip rupture, encapsulating structure time processing yield has only about 80%, and the processing yield is low.
Summary of the invention
At the problems referred to above, the invention provides the package leadframe shelf structure, it makes that the chip of encapsulation is difficult for causing breaking because of the material coefficient of thermal expansion difference of coefficients with the framework of bottom in hot environment, guarantee that product is effective, and improved the time processing yield.
The package leadframe shelf structure, its technical scheme is such: it comprises chassis base, Ji Dao, chip, lead-in wire, outer pin, described chassis base is provided with Ji Dao, described chip is positioned at the zone of described Ji Dao, described lead-in wire connects described chip, outer pin, it is characterized in that: be coated with the heat conduction glue-line on the described Ji Dao, the bonding described heat conduction glue-line in molybdenum sheet bottom, the upper surface of described molybdenum sheet is coated with conductive adhesive layer, the bonding described conductive adhesive layer in the bottom of described chip, the outward flange of described chip all is positioned at the outward flange inside of described molybdenum sheet.
It is further characterized in that: the replaceable one-tenth insulation of described conductive adhesive layer glue-line;
The thickness of described molybdenum sheet is 2mm.
After adopting structure of the present invention, owing to be provided with molybdenum sheet between Ji Dao and the chip, the thermal coefficient of expansion of molybdenum sheet is between basic island material, chip, and in hot environment, thermal expansion has obtained certain neutralization, make that distortion and the molybdenum sheet of chip are roughly the same, and the distortion of molybdenum sheet and Ji Dao is roughly the same, and then chip do not break in the hot environment again, guarantees that product is effective, and improve and process successively more than the yield to 95%, processing yield height.
Description of drawings
Fig. 1 is TO-3P encapsulating lead structural representation of the present invention;
Fig. 2 is the left view structural representation (adding epoxy resin layer) of Fig. 1.
Embodiment
See Fig. 1, Fig. 2, it comprises chassis base 1, basic island 2, chip 3, lead-in wire 4, outer pin 5, chassis base 1 is provided with basic island 2, chip 3 is positioned on the zone on basic island 2, and lead-in wire 4 connects chip 3, outer pin 5, is coated with heat conduction glue-line 6 on the basic island 2, the bonding heat conduction glue-line 6 in the bottom of the molybdenum sheet 7 that 2mm is thick, the upper surface of molybdenum sheet 7 is coated with conductive adhesive layer 8, the bonding conductive adhesive layer 8 in the bottom of chip 3, and the outward flange of chip 3 all is positioned at the outward flange inside of molybdenum sheet 7.The replaceable one-tenth insulation of conductive adhesive layer 8 glue-lines wherein.9 is epoxy resin layer among the figure.

Claims (3)

1. package leadframe shelf structure, it comprises chassis base, Ji Dao, chip, lead-in wire, outer pin, described chassis base is provided with Ji Dao, described chip is positioned at the zone of described Ji Dao, described lead-in wire connects described chip, outer pin, it is characterized in that: be coated with the heat conduction glue-line on the described Ji Dao, the bonding described heat conduction glue-line in molybdenum sheet bottom, the upper surface of described molybdenum sheet is coated with conductive adhesive layer, the bonding described conductive adhesive layer in the bottom of described chip, the outward flange of described chip all is positioned at the outward flange inside of described molybdenum sheet.
2. package leadframe shelf structure according to claim 1, it is characterized in that: described conductive adhesive layer replaces to the insulation glue-line.
3. package leadframe shelf structure according to claim 1 and 2, it is characterized in that: the thickness of described molybdenum sheet is 2mm.
CN 201110332730 2011-10-28 2011-10-28 Packaging lead frame structure Active CN102339808B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110332730 CN102339808B (en) 2011-10-28 2011-10-28 Packaging lead frame structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110332730 CN102339808B (en) 2011-10-28 2011-10-28 Packaging lead frame structure

Publications (2)

Publication Number Publication Date
CN102339808A CN102339808A (en) 2012-02-01
CN102339808B true CN102339808B (en) 2013-07-17

Family

ID=45515447

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110332730 Active CN102339808B (en) 2011-10-28 2011-10-28 Packaging lead frame structure

Country Status (1)

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CN (1) CN102339808B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9158883B2 (en) * 2012-08-08 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. System for designing a semiconductor device, device made, and method of using the system
CN102956598A (en) * 2012-11-20 2013-03-06 无锡市威海达机械制造有限公司 Welding frame structure for side pins
CN102956596A (en) * 2012-11-20 2013-03-06 无锡市威海达机械制造有限公司 Lead frame structure
CN110911376A (en) * 2018-09-14 2020-03-24 珠海格力电器股份有限公司 Semiconductor chip packaging piece and manufacturing method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3077668B2 (en) * 1998-05-01 2000-08-14 日本電気株式会社 Semiconductor device, lead frame for semiconductor device, and method of manufacturing the same
CN100448005C (en) * 2005-06-21 2008-12-31 天水华天科技股份有限公司 Photoelectric integrative infrared receiver and packaging method
CN201163624Y (en) * 2008-02-02 2008-12-10 上海旭福电子有限公司 Labeling type insulation packaging structure
CN201435388Y (en) * 2009-07-06 2010-03-31 晶诚（郑州）科技有限公司 Lead frame used for encapsulating MOSFET
CN102034782A (en) * 2009-09-30 2011-04-27 万国半导体有限公司 Mixed alloy lead frame used for power semiconductors
CN102163928A (en) * 2011-01-13 2011-08-24 常州西整电子科技有限公司 Special ultrahigh-power rectification power electronic device module for ultrasonic welding machine
CN202259273U (en) * 2011-10-28 2012-05-30 无锡红光微电子有限公司 Packaging lead frame structure

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