CN102339808A - Packaging lead frame structure - Google Patents
Packaging lead frame structure Download PDFInfo
- Publication number
- CN102339808A CN102339808A CN2011103327308A CN201110332730A CN102339808A CN 102339808 A CN102339808 A CN 102339808A CN 2011103327308 A CN2011103327308 A CN 2011103327308A CN 201110332730 A CN201110332730 A CN 201110332730A CN 102339808 A CN102339808 A CN 102339808A
- Authority
- CN
- China
- Prior art keywords
- chip
- molybdenum sheet
- lead
- heat conducting
- glue layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 4
- 239000003292 glue Substances 0.000 abstract 4
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000004568 cement Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a packaging lead frame structure. By using the structure, a packaged chip is difficult to depart from a frame at the bottom in a high temperature environment due to the difference of coefficients of thermal expansion of materials, thus guaranteeing valid products and improving primary processing yield. The structure comprises a frame baseplate, a base island, a chip, a lead and an outer pin, wherein the frame baseplate is provided with the base island, the chip is arranged in a base island region, and the lead is connected with the chip and the outer pin. The structure is characterized in that a heat conducting glue layer is coated on the base island, the heat conducting glue layer is adhered to the bottom of a molybdenum sheet, a heat conducting glue layer is coated on the upper surface of the molybdenum sheet, the heat conducting glue layer is adhered to the bottom of the chip, and external edges of the chip are all arranged in external edges of the molybdenum sheet.
Description
Technical field
The present invention relates to the technical field of semiconductor packages, be specially the package leadframe shelf structure.
Background technology
Existing TO-3P encapsulating structure is through conducting resinl/or insulating cement bonding chip at the TO-3P framework; Chip is sealed epoxy resin outward again, because the packaged chip size of this technology is bigger, the encapsulation back is owing to thermal expansion coefficient difference between chip and two kinds of materials of framework is bigger; Be prone to cause back heating seal and use in because temperature is too high; Make to make product failure by chip rupture, and present heating is sealed and is prone to cause chip rupture; Encapsulating structure time processing yield has only about 80%, and the processing yield is low.
Summary of the invention
To the problems referred to above, the invention provides the package leadframe shelf structure, it makes that the chip of encapsulation is difficult for causing in hot environment, breaking because of the material coefficient of thermal expansion difference of coefficients with the framework of bottom, guarantees that product is effective, and has improved the time processing yield.
The package leadframe shelf structure; Its technical scheme is such: it comprises chassis base, Ji Dao, chip, lead-in wire, outer pin, and said chassis base is provided with Ji Dao, and said chip is positioned at the zone of said Ji Dao; Said lead-in wire connects said chip, outer pin; It is characterized in that: be coated with the heat conduction glue-line on the said Ji Dao, the bonding said heat conduction glue-line in molybdenum sheet bottom, the upper surface of said molybdenum sheet is coated with conductive adhesive layer; The bonding said conductive adhesive layer in the bottom of said chip, the outward flange of said chip all are positioned at the outward flange inside of said molybdenum sheet.
It is further characterized in that: the replaceable one-tenth insulation of said conductive adhesive layer glue-line;
The thickness of said molybdenum sheet is 2mm.
After adopting structure of the present invention, owing to be provided with molybdenum sheet between Ji Dao and the chip, the thermal coefficient of expansion of molybdenum sheet is between basic island material, chip; In hot environment, thermal expansion has obtained certain neutralization, makes that the distortion of chip and molybdenum sheet are roughly the same; And the distortion of molybdenum sheet and Ji Dao is roughly the same, and then chip do not break in the hot environment again, guarantees that product is effective; And improve and process successively more than the yield to 95%, the processing yield is high.
Description of drawings
Fig. 1 is a TO-3P encapsulating lead structural representation of the present invention;
Fig. 2 is the left view structural representation (adding epoxy resin layer) of Fig. 1.
Embodiment
See Fig. 1, Fig. 2, it comprises chassis base 1, basic island 2, chip 3, lead-in wire 4, outer pin 5, and chassis base 1 is provided with basic island 2; Chip 3 is positioned on the zone on basic island 2, and lead-in wire 4 connects chip 3, outer pin 5, is coated with heat conduction glue-line 6 on the basic island 2; The bonding heat conduction glue-line 6 in the bottom of the molybdenum sheet 7 that 2mm is thick; The upper surface of molybdenum sheet 7 is coated with conductive adhesive layer 8, and the bonding conductive adhesive layer 8 in the bottom of chip 3, the outward flange of chip 3 all are positioned at the outward flange inside of molybdenum sheet 7.The replaceable one-tenth insulation of conductive adhesive layer 8 glue-lines wherein.9 is epoxy resin layer among the figure.
Claims (3)
1. package leadframe shelf structure; It comprises chassis base, Ji Dao, chip, lead-in wire, outer pin, and said chassis base is provided with Ji Dao, and said chip is positioned at the zone of said Ji Dao; Said lead-in wire connects said chip, outer pin; It is characterized in that: be coated with the heat conduction glue-line on the said Ji Dao, the bonding said heat conduction glue-line in molybdenum sheet bottom, the upper surface of said molybdenum sheet is coated with conductive adhesive layer; The bonding said conductive adhesive layer in the bottom of said chip, the outward flange of said chip all are positioned at the outward flange inside of said molybdenum sheet.
2. package leadframe shelf structure according to claim 1 is characterized in that: the replaceable one-tenth insulation of said conductive adhesive layer glue-line.
3. package leadframe shelf structure according to claim 1 and 2 is characterized in that: the thickness of said molybdenum sheet is 2mm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 201110332730 CN102339808B (en) | 2011-10-28 | 2011-10-28 | Packaging lead frame structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 201110332730 CN102339808B (en) | 2011-10-28 | 2011-10-28 | Packaging lead frame structure |
Publications (2)
Publication Number | Publication Date |
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CN102339808A true CN102339808A (en) | 2012-02-01 |
CN102339808B CN102339808B (en) | 2013-07-17 |
Family
ID=45515447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 201110332730 Active CN102339808B (en) | 2011-10-28 | 2011-10-28 | Packaging lead frame structure |
Country Status (1)
Country | Link |
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CN (1) | CN102339808B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102956596A (en) * | 2012-11-20 | 2013-03-06 | 无锡市威海达机械制造有限公司 | Lead frame structure |
CN102956598A (en) * | 2012-11-20 | 2013-03-06 | 无锡市威海达机械制造有限公司 | Welding frame structure for side pins |
CN106055724A (en) * | 2012-08-08 | 2016-10-26 | 台湾积体电路制造股份有限公司 | System for designing a semiconductor device, device made, and method of using the system |
CN110911376A (en) * | 2018-09-14 | 2020-03-24 | 珠海格力电器股份有限公司 | Semiconductor chip packaging piece and manufacturing method thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11317488A (en) * | 1998-05-01 | 1999-11-16 | Nec Corp | Semiconductor device, lead frame for the semiconductor device, and manufacture thereof |
CN1885537A (en) * | 2005-06-21 | 2006-12-27 | 天水华天科技股份有限公司 | Photoelectric integrative infrared receiver and packaging method |
CN201163624Y (en) * | 2008-02-02 | 2008-12-10 | 上海旭福电子有限公司 | Labeling type insulation packaging structure |
CN201435388Y (en) * | 2009-07-06 | 2010-03-31 | 晶诚(郑州)科技有限公司 | Lead frame used for encapsulating MOSFET |
CN102034782A (en) * | 2009-09-30 | 2011-04-27 | 万国半导体有限公司 | Mixed alloy lead frame used for power semiconductors |
CN102163928A (en) * | 2011-01-13 | 2011-08-24 | 常州西整电子科技有限公司 | Special ultrahigh-power rectification power electronic device module for ultrasonic welding machine |
CN202259273U (en) * | 2011-10-28 | 2012-05-30 | 无锡红光微电子有限公司 | Packaging lead frame structure |
-
2011
- 2011-10-28 CN CN 201110332730 patent/CN102339808B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11317488A (en) * | 1998-05-01 | 1999-11-16 | Nec Corp | Semiconductor device, lead frame for the semiconductor device, and manufacture thereof |
CN1885537A (en) * | 2005-06-21 | 2006-12-27 | 天水华天科技股份有限公司 | Photoelectric integrative infrared receiver and packaging method |
CN201163624Y (en) * | 2008-02-02 | 2008-12-10 | 上海旭福电子有限公司 | Labeling type insulation packaging structure |
CN201435388Y (en) * | 2009-07-06 | 2010-03-31 | 晶诚(郑州)科技有限公司 | Lead frame used for encapsulating MOSFET |
CN102034782A (en) * | 2009-09-30 | 2011-04-27 | 万国半导体有限公司 | Mixed alloy lead frame used for power semiconductors |
CN102163928A (en) * | 2011-01-13 | 2011-08-24 | 常州西整电子科技有限公司 | Special ultrahigh-power rectification power electronic device module for ultrasonic welding machine |
CN202259273U (en) * | 2011-10-28 | 2012-05-30 | 无锡红光微电子有限公司 | Packaging lead frame structure |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106055724A (en) * | 2012-08-08 | 2016-10-26 | 台湾积体电路制造股份有限公司 | System for designing a semiconductor device, device made, and method of using the system |
CN102956596A (en) * | 2012-11-20 | 2013-03-06 | 无锡市威海达机械制造有限公司 | Lead frame structure |
CN102956598A (en) * | 2012-11-20 | 2013-03-06 | 无锡市威海达机械制造有限公司 | Welding frame structure for side pins |
CN110911376A (en) * | 2018-09-14 | 2020-03-24 | 珠海格力电器股份有限公司 | Semiconductor chip packaging piece and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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CN102339808B (en) | 2013-07-17 |
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