CN102244523B - Zero intermediate frequency receiver and method for eliminating DC offset of same - Google Patents

Abstract

The invention discloses a zero-IF receiver and its DC offset elimination method. The receiver includes a low-noise amplifier, a mixer, a first variable gain amplifier, an analog-to-digital converter, and a DC offset elimination device. The invented DC offset elimination device adopts the combination of analog feedback circuit to simulate DC and digital terminal to remove DC, which not only avoids the complexity of simply using analog circuit to remove DC, but also meets the minimum sensitivity requirements of wideband receivers, and overcomes the The problem that the dynamic range of the input analog signal of the analog-to-digital converter should not be too large when simply using digital to remove the direct current is proved, and the present invention can eliminate the direct current offset in the baseband signal relatively cleanly.

Description

Zero-IF Receiver and Its Elimination Method of DC Offset

technical field

The invention relates to a receiver and a method for eliminating a DC offset thereof, in particular to a zero-IF receiver and a method for eliminating a DC offset thereof, and belongs to the technical field of communication.

Background technique

In recent years, the rapid development of wireless communication technologies such as wireless LAN, 3G technology, and Bluetooth has promoted further research on integrated wireless receivers in the GHz frequency range. The standard RF transceiver (Transceiver) front-end architecture based on these wireless communications is mainly divided into superheterodyne and zero-IF.

The traditional superheterodyne structure has a long history of converting the signal frequency band (RF) to a relatively low intermediate frequency (IF). The intermediate frequency IF is filtered, amplified, converted to baseband, and finally quantized and demodulated. IF signal processing requires IF filtering functions, and the devices that realize these functions are off-chip passive devices with high power, and this structure will generate image signals. In a receiver with a superheterodyne structure, removing the image signal is also a Big difficulty.

Because of this, since the zero-IF receiver does not need to pass through the intermediate frequency during the down-conversion process, and the image frequency is the RF signal itself, there is no image frequency interference, and the zero-IF receiver has gradually become the most widely used receiver structure. Fig. 1 is the structural block diagram of a kind of zero intermediate frequency receiver of prior art, and its working principle is as follows: after the radio frequency signal that receives is amplified by filter and low-noise amplifier, mixes with mutually orthogonal two-way local oscillator signals, The in-phase and quadrature baseband signals are generated respectively. Since the frequency of the local oscillator signal is the same as that of the radio frequency signal, the baseband signal is directly generated after mixing, and the signal selection and gain adjustment are performed on the baseband, which is controlled by a low-pass filter and a variable The gain amplifier is complete. Compared with the superheterodyne structure receiver, it has the following advantages: 1) The circuit is simpler and the overall cost is the lowest; 2) The analog-to-digital converter (ADC) works at a lower input frequency to obtain the best system performance; 3) No RF image rejection filter is required.

However, everything has two sides, and zero-IF receivers also have their disadvantages: 1) The baseband DC offset introduced during down-conversion reduces the overall dynamic range of the system; 2) Low radiation has more stringent requirements on LO leakage indicators. Then, from the shortcomings of the zero-IF receiver, it can be known that when using this structure, it is necessary to eliminate the baseband DC offset as much as possible and estimate the LO leakage at the transmitting end. At present, the technologies for eliminating the DC offset of the baseband mainly include pure analog circuit to remove DC and pure digital to remove DC. However, it is difficult to completely eliminate the DC offset of the baseband signal if a pure analog circuit is used to remove DC, especially for For a zero-IF receiver that requires low receiving sensitivity and a relatively large DC offset value, it is difficult to meet the requirements of DC removal by using a simple analog circuit. Even if a circuit that meets the requirements can be built, this circuit is very complicated and not suitable for Chip-level implementation; if you use pure digital to remove DC, although the DC can be removed relatively cleanly, the dynamics of the ADC input signal cannot meet the requirements. If the signal is greater than a certain value and the existing DC offset value is extremely high It is easy to exceed the input signal range specified by the ADC. Therefore, neither of the above two DC removal methods can satisfy a zero-IF receiver with a large signal dynamic range and low minimum receiving sensitivity requirements.

To sum up, it can be seen that the zero-IF receiver of the prior art has the problem that the direct current introduced in the down-conversion process is difficult to remove. Therefore, it is necessary to propose an improved technical means to solve this problem.

Contents of the invention

In order to overcome the problem that the direct current introduced in the down-conversion process of the above-mentioned prior art zero-IF receiver is difficult to remove, the main purpose of the present invention is to provide a zero-IF receiver and its DC offset elimination method, which satisfies zero In the case of sufficiently large signal dynamic range and sufficiently low minimum receiving sensitivity of the IF receiver, the DC offset of the baseband signal can be eliminated relatively cleanly, and the bit error rate of the received signal is guaranteed to be BER<1e ^-6 .

For reaching above-mentioned and other objects, the zero-IF receiver provided by the present invention comprises: low-noise amplifier, mixer, the first variable gain amplifier and analog-to-digital converter, in addition, this zero-IF receiver also comprises always The current offset elimination device, the DC offset elimination device further includes:

The state control unit is used to control the state of the receiver. After the initialization of the receiver is completed, the state control unit controls the input of the low-noise amplifier to be grounded, and makes the analog feedback loop in a non-working state;

A DC estimation unit, connected to the digital terminal of the analog-to-digital converter, for performing DC estimation on the digital terminal to obtain a DC estimated value;

An analog feedback loop, connected to the DC estimation unit to obtain a DC value to be eliminated, at least including a digital-to-analog converter, after the DC estimation unit obtains the DC estimation value, the state control unit controls the digital-to-analog converter In the working state, the DC value to be eliminated is converted into an analog DC signal;

a subtractor, one end of which receives the analog area tributary signal of the analog feedback loop, one end connected to the first variable gain amplifier, and the output end outputs a residual direct current to the analog-to-digital converter; and

The residual direct current removal unit is arranged at the digital end of the analog-to-digital converter, and is used for calculating the residual direct current value and eliminating the residual direct current value.

Further, the zero-IF receiver further includes a second variable gain amplifier, and the second variable gain amplifier is arranged between the subtractor and the analog-to-digital converter.

Further, the analog feedback loop also includes a precision reduction unit, which is used to reduce the precision of the DC value to be eliminated before sending it to the digital-to-analog converter for conversion into the analog DC-removed signal.

Further, the DC value to be eliminated is the DC estimated value minus the gain value of the second variable gain amplifier.

Further, the accuracy reduction unit reduces the accuracy of the DC value to be eliminated from 12 bits to 4 bits.

In order to achieve the above and other objects, the present invention also provides a method for eliminating the DC offset of the zero-IF receiver, which at least includes the following steps:

After the initialization of the receiver is completed, the input of the low-noise amplifier at the radio frequency end of the receiver is short-circuited to ground, and the digital-to-analog converter of the analog feedback loop is in a non-working state;

The DC estimation unit performs DC estimation on the digital terminal of the receiver analog-to-digital converter according to the configuration value of the register to obtain a DC estimation value;

Make the digital-to-analog converter in the working state, the analog feedback loop obtains a DC value to be eliminated from the DC estimation unit, and generates an analog DC-removed signal through the digital-to-analog converter;

The analog de-DC signal and the DC offset formed during the down-conversion process of the receiver form a residual DC value after de-DC by a subtractor; and

The residual direct current removal unit calculates the residual direct current value at the digital end of the analog-to-digital converter and eliminates it.

Further, if there is a second variable gain amplifier between the subtractor of the receiver and the analog-to-digital converter, the DC value to be eliminated is the estimated value of DC minus the gain value of the second variable gain amplifier.

Further, the step of the analog feedback loop obtaining a DC value to be eliminated from the DC estimation unit and generating an analog DC removal signal through the digital-to-analog converter includes:

reduce the accuracy of the DC value to be eliminated; and

The DC value to be eliminated with reduced precision is sent to the digital-to-analog converter to generate the analog DC-removed signal.

Further, the precision of the DC value to be eliminated is reduced from 12 bits to 4 bits.

Compared with the prior art, the zero-IF receiver and its DC offset elimination method provided by the present invention combine the analog DC removal with the digital terminal through the analog feedback circuit, which avoids the trouble of simply using the analog circuit to remove DC. Complexity, and can meet the minimum sensitivity requirements of wideband receivers, and overcome the problem that the dynamic range of the input analog signal of the analog-to-digital converter should not be too large when simply using digital to remove DC, and the required feedback DAC accuracy is also relatively low. Experimental simulation It is proved that using the zero-IF receiver and the DC offset elimination method provided by the present invention, the DC offset in the baseband signal can be eliminated relatively cleanly, and the bit error rate BER<1e ^-6 of the final received signal can be guaranteed.

Description of drawings

Fig. 1 is the structural block diagram of prior art zero-IF receiver;

Fig. 2 is the structural block diagram of the preferred embodiment of zero-IF receiver of the present invention;

Fig. 3 is a flow chart of the steps of the DC offset elimination method of the zero-IF receiver of the present invention;

FIG. 4 and FIG. 5 are simulation diagrams of the DC offset elimination effect of the zero-IF receiver of the present invention.

Detailed ways

The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Fig. 2 is a structural block diagram of a preferred embodiment of the zero-IF receiver of the present invention. The zero-IF receiver in this specific embodiment includes a low-noise amplifier 201, a mixer 202, a first variable gain amplifier 203 (VGA1), an analog-to-digital converter 204 (ADC), and a DC offset canceling device 205, wherein the DC offset The shift and cancel device 205 further includes a state control unit 206 , a DC estimation unit 207 , an analog feedback loop 208 , a subtractor 209 and a residual DC removal unit 210 .

The state control unit 206 is used to control the state of the receiver. After the initialization of the zero-IF receiver of the present invention and the calibration of the PLL (phase-locked loop) are completed, the state control unit 206 controls the input of the low-noise amplifier 201 to be short-circuited, and the analog The feedback loop 208 is in a disabled state.

The DC estimation unit 207 is connected to the digital terminal of the analog-to-digital converter 204, and is used for performing DC estimation on the digital terminal, that is, when the input of the low noise amplifier 201 is grounded, the DC estimation unit 207 performs DC estimation according to the configuration value of the relevant register, The obtained DC estimated value (assumed to be Idc) can be stored in the register, because Idc is the estimated value of the receiver DC before the analog feedback loop 208 is opened, it truly reflects the DC after the first variable gain amplifier 203 Offset.

The analog feedback loop 208 is connected to the DC estimation unit 207 to obtain a DC value to be eliminated from the DC estimation unit 207. Generally speaking, the DC value to be eliminated is a DC estimated value or a part thereof. The analog feedback loop 208 includes at least a digital-to-analog Converter 213 (DAC), when the DC estimation unit 207 performs DC estimation to obtain the DC estimated value, the state control unit 206 makes the analog feedback loop 208 in the working (Enable) state, even if the digital-to-analog converter is in the Enable state, the digital-to-analog The converter 213 performs digital-to-analog conversion on the DC value to be eliminated to generate an analog DC-removed signal and sends it to the subtractor 209 .

One end of the subtractor 209 receives the analog de-DC signal generated by the analog feedback loop 208, one end is connected to the first variable gain amplifier 203, and its output end is connected to the analog-to-digital converter 204, the purpose is to utilize the analog signal generated by the analog feedback loop 208 The de-DC signal removes the DC offset generated by the down-conversion process of the receiver.

The residual direct current removal unit 210 is arranged at the digital end of the analog-to-digital converter 204. Due to various reasons, it is difficult to completely eliminate the direct current offset through the analog feedback loop 208 through the analog end. Therefore, after the subtractor 209 , a residual direct current value ΔIdc may be generated, and the residual direct current removal unit 210 is used to calculate the residual direct current value at the digital end according to a certain algorithm and continue to eliminate it in a feedforward manner.

Generally speaking, for the zero-IF receiver provided in this specific embodiment, there is also a second variable gain amplifier 211 (VGA2) between the subtractor 209 and the analog-to-digital converter 204, which is used to amplify the DC signal to facilitate Accurate quantization, so the DC value to be eliminated obtained in the analog feedback loop 208 is the DC estimated value of the DC estimation unit 207 and the gain value of the second variable gain amplifier 211 is removed, and then it is sent to the digital-to-analog converter 213 for The analog side goes to DC.

Preferably, in a preferred embodiment of this embodiment, an accuracy reduction unit 212 can also be designed between the DC estimation unit 207 and the digital-to-analog converter 213 to reduce the accuracy, since the analog feedback loop 208 uses a digital-to-analog conversion The device performs digital-to-analog conversion on the DC estimated value of the digital signal. In order to reduce the complexity of the design and reduce the chip area, on the premise of not affecting the overall performance of the chip (the bit error rate is less than the specified value), a sufficiently low-precision digital-to-analog Converter 213 therefore requires de-accuracy for the digital signal before it is fed to the DAC. In the preferred embodiment of this embodiment, since the DC value to be eliminated of the digital signal estimated by the DC estimation unit 207 is 12 bits, it is found through the previous system simulation that the 4-bit digital-to-analog converter is the minimum precision that can meet the system performance requirements Digital-to-analog converter, therefore, in a preferred embodiment of this embodiment, the accuracy reduction unit 212 needs to convert the DC value of the digital signal to be eliminated from 12bit precision to 4bit precision, mainly to convert the DC value of the digital signal to be eliminated The 4-bit signal is intercepted and then sent to the digital-to-analog converter 213 for conversion to generate an analog DC-removed signal. Of course, the requirement for accuracy can be determined according to specific circumstances, and this embodiment is not limited thereto. For the specific interception of the digital signal by the precision reduction unit 212, take the precision of intercepting 4 bits from the digital signal of 12bit precision as an example, four bits can be intercepted arbitrarily, and the best interception method can also be obtained through system simulation, which is preferably implemented in this embodiment In the example, assuming that the DC estimated value of the digital signal is Idc=D ₁₁ D ₁₀ D ₉ D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ D ₀ , it can be obtained after system simulation and adopts the best interception method The intercepted digital signal Idc'=D ₁₀ D ₉ D ₈ D ₇ .

FIG. 3 is a flow chart of the steps of the DC offset elimination method of the zero-IF receiver of the present invention. As shown in Figure 3, the DC offset elimination method of the zero-IF receiver provided in this specific embodiment includes the following steps:

Step 301, after the initialization of the receiver and the calibration of the phase-locked loop (PLL) are completed, the input of the low-noise amplifier 201 at the radio frequency end is short-circuited to ground, and the digital-to-analog converter 213 of the analog feedback loop 208 is set to Disable state;

Step 302, the DC estimating unit 207 starts to work, it performs DC estimation according to the configuration value in the relevant register, obtains the DC estimated value Idc, and sends a DC value to be eliminated to the analog feedback loop 208 for removing DC at the analog end , the DC estimated value Idc can be stored in the corresponding register, and the DC value to be eliminated is the DC estimated value or a part thereof;

Step 303, make the digital-to-analog converter 213 in the Enable state, the analog feedback loop 208 is opened, and the DC removal operation is started, and the DC value to be eliminated is sent to the digital-to-analog converter 213, and an analog DC removal is obtained after the digital-to-analog converter 213 The signal is sent to the subtractor 209;

Step 304, the DC offset formed during the down-conversion process of the simulated DC signal and the receiver is removed by the subtractor 209 to form a residual DC value;

In step 305, the residual direct current removal unit 210 calculates the residual direct current value after removing direct current at the analog end according to a certain algorithm on the digital end, and uses it for removing direct current at the digital end.

If there is a second variable gain amplifier 211 in this specific embodiment, then in step 302, the DC value to be eliminated sent to the analog feedback loop 208 is the DC estimated value Idc minus the gain value of the second variable gain amplifier 211 .

Preferably, before step 303, a step of reducing the precision of the DC value to be eliminated may also be included. Since the analog feedback loop 208 uses the digital-to-analog converter 213 to perform digital-to-analog conversion on the DC value to be eliminated (Idc or Idc minus the gain value of the second variable gain amplifier 211) of the digital signal to perform DC removal at the analog end, in order to reduce The complexity of the design reduces the chip area, and under the premise of not affecting the overall performance of the chip (the bit error rate is less than the specified value), a sufficiently low-precision digital-to-analog converter can be used. In a preferred embodiment of this embodiment, The accuracy of the digital signal needs to be reduced. Since in the preferred embodiment of this embodiment, the estimated DC value of the digital signal is 12 bits, the DC value to be eliminated is 12 bits. After the previous system simulation, it was found that the 4-bit digital-to-analog converter is the lowest precision digital signal that can meet the system performance requirements. Therefore, it is necessary to intercept the DC value of the digital signal to be eliminated to obtain a 4-bit digital signal and then send it to the digital-to-analog converter for conversion. Taking the preferred embodiment of this embodiment as an example, let Idc=D ₁₁ D ₁₀ D ₉ D ₈ D ₇ D ₆ D ₅ D ₄ D ₃ D ₂ D ₁ D ₀ , which is actually used to simulate the signal without direct current (after interception signal) is Idc'=D ₁₀ D ₉ D ₈ D ₇ , then the residual DC amount calculated by the residual DC removal unit 210 obtained by the digital terminal through feedforward removal is

ΔIdc'=VGA2*ΔIdc=VGA2*(Idc-{D ₁₀ ,Idc',0000000}), the content in curly brackets in this formula is to add 0 to the lower bits of Idc' and expand it to 12bit to align with Idc. Subtract.

FIG. 4 and FIG. 5 are simulation diagrams of the DC removal effect of the zero-IF receiver of the present invention. Both Figure 4 and Figure 5 are carried out under the condition that the received signal power is the minimum receiving sensitivity -100dBm. Figure 4 shows the baseband signal waveform after the Mixer (mixer) introduces DC. It can be seen that the introduced DC is 9mV. Figure 5 is the waveform after the digital signal is converted into an analog voltage after removing DC. It can be seen that after the processing of removing DC at the analog end and removing DC at the digital end, the effective baseband signal is amplified and the DC is almost completely eliminated, thus illustrating this scheme. effectiveness and feasibility.

To sum up, the zero-IF receiver and its DC offset elimination method provided by this specific embodiment combine the analog DC removal with the digital terminal through the analog feedback circuit, which avoids the trouble of simply using the analog circuit to remove DC. Complexity, and can meet the minimum sensitivity requirements of wideband receivers, and overcome the problem that the dynamic range of the input analog signal of the analog-to-digital converter should not be too large when simply using digital to remove DC, and the required feedback DAC accuracy is also relatively low. Experimental simulation It is proved that using the zero-IF receiver and its DC offset elimination method provided in this specific embodiment, the DC offset in the baseband signal can be eliminated relatively cleanly, and the bit error rate BER of the final received signal can be guaranteed <1e ^-6 .

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Any person skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (7)

1. A zero-IF receiver, comprising a low-noise amplifier, a mixer, a first variable gain amplifier and an analog-to-digital converter, characterized in that, the zero-IF receiver also includes a DC offset canceling device, the DC The offset canceling device further includes: The state control unit is used to control the state of the receiver. After the initialization of the receiver is completed, the state control unit controls the input of the low-noise amplifier to be grounded, and makes the analog feedback loop in a non-working state; The DC estimation unit is connected to the digital terminal of the analog-to-digital converter, and performs DC estimation on the digital terminal according to the configuration value of the register to obtain a DC estimated value; An analog feedback loop, connected to the DC estimation unit to obtain a DC value to be eliminated, which at least includes a precision reduction unit and a digital-to-analog converter. After the DC estimation unit obtains the DC estimation value, the state control unit controls the digital The analog-to-analog converter is in the working state, and the accuracy reduction unit reduces the accuracy of the DC value to be eliminated and then sends it to the digital-to-analog converter to convert it into an analog DC-removed signal; A subtractor, one end of which receives the analog DC signal from the analog feedback loop, one end connected to the first variable gain amplifier, and the output end outputs residual DC to the analog-to-digital converter; and The residual direct current removal unit is arranged at the digital end of the analog-to-digital converter, and is used for calculating the residual direct current value and eliminating the residual direct current value. 2. The zero-IF receiver as claimed in claim 1, characterized in that: the zero-IF receiver further comprises a second variable gain amplifier, and the second variable gain amplifier is arranged between the subtractor and the analog-to-digital converter between. 3. The zero-IF receiver as claimed in claim 2, wherein the DC value to be eliminated is the DC estimated value minus the gain value of the second variable gain amplifier. 4. The zero-IF receiver according to claim 3, characterized in that: the accuracy reducing unit reduces the accuracy of the DC value to be eliminated from 12 bits to 4 bits. 5. A method for eliminating the DC offset of a zero-IF receiver, at least comprising the steps of: After the initialization of the receiver is completed, the input of the low-noise amplifier at the radio frequency end of the receiver is short-circuited to ground, and the digital-to-analog converter of the analog feedback loop is in a non-working state; The DC estimation unit performs DC estimation on the digital terminal of the receiver analog-to-digital converter according to the configuration value of the register to obtain a DC estimation value; Make the digital-to-analog converter in the working state, and the analog feedback loop obtains a DC value to be eliminated from the DC estimation unit; Using a precision reduction unit to reduce the precision of the DC value to be eliminated, and sending the DC value to be eliminated after the precision is reduced to the digital-to-analog converter to generate an analog DC-removed signal; The analog de-DC signal and the DC offset formed during the down-conversion process of the receiver form a residual DC value after de-DC by a subtractor; and The residual direct current removal unit calculates the residual direct current value at the digital end of the analog-to-digital converter and eliminates it. 6. the elimination method of the DC offset of a kind of zero intermediate frequency receiver as claimed in claim 5 is characterized in that: if there is the second variable gain amplifier between the subtractor of this receiver and this analog-to-digital converter, The DC value to be eliminated is the estimated DC value minus the gain value of the second variable gain amplifier. 7. The method for eliminating the DC offset of a zero-IF receiver as claimed in claim 6, wherein the precision of the DC value to be eliminated is reduced from 12 bits to 4 bits.