CN111865344B - An analog baseband circuit with variable gain and bandwidth - Google Patents
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Abstract
本发明属于集成电路技术领域，具体为一种可变增益和带宽的模拟基带电路。本发明的模拟基带电路包括带宽可调的低通滤波器、可变增益放大器；低通滤波器为五阶切比雪夫Ⅰ型低通滤波器，由一个一阶RC低通滤波器和两个双二次结构组成，置于前级，用于将由混频器输出的信号进行滤波和放大，并提供20dB的恒定增益，通过调节电容值控制低通滤波器的带宽；可变增益放大器共有两级，每级结构相同，置于后级，用于将由低通滤波器输出的信号进行放大，提供从0到18dB的可变增益；每一可变增益放大器的带宽大于前级低通滤波器可调带宽的最大值，以保证系统能够正常工作。本发明模拟基带电路具有带宽宽、增益调节精确、噪声低、功耗小的特点。
The invention belongs to the technical field of integrated circuits, in particular to an analog baseband circuit with variable gain and bandwidth. The analog baseband circuit of the invention includes a low-pass filter with adjustable bandwidth and a variable gain amplifier; the low-pass filter is a fifth-order Chebyshev type I low-pass filter, which consists of a first-order RC low-pass filter and two It is composed of a double quadratic structure and is placed in the front stage to filter and amplify the signal output by the mixer, and provide a constant gain of 20dB. The bandwidth of the low-pass filter is controlled by adjusting the capacitance value; the variable gain amplifier has two Each stage has the same structure and is placed in the latter stage to amplify the signal output by the low-pass filter, providing a variable gain from 0 to 18dB; the bandwidth of each variable gain amplifier is larger than that of the previous stage low-pass filter. The maximum value of the adjustable bandwidth to ensure that the system can work normally. The analog baseband circuit of the invention has the characteristics of wide bandwidth, accurate gain adjustment, low noise and low power consumption.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a gain and bandwidth variable analog baseband circuit.
Background
With the development of radio communication technology, the demand for high transmission rate receiver systems is more and more urgent. Ultra-wideband receiver systems with bandwidths up to hundreds of megahertz have emerged. The ultra-wideband receiver mainly comprises a radio frequency terminal and an analog baseband circuit, wherein the radio frequency terminal comprises an antenna, a radio frequency filter and a frequency mixer; the analog band-pass circuit mainly comprises a filter and a variable gain amplifier.
In an analog baseband circuit, a filter is mainly used for filtering out-of-band spurious signals and performing channel selection, and in order to better suppress the influence of adjacent channel signals, the transition band of the filter is as steep as possible. The structure of the filter is mainly divided into an open loop structure and a closed loop structure, wherein the bandwidth of the open loop structure is wider but the linearity is poorer; the closed loop structure has better linearity but narrower bandwidth. Given the bandwidth of the low-pass filter, the in-pass ripple and the stopband roll-off rate, the order of the filter and the quality factors of the stages, the break-over frequency and the pole-zero case can be calculated by the mathematical analysis software MATLAB. The variable gain amplifier is used to provide a certain gain to amplify signals, and also, as applied in an ultra-wideband receiver, it puts high demands on the bandwidth. In a specific application, a direct current offset may exist in a signal during a process of being amplified by a previous stage and being transmitted to a subsequent stage. A more common method is to add a dc offset calibration circuit between two stages of amplification circuits, but the cost is more complicated circuit structure and the power consumption is increased. The analog baseband circuit solves the problem by applying an alternating current coupling capacitor and a series voltage dividing resistor.
The effects of noise and linearity should be traded off in configuring the order of the filters and amplifiers of the stages. For better noise performance, it is desirable that the gain of the front stage is large and the gain of the rear stage is small; for better linearity, it is desirable that the gain of the previous stage is small and the gain of the subsequent stage is large. The analog baseband circuit places the filter at the front stage, and the variable gain amplifier at the rear stage, so that the linearity of the circuit is ensured; at the same time, the filter is charged with a constant gain of 20dB in order to improve the noise performance of the circuit.
Disclosure of Invention
It is therefore an object of the present invention to provide an analog baseband circuit with variable bandwidth and gain with wide bandwidth, low noise, and high linearity.
The invention provides a variable gain and bandwidth analog baseband circuit, which comprises a low-pass filter with adjustable bandwidth and a Variable Gain Amplifier (VGA); the low-pass filter is arranged at the front stage and used for filtering and amplifying the signal output by the frequency mixer, providing a constant gain of 20dB and controlling the bandwidth of the low-pass filter by adjusting a capacitance value; the variable gain amplifier is arranged at the rear stage, the variable gain amplifier has two stages, the structure of each stage is the same, and the signal output by the low-pass filter is amplified to provide variable gain from 0 to 18 dB; the bandwidth of each variable gain amplifier should be greater than the maximum value of the adjustable bandwidth of the low-pass filter at the front stage, so as to ensure that the system can work normally.
In the present invention, the low pass filter is a five-order chebyshev type i Low Pass Filter (LPF), comprising: a first order RC low pass filter, a first order BIQUAD structure (BIQUAD), a second order BIQUAD structure (BIQUAD); the first-order RC low-pass filter is used for low-pass filtering, the input end of the first-order RC low-pass filter receives a signal from the mixer, and the output end of the first-order RC low-pass filter is connected with the first-order biquadratic structure; the first-stage biquad structure is used for low-pass filtering and providing 20dB of gain, the input end of the first-stage biquad structure receives the output from the first-stage RC low-pass filter, the output of the first-stage RC low-pass filter is connected with an alternating-current coupling capacitor, and two equal direct-current divider resistors are used for providing a proper common-mode direct-current level for the second-stage biquad structure; the two direct current divider resistors are connected in series, one end of each direct current divider resistor is connected with a power supply, and the other end of each direct current divider resistor is grounded; the alternating current coupling capacitor is connected in series with a direct current divider resistor with one end grounded to form a first-order high-pass filter; the alternating current coupling capacitor is used for coupling an alternating current output signal of the first-stage biquad structure to the input of the second-stage biquad structure and isolating direct current offset of a front stage, the input end of the alternating current coupling capacitor is connected with the output of the first-stage biquad structure, and the output end of the alternating current coupling capacitor is connected with the input of the second-stage biquad structure; and the second-stage biquadratic structure is used for low-pass filtering, the input end of the second-stage biquadratic structure is connected with the output end of the alternating-current coupling capacitor, and the output end of the second-stage biquadratic structure is connected with the first variable gain amplifier. As shown in fig. 2.
Preferably, the biquadratic structure consists of four Gm cells (Gm1, Gm2, Gm3, Gm4) and four capacitors (C11, C12, C21, C22), for convenience, the capacitors C11, C12 are collectively denoted as C1, C21, C22 are collectively denoted as C2; each Gm cell employs a nauta structure. As shown in fig. 3. The differential input signal is connected with the input end of Gm1, the output end of Gm1 is connected with the input end of Gm2 and is simultaneously connected with C11 and C12, the output end of Gm2 is connected with the input end and is simultaneously connected with the input end of Gm3, the output end of Gm3 is connected with the input end of Gm4 and is simultaneously connected with C21 and C22, and the output end of Gm4 is cross-connected with the output end of Gm 1. The output of the whole biquad structure is the output of Gm 3.
Preferably, the nauta structure is composed of 6 inverters (Inv 1-Inv 6), as shown in fig. 4, positive and negative input signals are respectively connected to the input terminals of Inv1 and Inv2, the output terminal of Inv1 is connected to the input terminals of Inv3 and Inv5 and the output terminals of Inv5 and Inv6, and the output terminal of Inv2 is connected to the input terminals of Inv4 and Inv6 and the output terminals of Inv4 and Inv 3.
Preferably, the direct current divider resistors are all high resistors with the resistance of more than 1M ohm, so that the influence of the fluctuation of the resistance value of the resistors caused by process fluctuation on the direct current level is reduced; the AC coupling capacitor cannot be too small, at least in the order of pF, otherwise the high-pass cut-off frequency is too high, and the passband signal is influenced.
Preferably, in the low-pass filter, all capacitors used therein except the ac coupling capacitor are formed by a capacitor array, the capacitor array is controlled by a digital decoder, and the bandwidth of the filter is adjustable by controlling the capacitance to be adjustable.
Preferably, in order to control the quality factor Q of the circuit to be constant on the basis of adjustable bandwidth, the adjustable capacitor arrays C1 (C11, C12) and C2 (C21, C22) must be increased or decreased by the same factor at the same time.
In the invention, the variable gain amplifier is a two-stage amplifier structure, the first stage of fully differential input transistor is an N-tube with a source level negative feedback resistor and a capacitor, the source end of the differential input tube is connected with the negative feedback resistor and the capacitor which are connected in parallel, the drain end of the N-tube is connected with a load resistor, the other end of the load resistor is connected with a power supply, and the drain end of the N-tube is connected with the grid electrode of the differential negative feedback transistor; the differential negative feedback transistor is a P tube, the source ends of the differential negative feedback transistors are respectively connected with two ends of the source level negative feedback capacitor, and the source ends of the differential negative feedback transistors are connected with a power supply; the output of the first stage is at the drain terminal of the fully differential input N tube, and is connected with the source terminal of the second stage differential amplification N tube, the second stage is a simple common source amplifier, the input tube receives the output from the first stage, the drain terminal of the input tube is connected with a load resistor, and the source terminal of the input tube is connected with a current source; the output of the amplifier, i.e. the output of the second stage, is at the drain of the second stage input tube. As shown in fig. 6.
An alternating current coupling capacitor and a direct current divider resistor are connected between the first-stage variable gain amplifier and the second-stage variable gain amplifier, and the connection mode and the function of the alternating current coupling capacitor and the direct current divider resistor are similar to those of the alternating current coupling capacitor and the direct current divider resistor in the low-pass filter, and are shown in fig. 2; the direct current divider resistors are all high resistors with the resistance of more than 1M ohm, so that the influence of the fluctuation of the resistance value of the resistors caused by process fluctuation on a direct current level is reduced; the AC coupling capacitor cannot be too small, at least in the order of pF, otherwise the high-pass cut-off frequency is too high, and the passband signal is influenced.
Preferably, the first-stage input transistor of the variable gain amplifier adopts an N-tube, and the second-stage input tube also adopts an N-tube in consideration of level matching.
In the invention, Alternating Current (AC) coupling capacitors are connected between a first-stage BIQUAD and a second-stage BIQUAD and between two VGAs and used for inhibiting direct current offset caused by overhigh gain of a front stage; series divider resistors are connected between the first and second stages of BIQUAD and between the two VGAs to provide the appropriate dc common mode voltage.
Preferably, since the second biquad structure does not provide gain, an ac coupling capacitor and a dc voltage dividing resistor are not required to be connected between the second biquad structure and the first stage variable gain amplifier to suppress dc offset.
Preferably, the source degeneration resistor used in the first stage of the variable gain amplifier is composed of a resistor array, the resistor array is controlled by a digital decoder, and the gain of the variable gain amplifier is adjustable by controlling the resistor to be adjustable.
The analog baseband circuit provided by the invention has the characteristics of wide bandwidth, accurate gain adjustment, low noise and low power consumption.
Drawings
Figure 1 is a block diagram of an ultra-wideband receiver system and a schematic of the present disclosure.
Fig. 2 is a schematic diagram of the overall structure of the present invention.
Fig. 3 is a schematic structural diagram of each of the bi-quadratic structures shown in fig. 2.
Fig. 4 is a schematic diagram of the structure of each Gm cell shown in fig. 3.
FIG. 5 is a diagram of a capacitor array used in the low pass filter of the present invention.
Fig. 6 is a schematic diagram of the structure of each stage of the variable gain amplifier according to the present invention.
FIG. 7 is the source degeneration resistor R of FIG. 6SSchematic array diagram.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 is a schematic diagram of a prior art ultra-wideband receiver system framework.
As shown in fig. 1, the radio frequency signal emitted from the antenna is subjected to frequency-selective filtering, low-noise amplification and frequency conversion, and then filtered and amplified by an analog baseband circuit, and provided to the ADC for conversion into a digital signal. It can be seen that the analog baseband circuit is a bridge connecting the radio frequency front end and the digital signal processing module, and it is necessary to cooperatively consider and optimally design the module.
Fig. 2 is a structural frame diagram of the present invention.
As shown in fig. 2, the present invention provides an analog baseband circuit for use in an ultra-wideband receiver, which mainly includes a low-pass filter and a variable gain amplifier. The input signal of the whole system comes from a front-end mixer, the signal is filtered and amplified by a low-pass filter, and then a certain gain is provided by a variable gain amplifier. The low pass filter consists of a first order RC low pass filter and two biquad structures, the first biquad structure providing a constant 20dB gain and the second biquad structure providing no gain. The variable gain amplifier has two stages, each stage has the same structure, and the gain range of each stage is from 0dB to 9dB and takes 3dB as a step length. An alternating current coupling capacitor and a direct current divider resistor are connected between the first biquad structure and the second biquad structure and between the first variable gain amplifier and the second variable gain amplifier.
Fig. 3 is a schematic diagram of each of the bi-quadratic structures described in fig. 2.
As shown in fig. 3, the biquad structure is a fully differential structure, and includes four Gm cells and four capacitors C1 (C11, C12) and C2 (C21, C22), differential input signals are connected to the input terminals of Gm1, the output terminal of Gm1 is connected to the input terminal of Gm2 and is connected to C11 and C12, the output terminal of Gm2 is connected to the input terminal and is connected to the input terminal of Gm3, the output terminal of Gm3 is connected to the input terminal of Gm4 and is connected to C21 and C22, and the output terminal of Gm4 is cross-connected to the output terminal of Gm 1. The output of the whole biquad structure is the output of Gm 3. The gain of the structure is determined by the ratio of Gm4 and Gm1, the transition frequency is determined by Gm3, Gm4, C1 and C2 together, the quality factor Q value is determined by Gm3, Gm4, Gm2, C1 and C2 together, and in order to control the adjustable bandwidth of the filter, capacitors C1 and C2 used for each biquadratic structure and a capacitor C used for a first-order RC filter are formed by capacitor arrays. In order to control the quality factor Q constant while tuning the bandwidth, C1 and C2 must be increased or decreased by the same factor at the same time.
Fig. 4 is a schematic circuit diagram of the Gm cell of fig. 3.
As shown in fig. 4, each Gm cell has a nauta structure, and is formed by 6 inverters Inv1-Inv6, inverters Inv1 and Inv2 forming a differential input, inverters Inv4 and Inv5 cross-coupled to form a negative resistance, and inverters Inv3 and Inv6 forming a common mode feedback circuit. The positive and negative input signals are respectively connected with input ends of Inv1 and Inv2, an output end of Inv1 is connected with input ends of Inv3 and Inv5 and output ends of Inv5 and Inv6, and an output end of Inv2 is connected with input ends of Inv4 and Inv6 and output ends of Inv4 and Inv 3.
Fig. 5 is a schematic diagram of a capacitor array used in the low pass filter. The capacitor array is controlled by a 3-8 decoder, and eight different bandwidth settings are provided, wherein the bandwidth setting is from 151MHz to 256MHz, and the step length is 15 MHz.
Fig. 6 is a schematic diagram of the structure of the variable gain amplifier in the present invention.
As shown in fig. 6, the amplifier is a two-stage structure. The working principle is as follows: source negative feedback capacitor CSA zero point of a left half plane is introduced, the zero point is used for offsetting an output pole of the circuit, the bandwidth of the circuit is improved, and in order to work together with a low-pass filter of a front stage, the bandwidth of the variable gain amplifier must be larger than the maximum adjustable bandwidth (256 MHz) of the low-pass filter; in addition, although the circuit is of an open loop structure, the linearity of the amplifier is greatly improved due to the negative feedback action of the M2 tube, and the amplifier is provided with a high-linearity amplifierThe first stage of this circuit can be viewed as an enhanced source follower. The gain of the amplifier is the product of the transconductance ratio and the resistance ratio, RSIs composed of resistor array, and is controlled by source negative feedback resistor RSThe gain can be made variable. In the variable gain amplifier, an input signal is connected with the gate end of M1, and an active stage negative feedback resistor R is connected between the source ends of two M1 in parallelSAnd a capacitor CSMeanwhile, the source end of M1 is connected to the drain end of current source M4, the drain end of M1 is connected to resistor R2, the drain end of M1 is connected to the gate end of M2, and the drain end of M2 and negative feedback capacitor CSThe output of the first stage is the drain terminal of M1, and is connected to the gate terminal of the input pair transistor M3 of the second stage, the source terminal of M3 is connected to the drain terminal of the current source M5, and the drain terminal of M3 is connected to the load resistor R3. The output of the entire variable gain amplifier is at the drain of M3.
Fig. 7 is a schematic diagram of a resistor array used in a variable gain amplifier. The capacitor array is controlled by a 2-4 decoder, and has four different bandwidth settings, which are variable from 0 to 9dB in steps of 3 dB. Plus the constant 20dB gain from the pre-filter, the gain range of the present invention can vary from 20dB to 38 dB.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
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| CN115314057B (en) * | 2022-10-08 | 2022-12-23 | 深圳捷扬微电子有限公司 | Analog baseband circuit based on inverter technology |
| CN115296680B (en) * | 2022-10-08 | 2023-02-10 | 深圳捷扬微电子有限公司 | Radio frequency receiver circuit applied to ultra-wideband |
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