CN109672461B - DC offset compensation system and method - Google Patents

Abstract

The invention discloses a direct current offset compensation system, comprising: a signal processing path, a first compensation module, a second compensation module and a third compensation module. The first compensation module is used to compensate the DC offset of the second sub-processing path in the signal processing path, so that the first DC offset value output by the signal processing path is less than or equal to the first threshold value; the second compensation module is used for Based on the first DC offset value, the DC offset value of the first sub-processing path is compensated, so that the second DC offset value output by the signal processing path is less than or equal to the second threshold value; the third compensation module is used to compensate the DC offset value based on the second DC offset value. The offset value is used to compensate the DC offset of the signal processing path, so that the third DC offset value output by the signal processing path is less than or equal to the third threshold value. The invention also discloses a direct current offset compensation method.

Description

A DC offset compensation system and method

technical field

The present invention relates to the receiver technology of wireless communication, in particular to a direct current offset compensation system and method.

Background technique

In recent years, wireless communication technology has developed rapidly, and devices with wireless communication functions, such as smart phones, tablet computers, and notebook computers, are used more and more widely, which greatly facilitates people's daily work and life. The demand for portability of wireless devices makes low power consumption and high integration more and more important in the design of wireless transceivers; and in wireless transceivers, the design of the receiver is often the key.

In the common wireless receiver structure, the zero-IF receiver has great advantages in low power consumption and high integration, and is very suitable for application in today's wireless equipment. However, since the IF signal of a zero-IF receiver is at baseband, the DC offset of the mixer and IF amplifier in the receiver will be directly superimposed on the desired signal, which will seriously affect the dynamic range of the circuit. Therefore, in order to make the receiver work normally, a sampling DC offset compensation technology is required to effectively compensate the DC offset and reduce low-frequency noise.

In the related art, the DC offset compensation technology mainly includes technologies such as AC coupling and DC negative feedback. Because the AC coupling technology is difficult to apply in the zero-IF receiver, the circuit of the analog negative feedback scheme in the DC negative feedback is complex and the stability is poor, and the circuit of the digital negative feedback scheme in the DC negative feedback is simple; therefore, the zero-IF receiver is A digital negative feedback scheme is usually employed to compensate for DC offsets. However, the digital negative feedback scheme will be limited by the performance of the DC offset compensation system when compensating for the DC offset, resulting in low compensation accuracy.

SUMMARY OF THE INVENTION

In order to solve the problems existing in the prior art, the embodiments of the present invention are expected to provide a DC offset compensation system and method, which can improve the compensation accuracy of the DC offset in the receiver.

The technical solution of the embodiment of the present invention is realized as follows:

An embodiment of the present invention further provides a DC offset compensation system, the system includes: a signal processing path, the signal processing path includes a first sub-processing path and a second sub-processing path, and an output of the first sub-processing path The terminal is connected to the input terminal of the second sub-processing path; the system further includes: a first compensation module, a second compensation module and a third compensation module; wherein,

the first compensation module, configured to compensate the DC offset of the second sub-processing path, so that the first DC offset value output by the signal processing path is less than or equal to a first threshold;

The second compensation module is configured to compensate the DC offset of the first sub-processing path based on the first DC offset value, so that the second DC offset value output by the signal processing path is less than or equal to the second threshold;

The third compensation module is configured to compensate the DC offset of the signal processing path based on the second DC offset value, so that the third DC offset value output by the signal processing path is less than or equal to a third threshold value ; the third threshold is smaller than the second threshold.

In the above solution, the system further includes: a DC offset determination module; wherein,

The DC offset determination module is used to detect in real time whether the first DC offset value output by the signal processing path is less than or equal to the first threshold value; when the first DC offset value is greater than the first threshold value, trigger the a first compensation module;

The DC offset determination module is further configured to detect in real time whether the second DC offset value output by the signal processing path is less than or equal to a second threshold value; when the second DC offset value is greater than the second threshold value, trigger the first DC offset value. Two compensation modules;

The DC offset determination module is further configured to detect in real time whether the third DC offset value output by the signal processing path is less than or equal to a third threshold value; when the third DC offset value is greater than the third threshold value, trigger the third DC offset value. Three compensation modules.

In the above solution, the first compensation module is specifically configured to compensate the DC offset of the second sub-processing path by injecting DC at the input end of the second sub-processing path;

The second compensation module is specifically configured to compensate the DC offset of the first sub-processing path by injecting DC at the input end of the first sub-processing path;

The third compensation module is specifically configured to compensate the DC offset of the signal processing channel by injecting DC at the input end of the second sub-processing channel.

In the above solution, the second compensation module is further configured to compensate the DC offset of the first sub-processing channel when the DC amount injected at the input end of the second sub-processing channel is the first DC amount, so that the second DC offset value output by the signal processing path is less than or equal to the second threshold value; the first DC amount is when the DC offset value output by the signal processing path is the first DC offset value, the The direct current injected at the input end of the second sub-processing path;

The third compensation module is further configured to compensate the DC offset of the signal processing channel when the DC amount injected at the input end of the first sub-processing channel is the second DC amount, so that the signal processing The third DC offset value output by the channel is less than or equal to the third threshold value; the second DC amount is when the DC offset value output by the signal processing channel is the second DC offset value, the input end of the first sub-processing channel The amount of DC injected.

In the above solution, the gain of the first sub-processing path is greater than the gain of the second sub-processing path.

An embodiment of the present invention provides a DC offset compensation method. The method is applied to a signal processing path including a first sub-processing path and a second sub-processing path, wherein the output end of the first sub-processing path is connected to the second sub-processing path. input connections of processing paths; the method includes:

Compensating the DC offset of the second sub-processing path, so that the first DC offset value output by the signal processing path is less than or equal to a first threshold;

Compensating the DC offset of the first sub-processing path based on the first DC offset value, so that the second DC offset value output by the signal processing path is less than or equal to a second threshold;

Based on the second DC offset value, the DC offset value of the signal processing path is compensated, so that the third DC offset value output by the signal processing path is less than or equal to a third threshold value; the third threshold value is smaller than the second DC offset value threshold.

In the above solution, before the DC offset of the second sub-processing path is compensated so that the first DC offset value output by the signal processing path is less than or equal to the first threshold, the method further includes:

Detecting in real time whether the first DC offset value output by the signal processing path is less than or equal to the first threshold;

When the first DC offset value is greater than the first threshold value, perform compensation for the DC offset of the second sub-processing path, so that the first DC offset value output by the signal processing path is less than or equal to the first DC offset value threshold step;

Before compensating the DC offset of the first sub-processing path based on the second DC offset value, so that the second DC offset value output by the signal processing path meets the second threshold, the method further includes :

Detecting in real time whether the second DC offset value output by the signal processing path is less than or equal to the second threshold;

When the second DC offset value is greater than the first threshold, perform compensation for the DC offset of the first sub-processing path based on the first DC offset value, so that the second DC offset output by the signal processing path the step where the offset value is less than or equal to the second threshold;

Before compensating the DC offset of the signal processing path based on the second DC offset value, so that the second DC offset value output by the signal processing path is less than or equal to a third threshold, the method further includes :

Detecting in real time whether the third DC offset value output by the signal processing path is less than or equal to the third threshold;

When the third DC offset value is greater than a third threshold, perform compensation for the DC offset of the signal processing path based on the second DC offset value, so that the third DC offset value output by the signal processing path is less than or equal to a third threshold; the third threshold is smaller than the second threshold.

In the above solution, the compensating for the DC offset of the second sub-processing path includes: compensating for the DC offset of the second sub-processing path by injecting DC at the input end of the second sub-processing path ;

The compensating for the DC offset of the first sub-processing path includes: compensating for the DC offset of the first sub-processing path by injecting DC at the input end of the first sub-processing path;

The compensating for the DC offset of the signal processing path includes: compensating for the DC offset of the signal processing path by injecting DC at the input end of the second sub-processing path.

In the above solution, the DC offset value of the first sub-processing path is compensated based on the first DC offset value, so that the second DC offset value output by the signal processing path is less than or equal to a second threshold value ,include:

When the DC amount injected at the input end of the second sub-processing channel is the first DC amount, the DC offset of the first sub-processing channel is compensated, so that the second DC offset value output by the signal processing channel is less than or equal to the second threshold; the first DC amount is the DC amount injected by the input end of the second sub-processing path when the DC offset value output by the signal processing path is the first DC offset value;

Compensating the DC offset of the signal processing path based on the second DC offset value, so that the third DC offset value output by the signal processing path is less than or equal to a third threshold, including:

When the DC quantity injected at the input end of the first sub-processing path is the second DC quantity, the DC offset of the signal processing path is compensated, so that the third DC offset value output by the signal processing path is less than or is equal to the third threshold; the second DC amount is the DC amount injected by the input end of the first sub-processing path when the DC offset value output by the signal processing path is the second DC offset value.

In the above solution, the gain of the first sub-processing path is greater than the gain of the second sub-processing path.

It can be seen that the DC offset compensation system and method provided by the embodiments of the present invention are applied to a signal processing path including a first sub-processing path and a second sub-processing path, and the output end of the first sub-processing path is connected to the second sub-processing path. The input terminal of the channel is connected. First, the DC offset of the second sub-processing path is compensated, so that the first DC offset value output by the signal processing path is less than or equal to the first threshold; then, based on the first DC offset value, Compensating the DC offset of the first sub-processing path, so that the second DC offset value output by the signal processing path is less than or equal to a second threshold; finally, based on the second DC offset value, the signal The DC offset of the processing path is compensated, so that the third DC offset value output by the signal processing path is less than or equal to a third threshold; the third threshold is less than the second threshold.

It can be seen that, in the embodiment of the present invention, firstly, the DC offset of the second sub-processing path is compensated to reduce the DC offset of the second sub-processing path; then, the DC offset of the first sub-processing path is compensated. Compensation is performed to reduce the DC offset of the first sub-processing path; finally, the overall compensation is performed on the DC offset of the signal processing path, so that the DC offset of the signal processing path is reduced to a range that does not affect the normal operation of the signal processing path Inside.

Because before the DC offset of the first sub-processing path is superimposed on the DC offset of the second sub-processing path, the DC offset of the second sub-processing path has been compensated; and before the DC offset of the second sub-processing path is compensated; After the sub-processing paths are compensated, the overall compensation is also performed on the signal processing paths. Therefore, by segmenting the signal processing path and compensating for the DC offset of the segmented signal processing path in three stages, compared with the prior art, when the working state of the signal processing path is constant, the DC offset can be reduced. The performance index of the compensation module in the offset compensation system. Correspondingly, when the performance of the DC offset compensation system of the present invention is the same as that of the existing DC offset compensation system, the compensation precision of the DC offset can be improved even when the performance requirements are lowered. In addition, the compensation speed can be improved, the realization difficulty of the DC offset compensation system can be reduced, the system scale can be reduced, and the power consumption and area can be reduced.

Description of drawings

Figure 1 is a schematic structural diagram of a DC offset compensation system based on an AC coupling scheme;

FIG. 2 is a schematic structural diagram of a single-channel DC offset compensation system based on a digital negative feedback scheme;

FIG. 3 is a schematic structural diagram of a segmented DC offset compensation system based on a digital negative feedback scheme;

FIG. 4 is a schematic diagram of the realization of an existing DC offset compensation method based on a segmented DC offset compensation system;

FIG. 5 is a schematic diagram of the implementation flow of Embodiment 1 of the DC offset compensation method according to the present invention;

FIG. 6 is another structural schematic diagram of a segmented DC offset compensation system based on a digital negative feedback scheme;

FIG. 7 is a schematic diagram of an implementation of a DC offset compensation method according to an embodiment of the present invention;

8 is a schematic diagram of an optional composition structure of a DC offset compensation system according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of another optional composition structure of a DC offset compensation system according to an embodiment of the present invention.

Detailed ways

It can be seen from the background art that the DC offset compensation scheme in the related art has the problem of low compensation precision when compensating for the DC offset of the receiver.

For example, Figure 1 is a schematic structural diagram of a DC offset compensation system based on an AC coupling scheme. It can be seen from Figure 1 that the receiver includes a signal processing path, which includes a mixer, a filter, and an intermediate frequency amplifier. ; In the signal processing path, a DC blocking capacitor can be added to compensate for the DC offset. However, this scheme requires a large number of discrete capacitors, and the required size of the capacitors, therefore, it is not practical to integrate these capacitors, which makes the AC-coupling scheme difficult to apply in a zero-IF receiver.

Figure 2 is a schematic structural diagram of a single-channel DC offset compensation system based on a digital negative feedback scheme. As shown in Figure 2, the scheme is to feed back the DC offset value output by the signal processing path to the input of the filter by means of digital feedback. This reduces the DC offset value that needs to be compensated. Because the overall gain of the signal processing path is relatively large, the compensation module in the system needs to compensate the DC offset value very finely, and the performance index of the compensation module needs to be very high, which will make it difficult to implement a single-channel DC offset compensation system. big.

For example, in a signal processing path with a gain of 1000 times, when the DC offset value of the input terminal of the signal processing path is 1mv, the DC offset value of the output terminal of the signal processing path will reach 1000mv. If the DC offset of the signal processing path is compensated at the output end, the DC offset value output by the signal processing path is reduced to 10mv, so it is necessary to inject a reverse DC value of 990mv at the output end; The DC offset value of the signal processing channel is compensated to reduce the DC offset value of the signal processing channel output to 10mv. In this way, it is only necessary to inject a reverse DC value of 0.99mv at the input end, so that the DC offset value of the signal processing channel output can be adjusted by digital feedback. The value is fed back to the input of the filter to reduce the DC offset value that needs to be compensated.

Further, if the DC offset value output by the signal processing path is to be reduced to 10mv, the DC offset value at the input end of the signal processing path will be compensated to 0.01mv, which has very strict requirements for the performance index of the compensation module in the system. As a result, the implementation of the single-channel DC offset compensation system is relatively difficult. Therefore, the single-channel DC offset compensation system needs to make a compromise between the performance index and the compensation accuracy.

For the single-channel DC offset compensation system based on the digital negative feedback scheme, the related art proposes a segmented DC offset compensation system based on the digital negative feedback scheme. As shown in Figure 3, the segmented DC offset compensation system includes two channels. Compensation module, the two compensation modules divide the signal processing path in the receiver into a first sub-processing path and a second sub-processing path. FIG. 4 is a schematic diagram of the realization of the existing DC offset compensation method based on the segmented DC offset compensation system. Referring to FIG. 3 and FIG. 4 , in the prior art, the DC offset compensation methods based on the segmented DC offset compensation system are respectively Only the DC offset of the first sub-processing path and the signal processing path is compensated. However, after the DC offset of the first sub-processing path is compensated, the DC offset output after the compensation of the first sub-processing path will also pass through the second sub-processing path. Therefore, after the compensation of the first sub-processing path The output DC offset will be superimposed on the second sub-processing path, resulting in a larger DC offset compensation range for the signal processing path, so that the compensation accuracy is limited by the performance of the compensation module in the segmented DC offset compensation system. Accuracy is not high.

Based on this, the solutions provided by the embodiments of the present invention are used to compensate the DC offset of a signal processing path in a receiver, where the signal processing path includes a first sub-processing path and a second sub-processing path, wherein the first sub-processing path The output terminal of the processing path is connected to the input terminal of the second sub-processing path. First, the DC offset of the second sub-processing path is compensated to reduce the DC offset of the second sub-processing path; then, the DC offset of the first sub-processing path is compensated to reduce the first sub-processing path. DC offset of the sub-processing path; finally, overall compensation is performed for the DC offset of the signal processing path, so that the DC offset of the signal processing path is reduced to a range that does not affect the normal operation of the signal processing path.

Because before the DC offset of the first sub-processing path is superimposed on the DC offset of the second sub-processing path, the DC offset of the second sub-processing path has been compensated; and before the DC offset of the second sub-processing path is compensated; After the sub-processing paths are compensated, the overall compensation is also performed on the signal processing paths. Therefore, by segmenting the signal processing path and compensating for the DC offset of the segmented signal processing path in three stages, compared with the prior art, when the working state of the signal processing path is constant, the DC offset can be reduced. The performance index of the compensation module in the offset compensation system. Correspondingly, when the performance of the DC offset compensation system of the present invention is the same as that of the existing DC offset compensation system, the compensation precision of the DC offset can be improved even when the performance requirements are lowered.

The realization, functional characteristics and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

FIG. 5 is a schematic diagram of the implementation flow of Embodiment 1 of the DC offset compensation method of the present invention. Referring to FIG. 5 , the DC offset compensation method of this embodiment includes the following steps:

Step 101: Compensate the DC offset of the second sub-processing path, so that the first DC offset value output by the signal processing path is less than or equal to a first threshold;

The DC offset compensation method of this embodiment is applied in a DC offset compensation system, and is used for compensating for the DC offset of the signal processing path in the receiver. The DC offset compensation system may include the signal processing path, or may not include the signal processing path. The following will take the DC offset compensation system including the signal processing path as an example for detailed description. In addition to the signal processing path, the DC offset compensation system may further include a rough compensation module, a fine compensation module and a DC offset determination module. The signal processing path may include a mixer, a filter and an intermediate frequency amplifier, and the output end of the mixer is connected to the input end of the filter, and the output end of the filter is connected to the input end of the intermediate frequency amplifier.

Here, the coarse compensation module and the fine compensation module are connected in parallel at different positions of the signal processing path, and are used for compensating for the DC offset of the signal processing path. Generally, according to the signal flow direction of the signal processing path, the coarse compensation module can be connected before the fine compensation module; and, according to the position where the coarse compensation module and the fine compensation module are connected in parallel in the signal processing path, the signal processing path can be divided into a first sub-processing path and a second sub-processing path, the part of the signal processing path between the coarse compensation module and the fine compensation module is the first sub-processing path, and the part of the signal processing path after the fine compensation module is the second sub-processing path processing path.

Specifically, the coarse compensation module can be connected in parallel to the input end of the mixer or the input end of the filter; correspondingly, the fine compensation module can be connected in parallel to the input end of the filter or the intermediate frequency Amplifier input. The DC offset judgment module is used to detect the DC offset value output by the signal processing path. Therefore, the DC offset judgment module can not only be connected in series with the output end of the signal processing path, but also can be connected in parallel with the output of the mixer. output, or at the same time in parallel with the output of the filter.

For example, as shown in FIG. 3 , the coarse compensation module can be connected in parallel with the input end of the mixer, the fine compensation module can be connected in parallel with the input end of the intermediate frequency amplifier, and the DC offset judgment module can be connected in series with the output end of the intermediate frequency amplifier ; In this system, the first sub-processing path includes a mixer and a filter, and the second sub-processing path includes an intermediate frequency amplifier. FIG. 6 is another schematic structural diagram of a segmented DC offset compensation system based on a digital negative feedback scheme. Referring to FIG. 6 , the coarse compensation module can be connected in parallel with the input end of the mixer, and the fine compensation module can be In parallel with the input end of the filter, the DC offset judgment module is connected in series with the output end of the intermediate frequency amplifier; in this system, the first sub-processing path includes a mixer, and the second sub-processing path includes a filter and IF amplifier.

According to active or passive, the mixer can be divided into passive mixing switch circuit and active mixing switch circuit; according to different architectures, it can be divided into single-balanced architecture mixer and double-balanced architecture mixer. frequency converter. No matter what kind of mixer it is, it is used to convert the radio frequency signal to the intermediate frequency signal; specifically, the mixer moves the radio frequency voltage signal or the radio frequency current signal to the intermediate frequency under the driving of the local oscillator signal, thereby Output intermediate frequency voltage signal or intermediate frequency current signal.

The filter can be divided into active filter circuit and passive filter circuit according to active or passive; according to different modes, it can be divided into current mode filter and voltage mode filter; according to the gain type of the filter Different, it can be divided into a fixed gain filter and a variable gain filter. No matter what kind of filter it is, it is used to realize the frequency selective filtering of the intermediate frequency signal.

According to different modes, the intermediate frequency amplifier can be divided into a current mode intermediate frequency amplifier and a voltage mode intermediate frequency amplifier; according to different gain types, it can be further divided into an intermediate frequency amplifier with continuously adjustable gain and an intermediate frequency amplifier with discrete adjustable gain. No matter what kind of intermediate frequency amplifier, it is used to realize the amplification of intermediate frequency signal.

Of course, in addition to the mixer, the filter and the intermediate frequency amplifier, the signal processing path may also include other modules, which will not be described here.

The DC offset compensation method according to the embodiment of the present invention will be described in detail below with reference to FIG. 3 or FIG. 6 .

In one embodiment, the DC offset of the signal processing path may refer to a DC voltage offset, or may refer to a DC current offset. When the DC offset of the signal processing path is a DC voltage offset, the DC offset of the signal processing path is compensated by injecting a DC voltage; correspondingly, when the DC offset of the signal processing path is a DC current offset , the DC offset of the signal processing path is compensated by injecting a DC current. In the following embodiments, the DC offset of the signal processing path is described in detail by taking the DC voltage offset as an example.

When the fine compensation module compensates the DC offset of the second sub-processing path, it can be performed on the premise of turning off the first sub-processing path and the coarse compensation module, or it can be performed without turning off the first sub-processing path. and the premise of the rough compensation module. In this embodiment, in order to reduce the performance of the DC offset determination module when compensating for the DC offset of the signal processing path, the fine compensation module will turn off the first sub-processing path and the rough compensation module on the premise of turning off the first sub-processing path and the rough compensation module. An example of compensating for the DC offset of the two sub-processing paths will be described in detail.

In one embodiment, the fine compensation module is used to compensate the DC offset of the second sub-processing path, and the second sub-processing path, the fine compensation module and the DC offset determination module need to be turned on, and the first sub-processing path and the DC offset determination module need to be turned off at the same time. Coarse compensation module. Here, the switching power supply can be used to control each module separately, so that the module can be turned on when the module is powered on, and the module can be turned off when the module is powered off.

In an embodiment, the DC offset determination module can detect the DC offset value output by the signal processing path in real time, and in each stage of the DC offset compensation, can generate a corresponding control signal according to the detected DC offset value. . For example, when the DC offset value detected by the DC offset determination module is greater than a preset threshold value, a first control signal is generated, and the first control signal indicates that the signal processing path or the corresponding sub-processing path in the signal processing path needs to be adjusted. The DC offset is compensated; when the DC offset value detected by the DC offset determination module is less than or equal to the preset threshold, a second control signal is generated, and the second control signal indicates that the signal processing path or the corresponding signal processing path in the signal processing path is stopped. The DC offset of the sub-processing path is compensated.

In each stage of the DC offset compensation, the DC offset determination module can send the generated control signal to the corresponding compensation module; after the corresponding compensation module receives the control signal, the corresponding compensation operation is performed according to the received control signal .

For example, the DC offset determination module may send the generated first control signal to a rough compensation module, and after receiving the first control signal, the rough compensation module compensates for the DC offset of the first sub-processing path; Alternatively, the DC offset determination module sends the generated second control signal to the coarse compensation module, and after receiving the second control signal, the coarse compensation module stops compensating for the DC offset of the first sub-processing path. The DC offset determination module may also send the generated first control signal to the fine compensation module, and after the fine compensation module receives the first control signal, the DC offset of the second sub-processing path or the entire signal processing path is adjusted. or, the DC offset determination module sends the generated second control signal to the fine compensation module, and after receiving the second control signal, the fine compensation module stops compensating the second sub-processing path or the entire The DC offset of the signal processing path is compensated.

It should be noted that, which compensation module the DC offset determination module sends the generated control signal to, needs to first determine which compensation stage it is in.

Specifically, in the first compensation stage, the DC offset determination module detects the first DC offset value output by the signal processing path in real time, and determines whether the first DC offset value is less than or equal to the first threshold; when When the first DC offset value is greater than the first threshold, the DC offset determination module feeds back the generated first control information to the fine compensation module. After receiving the first control information, the fine compensation module injects a DC voltage opposite to the DC offset of the second sub-processing path at the input end of the second sub-processing path, so as to compensate the second sub-processing path. The DC offset of the sub-processing path is compensated.

During the process of injecting the DC voltage into the input terminal of the second sub-processing path by the fine compensation module, when the DC offset determination module detects that the output first DC offset value is less than or equal to the first threshold value, The DC offset determination module feeds back the generated second control signal to the fine compensation module. After the fine compensation module receives the second control signal, it will no longer inject the DC voltage at the input end of the second sub-processing channel, and at the same time, inject the first voltage into the input end of the second sub-processing channel. The DC amount is stored, so that the fine compensation module can keep the injected first DC amount unchanged during the process of compensating for the DC offset of the first sub-processing path.

For example, the first threshold is 1mv, when the DC offset determination module detects that the first DC offset value is less than or equal to 1mv, the DC offset determination module will generate a first control signal, and use the The first control signal is sent to the fine compensation module.

The first threshold can be set according to actual needs, and the specific setting will be based on the reference that does not affect the performance of the second sub-processing path; that is, a certain DC offset can be allowed in the second sub-processing path, As long as the existing DC offset does not affect the performance of the second sub-processing path. In this way, the normal operation of the receiver can be ensured under the premise of reducing the performance index of the fine compensation module, thereby reducing the difficulty of implementing the DC offset compensation system, reducing the system scale, and reducing power consumption and area.

Step 102: Compensate the DC offset of the first sub-processing path based on the first DC offset value, so that the second DC offset value output by the signal processing path is less than or equal to a second threshold;

Here, the first sub-processing channel and the rough compensation module are turned on, and when the DC amount injected at the input end of the second sub-processing channel is the first DC amount, the DC offset of the first sub-processing channel is performed. compensation, so that the second DC offset value output by the signal processing path is less than or equal to the second threshold value. Wherein, the first DC amount is when the first sub-processing path is in an off state and the DC offset value output by the signal processing path is the first DC offset value, the second sub-processing path The amount of DC injected at the input.

Specifically, in the second compensation stage, on the premise of maintaining the first DC amount, the DC offset determination module detects the second DC offset value output by the signal processing path in real time, and determines the second DC offset whether the value is less than or equal to the second threshold; when the second DC offset value is greater than the second threshold, the DC offset determination module feeds back the generated first control signal to the rough compensation module. The rough compensation module compensates the DC offset of the first sub-processing path by injecting a DC voltage opposite to the DC offset of the first sub-processing path at the input end of the first sub-processing path.

During the process of injecting the DC voltage into the input terminal of the first sub-processing path by the rough compensation module, when the DC offset determination module detects that the output second DC offset value is less than or equal to the second threshold, the The DC offset determination module feeds back the generated second control signal to the rough compensation module. After the rough compensation module receives the second control signal, it will no longer inject the DC voltage at the input end of the first sub-processing channel, and at the same time, inject the second voltage into the input end of the first sub-processing channel. The direct current quantity is stored, so that the rough compensation module can keep the injected second direct current quantity unchanged during the process of compensating for the direct current offset of the signal processing path.

The second threshold can be set according to actual needs, and the specific setting will be based on the reference that does not affect the performance of the first sub-processing path; that is, a certain DC offset can be allowed in the first sub-processing path, As long as the existing DC offset does not affect the performance of the first sub-processing path. In this way, the normal operation of the receiver can be ensured under the premise of reducing the performance index of the rough compensation module, thereby reducing the difficulty of implementing the DC offset compensation system, reducing the system scale, and reducing power consumption and area.

Step 103: Compensate the DC offset of the signal processing path based on the second DC offset value, so that the third DC offset value output by the signal processing path is less than or equal to a third threshold; the third threshold less than the second threshold.

Here, when the DC quantity injected at the input end of the first sub-processing path is the second DC quantity, the DC offset of the entire signal processing path is compensated, so that the third DC offset value output by the signal processing path is less than or equal to the third threshold. The second DC quantity is the DC quantity injected by the input end of the first sub-processing path when the DC offset value output by the signal processing path is the second DC offset value.

Specifically, in the third compensation stage, the DC offset determination module detects the third DC offset value output by the signal processing path in real time, and determines whether the third DC offset value is less than or equal to the third threshold; When the third DC offset value is greater than the third threshold value, the DC offset determination module feeds back the generated first control information to the fine compensation module. After the fine compensation module receives the first control information, on the basis of maintaining the first DC flow, the input end of the second sub-processing channel injects the DC offset with the second sub-processing channel. The opposite DC voltage is used to compensate for the DC offset of the entire signal processing path.

During the process of injecting the DC voltage into the input terminal of the second sub-processing path by the fine compensation module, when the DC offset determination module detects that the output third DC offset value is less than or equal to the third threshold, the The DC offset determination module feeds back the generated second control signal to the fine compensation module. After the fine compensation module receives the second control signal, it will no longer inject a DC voltage at the input of the second sub-processing path, and at the same time, inject the entire compensation stage into the input of the second sub-processing path The third DC quantity at the terminal is stored to ensure the subsequent normal operation of the signal processing path in the receiver.

The third threshold can be set according to actual needs, and the specific setting will be based on the performance that does not affect the entire signal processing path; that is, a certain DC offset can be allowed in the signal processing path, as long as the DC offset exists. It is sufficient that the performance of the signal processing path is not affected.

In the following, with reference to FIG. 3 , an example of the DC offset compensation method according to the embodiment of the present invention will be described in detail with respect to the segmented-based DC offset compensation system.

FIG. 7 is a schematic diagram of the implementation of the DC offset compensation method according to the embodiment of the present invention. Referring to FIG. 7 , the DC offset compensation method according to the embodiment of the present invention is performed in three stages.

It is assumed that the gain of the signal processing path is 1000, wherein the gain of the first sub-processing path is 100, and the gain of the second sub-processing path is 10. Before compensating the DC offset of the signal processing path, the initial DC offset value output by the signal processing path is 1010mv, wherein, there is a DC offset of 1mv at the input end of the first sub-processing path, and at the same time, the second sub-processing path has a DC offset value of 1010mv. There is also a 1mv DC offset at the input.

In the first compensation stage, the second sub-processing path, the fine compensation module and the DC offset determination module are turned on, and the coarse compensation module and the first sub-processing path are turned off at the same time; the fine compensation module is based on the first control signal generated by the DC offset determination module, The DC offset of the second sub-processing path is compensated, and when the DC offset determination module detects that the first DC offset value output by the signal processing path is less than or equal to the first threshold, the generated second control signal is fed back to the The fine compensation module, so that the fine compensation module stops compensating for the DC offset of the second sub-processing path. Here, the first threshold can be set to 1mv, since the gain of the second sub-processing path is 10; therefore, the DC offset value of the input end of the second sub-processing path is compensated to 0.1mv, correspondingly, the fine The first DC flow rate injected by the compensation module into the input end of the second sub-processing channel is 0.9mv, and the compensation range is 0.9mv. After the first-stage compensation is completed, the first sub-processing path and the rough compensation module will be turned on. At this time, the DC offset value output by the signal processing path is 1001mv.

In the second compensation stage, the first sub-processing channel and the rough compensation module are turned on, and the first DC flow rate is kept unchanged. The offset is compensated, and when the DC offset determination module detects that the second DC offset value output by the signal processing path is less than or equal to the second threshold, the generated second control signal is fed back to the rough compensation module, so that the rough compensation module Stops compensating for the DC offset of the first subprocessing path. Here, the second threshold can be set to 11mv, since the gain of the first sub-processing path is 100, the gain of the second sub-processing path is 10, and the second DC offset value is not exactly the same as that of the first sub-processing path. The DC offset of the processing path, the second sub-processing path also superimposes the DC offset of 1mv; therefore, the DC offset value of the input end of the first sub-processing path is compensated to 0.01mv, correspondingly, the rough compensation module The second DC quantity injected into the input end of the first sub-processing path is 0.99mv, and the compensation range is 0.99mv.

In the third compensation stage, keeping the second DC quantity unchanged, the fine compensation module compensates the DC offset of the entire signal processing path according to the first control signal generated by the DC offset determination module, and detects the DC offset in the DC offset determination module. When the third DC offset value output by the signal processing path is less than or equal to the third threshold, the generated second control signal is fed back to the fine compensation module, so that the fine compensation module stops compensating for the DC offset of the entire signal processing path. Here, the third threshold can be set to 10mv, since the gain of the first sub-processing path is 100, and the gain of the second sub-processing path is 10; therefore, before the third compensation stage, the input of the second sub-processing path The DC offset value of the second sub-processing channel is 1.1mv, so the fine compensation module injects 0.1 mV at the input end of the second sub-processing channel on the basis of the first DC amount that has been injected into the input end of the second sub-processing channel. mv, that is, the third DC offset value output by the signal processing path can be made smaller than or equal to the third threshold value.

It can be seen from the above description that the DC offset value output by the signal processing path is 1010mv. Using the DC offset compensation method of the embodiment of the present invention, if the DC offset value output by the signal processing path is to be reduced to 10mv, the rough The compensation module only needs to drop to 0.01mv, and the compensation range of the fine compensation module is 0.9mv (that is, a maximum of 0.9mv is injected in the first stage). However, if the DC offset compensation method based on the single-channel DC offset compensation system is used, if the DC offset value output by the signal processing path is to be reduced to 10mv, under the same working state of the signal processing path, the compensation module needs to It is reduced to 0mv, so the realization of the single-channel DC offset compensation system is very difficult. However, using the existing DC offset compensation method based on the segmented DC offset compensation system, if the DC offset value output by the signal processing path is to be reduced to 10mv, the rough compensation module needs to be reduced to 0.01mv, while the fine compensation module needs to be reduced to 0.01mv. The compensation range is 1mv. In this way, when the existing DC offset compensation method compensates the DC offset of the signal processing path, the required compensation range is relatively large, so the compensation speed is relatively slow.

Therefore, in the DC offset compensation method provided by the embodiment of the present invention, before compensating the DC offset of the first sub-processing path, by compensating the DC offset of the second sub-processing path, the compensation in the DC offset compensation system can be reduced. The compensation range of the module makes the compensation speed larger. Meanwhile, after the DC offset of the first sub-processing path is compensated, the overall compensation of the DC offset of the signal processing path can be performed, so that the compensation precision can be higher. In addition, in the process of compensating the DC offset of the sub-processing path, a certain DC offset is allowed without affecting the performance of the sub-processing path, so that the performance index of the compensation module in the DC compensation system can be reduced, thereby reducing the DC offset. Compensate the realization difficulty of the system, reduce the system scale, reduce power consumption and area.

In addition, the gain of the first sub-processing path may be greater than the gain of the second sub-processing path, may also be smaller than the gain of the second sub-processing path, or may be equal to the gain of the second sub-processing path; The relative magnitude of the gain of the first sub-processing path and the gain of the second sub-processing path will not be limited in this embodiment of the present invention.

In order to implement the method of the embodiment of the present invention, the embodiment of the present invention further provides a DC offset compensation system, which is used to realize the specific details of the above-mentioned DC offset compensation method, and achieve the same effect.

FIG. 8 is an optional structural schematic diagram of a DC offset compensation system according to an embodiment of the present invention. Referring to FIG. 8 , the DC offset compensation system of this embodiment includes: a signal processing path 21 , and the signal processing path 21 includes a first a sub-processing path 211 and a second sub-processing path 212, the output end of the first sub-processing path 211 is connected to the input end of the second sub-processing path 212; the system further includes: a first compensation module 22, a second sub-processing path 212 Compensation module 23 and third compensation module 24; wherein,

The first compensation module 22 is configured to compensate the DC offset of the second sub-processing path, so that the first DC offset value output by the signal processing path is less than or equal to a first threshold;

The second compensation module 23 is configured to compensate the DC offset of the first sub-processing path based on the first DC offset value, so that the second DC offset value output by the signal processing path is less than or is equal to the second threshold;

The third compensation module 24 is configured to compensate the DC offset of the signal processing path based on the second DC offset value, so that the third DC offset value output by the signal processing path is less than or equal to the third DC offset value. threshold; the third threshold is smaller than the second threshold.

Optionally, the DC offset compensation system in this embodiment further includes: a DC offset determination module 25; wherein,

The DC offset determination module 25 is used to detect in real time whether the first DC offset value output by the signal processing path is less than or equal to the first threshold; when the first DC offset value is greater than the first threshold, trigger the the first compensation module 22;

The DC offset determination module 25 is further configured to detect in real time whether the second DC offset value output by the signal processing path is less than or equal to a second threshold; when the second DC offset value is greater than the second threshold, trigger the the second compensation module 23;

The DC offset determination module 25 is further configured to detect in real time whether the third DC offset value output by the signal processing path is less than or equal to a third threshold; when the third DC offset value is greater than the third threshold, trigger the The third compensation module 24 .

Optionally, the first compensation module 22 is specifically configured to compensate the DC offset of the second sub-processing path by injecting DC at the input end of the second sub-processing path;

The second compensation module 23 is specifically configured to compensate the DC offset of the first sub-processing path by injecting DC at the input end of the first sub-processing path;

The third compensation module 24 is specifically configured to compensate the DC offset of the signal processing path by injecting DC at the input end of the second sub-processing path.

It should be noted that the first compensation module 22, the second compensation module 23 and the third compensation module 24 are collectively referred to as compensation modules hereinafter. It can be a module formed by mixing and superimposing some electronic devices for processing analog signals and some electronic devices for processing digital signals. In this embodiment, the compensation module will briefly illustrate the implementation method of compensating for DC offset by taking a module formed by mixing and superposing some electronic devices for processing analog signals and some electronic devices for processing digital signals as an example.

Wherein, the compensation module may include a digital logic control unit and an analog-to-digital conversion unit. First, the digital logic control unit performs code word control on the analog-to-digital conversion unit based on the DC offset judgment value fed back by the DC offset judgment module, so that the analog-to-digital conversion unit generates a corresponding DC current or DC voltage and injects it into the signal processing path. , so as to compensate the DC offset of the signal processing path.

Optionally, the second compensation module 23 is further configured to compensate the DC offset of the first sub-processing channel when the DC amount injected at the input end of the second sub-processing channel is the first DC amount , so that the second DC offset value output by the signal processing path is less than or equal to the second threshold value; the first DC amount is when the DC offset value output by the signal processing path is the first DC offset value, so the direct current injected at the input end of the second sub-processing path;

The third compensation module 24 is further configured to compensate the DC offset of the signal processing channel when the DC amount injected at the input end of the first sub-processing channel is the second DC amount, so that the signal The third DC offset value output by the processing path is less than or equal to the third threshold value; the second DC amount is when the DC offset value output by the signal processing path is the second DC offset value, the input of the first sub-processing path The amount of DC injected at the terminal.

Optionally, the gain of the first sub-processing path 211 is greater than the gain of the second sub-processing path 212 .

In this embodiment, the third compensation module 24 can use the first compensation module 22 to specifically implement its functions, as shown in FIG. 9 , another optional structural schematic diagram of the DC offset compensation system according to the embodiment of the present invention. Specifically, the first compensation module 22 is configured to compensate the DC offset of the second sub-processing path, so that the first DC offset value output by the signal processing path is less than or equal to the first threshold; so The first compensation module 22 is further configured to compensate the DC offset of the signal processing path based on the second DC offset value, so that the third DC offset value output by the signal processing path is less than or equal to the third DC offset value. threshold; the third threshold is smaller than the second threshold.

When the DC offset compensation system provided in the above embodiment performs DC offset compensation, only the division of the above program modules is used as an example for illustration. The internal structure is divided into different program modules to perform all or part of the processing described above. In addition, the DC offset compensation system provided by the above embodiments and the DC offset compensation method embodiments belong to the same concept, and the specific implementation process thereof is detailed in the method embodiments, which will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and scope of the present invention are included in the protection scope of the present invention.

Claims (10)

1. A dc offset compensation system, the system comprising: the signal processing path comprises a first sub-processing path and a second sub-processing path, and the output end of the first sub-processing path is connected with the input end of the second sub-processing path; the system further comprises: the device comprises a first compensation module, a second compensation module and a third compensation module; wherein,

the first compensation module is used for compensating the direct current offset of the second sub-processing path so that a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value;

the second compensation module is configured to compensate for the dc offset of the first sub-processing path based on the first dc offset value, so that a second dc offset value output by the signal processing path is smaller than or equal to a second threshold;

the third compensation module is configured to compensate for the dc offset of the signal processing path based on the second dc offset value, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; the third threshold is less than the second threshold.

2. The system of claim 1, further comprising: a direct current offset discrimination module; wherein,

the direct current offset judgment module is used for detecting whether a first direct current offset value output by the signal processing path is smaller than or equal to a first threshold value or not in real time; when the first constant loss adjusting value is larger than a first threshold value, triggering the first compensation module;

the direct current offset judgment module is also used for detecting whether a second direct current offset value output by the signal processing channel is smaller than or equal to a second threshold value in real time; when the second direct current offset value is larger than a second threshold value, triggering the second compensation module;

the direct current offset judgment module is also used for detecting whether a third direct current offset value output by the signal processing path is smaller than or equal to a third threshold value in real time; and when the third direct current offset value is larger than a third threshold value, triggering the third compensation module.

3. The system according to claim 1, wherein the first compensation module is configured to compensate for dc offsets of the second sub-processing path by injecting dc at an input of the second sub-processing path;

the second compensation module is specifically configured to compensate for dc offset of the first sub-processing path by injecting dc into an input end of the first sub-processing path;

the third compensation module is specifically configured to compensate for dc offset of the signal processing path by injecting dc into the input end of the second sub-processing path.

4. The system according to claim 3, wherein the second compensation module is further configured to compensate the dc offset of the first sub-processing path when the dc amount injected at the input end of the second sub-processing path is the first dc amount, so that the second dc offset value output by the signal processing path is smaller than or equal to a second threshold value; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;

the third compensation module is further configured to compensate for a dc offset of the signal processing path when the dc quantity injected at the input end of the first sub-processing path is a second dc quantity, so that a third dc offset value output by the signal processing path is smaller than or equal to a third threshold; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.

5. The system of claim 1, wherein the gain of the first sub-processing path is greater than the gain of the second sub-processing path.

6. The direct current offset compensation method is applied to a signal processing path comprising a first sub-processing path and a second sub-processing path, wherein an output end of the first sub-processing path is connected with an input end of the second sub-processing path; the method comprises the following steps:

compensating the direct current offset of the second sub-processing path to enable a first direct current offset output by the signal processing path to be smaller than or equal to a first threshold value;

compensating the direct current offset of the first sub-processing path based on the first direct current offset value, so that a second direct current offset value output by the signal processing path is smaller than or equal to a second threshold value;

compensating the direct current offset of the signal processing path based on the second direct current offset value so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; the third threshold is less than the second threshold.

7. The method of claim 6, wherein before compensating for the dc offset of the second sub-processing path such that the first dc offset of the signal processing path output is less than or equal to the first threshold, the method further comprises:

detecting whether a first constant loss adjusting value output by the signal processing channel is smaller than or equal to a first threshold value in real time;

when the first dc offset is greater than a first threshold, performing compensation on the dc offset of the second sub-processing path to make the first dc offset output by the signal processing path less than or equal to the first threshold;

before the compensating the dc offset of the first sub-processing path based on the first dc offset value so that a second dc offset value output by the signal processing path is less than or equal to a second threshold value, the method further includes:

detecting whether a second direct current offset value output by the signal processing channel is smaller than or equal to a second threshold value in real time;

when the second dc offset value is greater than a second threshold, performing a step of compensating the dc offset of the first sub-processing path based on the first dc offset value, so that the second dc offset value output by the signal processing path is less than or equal to the second threshold;

before the compensating the dc offset of the signal processing path based on the second dc offset value so that a third dc offset value output by the signal processing path is less than or equal to a third threshold, the method further includes:

detecting whether a third direct current offset value output by the signal processing path is smaller than or equal to a third threshold value in real time;

when the third dc offset value is greater than a third threshold, performing compensation on the dc offset of the signal processing path based on the second dc offset value, so that the third dc offset value output by the signal processing path is less than or equal to the third threshold; and the third threshold is smaller than the second threshold.

8. The method of claim 6, wherein the compensating for DC offsets of the second sub-processing path comprises: compensating the DC offset of a second sub-processing path in a mode of injecting DC into the input end of the second sub-processing path;

the compensating the dc offset of the first sub-processing path includes: compensating for DC offset of the first sub-processing path by injecting DC into an input of the first sub-processing path;

the compensating the dc offset of the signal processing path includes: and compensating the DC offset of the signal processing path by injecting DC into the input end of the second sub-processing path.

9. The method of claim 8, wherein the compensating the dc offset of the first sub-processing path based on the first dc offset value to make a second dc offset value output by the signal processing path less than or equal to a second threshold value comprises:

when the direct current quantity injected into the input end of the second sub-processing path is the first direct current quantity, compensating the direct current offset of the first sub-processing path so as to enable a second direct current offset value output by the signal processing path to be smaller than or equal to a second threshold value; the first direct current is the direct current injected by the input end of the second sub-processing path when the direct current offset value output by the signal processing path is the first direct current offset value;

the compensating, based on the second dc offset value, the dc offset of the signal processing path so that a third dc offset value output by the signal processing path is less than or equal to a third threshold includes:

when the direct current quantity injected into the input end of the first sub-processing path is a second direct current quantity, compensating the direct current offset of the signal processing path so as to enable a third direct current offset value output by the signal processing path to be smaller than or equal to a third threshold value; and the second direct current quantity is the direct current quantity injected by the input end of the first sub-processing path when the direct current loss regulating value output by the signal processing path is the second direct current loss regulating value.

10. The method of claim 6, wherein the gain of the first sub-processing path is greater than the gain of the second sub-processing path.

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