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CN102244019A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN102244019A
CN102244019A CN201010266857XA CN201010266857A CN102244019A CN 102244019 A CN102244019 A CN 102244019A CN 201010266857X A CN201010266857X A CN 201010266857XA CN 201010266857 A CN201010266857 A CN 201010266857A CN 102244019 A CN102244019 A CN 102244019A
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CN
China
Prior art keywords
layer
capping layer
bump
projection
capping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201010266857XA
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English (en)
Inventor
徐君蕾
何明哲
郑明达
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN201610083738.8A priority Critical patent/CN105632953A/zh
Publication of CN102244019A publication Critical patent/CN102244019A/zh
Pending legal-status Critical Current

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Abstract

本发明揭示一种半导体装置及其制造方法。该制造方法包括在一封盖(encapsulating)层上方形成一凸块下金属(under-bump metallurgy，UBM)层，接着在封盖层的开口内的凸块下金属层上形成一凸块(bump)层。在从封盖层的上表面去除多余的凸块层材料之后，去除封盖层直至凸块层的一顶部突出于封盖层的上表面。本发明可避免UBM底切问题。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，尤其涉及一种凸块(bump)结构的制造方法。
背景技术
现今的集成电路都是由数百万个有源(active)及/或无源(passive)装置所组成，例如晶体管及电容。这些装置在初始时彼此隔离，但后来会内连在一起而构成功能性电路。通常内连结构包括横向内连接(例如，金属线(导线))及直向内连接(例如，介层连接窗(via)及接触窗(contact))。而这些内连线对于现今集成电路的效能及密度限制产生越来越多影响。接合垫形成于内连结构的顶部并露出于各个芯片的表面。芯片通过了接合垫而电性连接至封装结构或另一芯片。接合垫可用于打线接合工艺(wire bonding)及倒装芯片接合工艺(flip-chip bonding)。在典型的凸块工艺(bumping process)中，内连线结构形成于金属化层上，接着形成底层凸块金属化(UBM)层及进行焊球(solder ball)植入。
倒装芯片封装利用凸块进行芯片的I/O接合垫与基底之间或与封装的引线架(lead frame)之间的电性连接。就结构上来说，凸块实际上包括了凸块本身及位于凸块与I/O接合垫之间的凸块下金属(under-bump metallurgy，UBM)层。凸块下金属层通常包括依序排置的一粘着层、一阻障层及一润湿(wetting)层。取决于凸块本身所使用的材料，其可分为焊料凸块、金凸块、铜柱凸块、混金属凸块。近来，已提出了铜内连柱(copper interconnect post)技术。其利用铜柱取代焊料凸块，以将电子部件连接至基底。铜内连柱可得到具有最小凸块架桥(bump bridging)机率的微小间距，以降低电路的电容负载并容许电子部件在高频下操作。而仍需以焊料合金覆盖凸块结构以及连接电子部件。
通常在凸块下金属层的湿蚀刻中，会产生各向同性蚀刻轮廓，其中所有方向的蚀刻率是一样的，使被蚀刻的凸块下金属层发生底切(undercutting)，其造成了不必要的线宽损失。湿蚀刻所造成的底切将引发应力集中，而在微间距设计中发生凸块侧壁剥离、凸块破裂及凸块架桥。虽然蚀刻工艺中本来就会发生底切问题，然而其不利于内连线的长期可靠度。底切使得焊料凸块与芯片的接合垫之间的接合变差，因而危及焊料凸块结构的完整性，导致芯片提早失效。
发明内容
为了解决现有技术的问题，在本发明一实施例中，一种半导体装置的制造方法，包括：在具有一金属垫区的一半导体基底上方形成一封盖层，其中封盖层具有一开口露出一部分的该金属垫区；在露出的金属垫区部分上方的封盖层的开口内形成一凸块下金属层；在凸块下金属层上方形成一凸块层，以填入封盖层的开口且延伸至封盖层的上表面；以及自封盖层的上表面去除凸块层。
本发明另一实施例中，一种半导体装置的制造方法，包括：在具有一金属垫区的一半导体基底上方形成一封盖层，其中封盖层具有一开口露出一部分的金属垫区；顺着封盖层的开口的底部及侧壁形成一凸块下金属层且延伸至封盖层的上表面；在凸块下金属层上方形成一凸块层，其中凸块层填入封盖层的开口且位于封盖层的上表面上；以及自封盖层的上表面去除凸块层及凸块下金属层。
本发明又一实施例中，一种半导体装置，包括：一半导体基底，包括一金属垫区；一封盖层，位于半导体基底上方，且未覆盖金属垫区的一第一部分；一凸块层，局部形成于封盖层内且电性连接至金属垫区的第一部分，其中凸块层的一顶部突出于封盖层的上表面；以及一凸块下金属层，形成于封盖层内且电性连接至金属垫区的第一部分，其中凸块下金属层形成于凸块层与金属垫区的第一部分之间。
本发明可避免UBM底切问题。
附图说明
图1至图6示出根据一实施例的凸块结构的制造方法中各个阶段的剖面示意图。
图7至图9示出根据另一实施例的凸块结构的制造方法中各个阶段的剖面示意图。
其中，附图标记说明如下：
10～基底；
12～接触区/金属垫区；
12a～部分；
14～保护层；
15～第一开口；
16～封盖层；
18～掩模层；
20～第二开口；
22、22a～凸块下金属层；
22p、24p～顶部；
24～凸块层；
24a～第一部；
24b～第二部；
26a～第一上盖层；
26b～第二上盖层；
26c～第三上盖层；
28、30～回蚀刻工艺/平坦化工艺；
32、32a～凸块结构；
T1、T2～厚度。
具体实施方式
本文提供了使用于半导体装置(其上具有焊料凸块、铜柱、后护层内连接(post passivation interconnect)及/或硅通孔电极(through-silicon via，TSV))的一种凸块工艺，以应用于倒装芯片构装(flip-chip assembly)、晶片级芯片尺寸封装(wafer-level chip scale package，WLCSP)、三维集成电路(three-dimensional integrated circuit，3DIC)堆叠及/或任何先进封装技术领域。本文实施例关于使用于半导体装置的凸块下金属层的制造方法。在以下的说明书全文中，所提出许多特定细节部分，用以充分了解本发明。然而，任何本领域普通技术人员将会了解本发明能够在没有这些特定细节情形下实行。在一些范例中，并未详述公知结构及工艺，以避免使本发明产生不必要的混淆。本说明书全文中所提及关于″一实施例″的意思是指有关于本实施例中所提及特定的特征(feature)、结构、或特色包含于本发明的至少一实施例中。因此，本说明书全文中各处所出现的″在一实施例中″用语所指的并不全然表示为相同的实施例。另外，特定的特征、结构、或特色能以任何适当方式而与一或多个实施例作结合。可以理解的是以下的附图并未依照比例示出，而仅仅提供说明之用。
此处，图1至图6示出根据一实施例的凸块结构的制造方法中各个阶段的剖面示意图。
请参照图1，用于凸块制造的基底10可包括用于半导体集成电路制造的半导体基底，且可在其中及/或其上形成集成电路。半导体基底的定义为任何含半导体材料的结构体，其包括但不局限于硅块材(bulk silicon)、半导体晶片、绝缘层上覆硅(silicon-on-insulator，SOI)基底或锗化硅基底。也可使用其他包括三族、四族、五族元素的半导体材料。基底10可进一步包括多个隔离特征部件(未示出)，例如浅沟槽隔离(shallow trench isolation，STI)特征部件或局部硅氧化(local oxidation of silicon，LOCOS)特征部件。隔离特征部件可定义及隔离各种不同的微电子元件(未示出)。各种不同的微电子元件可形成于基底10内，包括：晶体管(例如，金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)、互补式金属氧化物半导体晶体管(complementary metal oxide semiconductor(CMOS)transistor)、双极结晶体管(bipolar junction transistor，BJT)、高电压晶体管、高频晶体管、p型沟道及/或n型沟道场效应晶体管(PFET/NFET)等等)、电阻、二极管、电容、电感、熔丝、及其他适当的元件。进行不同工艺以形成不同的微电子元件，包括：沉积、蚀刻、注入、光刻、退火及其他适当的工艺。内连接这些微电子元件而形成集成电路装置，例如，逻辑装置、存储装置(如，静态随机存取存储器(static random access memory，SRAM)、射频(radio frequency，RF)装置、输入/输出(I/O)装置、芯片系统(system-on-chip，SoC)装置、其组合及其他适当类型的装置。
在一些实施例中，基底10还包括位于机体电路上方的内层(inter-layer)介电层及金属化结构。位于金属化结构内的内层介电层包括：低介电常数材料、未掺杂硅玻璃(un-doped silicon glass，USG)、氮化硅、氮氧化硅、或其他一般所使用的材料。低介电常数材料的介电常数(k值)可低于3.9或低于2.8。位于金属化结构内的金属线可由铜或铜合金所构成。接触区12为顶层金属化层，形成于顶层内层介电层内，其为布线的一部分且若有需要，其具有经过平坦化工艺(例如，化学机械研磨(chemical mechanical polishing，CMP))处理过的露出表面。用于接触区12的材料可包括但布局限于铜(Cu)、铝(Al)、AlCu、铜合金或其他可动式(mobile)导电材料。在一实施例中，接触区12为金属垫区，其可用于接合工艺中，以将各个芯片内的集成电路连接至外部特征部件。
图1也示出在基底10上形成一保护(passivation)层14，其具有一第一开口15而露出一部分的金属垫区，以便于后续凸块制作。在一实施例中，保护层14由非有机材料所构成，其择自于未掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅或其组合。在另一实施例中，保护层14由高分子材料所构成，例如环氧化物、聚亚酰胺(polyimide)、苯环丁烯(benzocyclobutene，BCB)、聚苯恶唑(polybenzoxazole，PBO)等等。另外，也可使用其他相对软性且通常为有机的介电材料。在一实施例中，保护层14具有双层结构，包括一介电层及一高分子层。
图1也示出在基底10形成一封胶(encapsulating)层16，以覆盖保护层14并填入第一开口15。封盖层16由非导电材料所构成，避免相邻的连接线彼此发生短路。封盖层16也保护基底10免受水气、离子污染、辐射或不利的操作环境(如，热力及机械力作用、冲击或震动环境)影响。在一实施例中，封盖层16由底胶(underfill)材料所构成，其包括酐类固化(anhydride-cured)或胺类固化(amine-cured)环氧化物材料、环氧化物高分子、硅酸盐类(silsesquioxane-based)环氧树脂等等。底胶材料呈现高度的毛细流动(capillary flow)，以便于底胶材料在基底的形成结构上的渗透。底胶材料也有助于应力吸收，其起因于热膨胀不匹配，其存在于集成电路基底与封装基底之间。在一实施例中，封盖层16由介电材料所构成，其可包括SiO2、SiOxNy、Si3N4或介电常数低于3.9的介电材料。
接着，在封盖层16上形成一掩模层18。在一些实施例中，掩模层18可为干膜或光致刻蚀剂层，其历经涂布、烘烤、除渣(descum)等步骤，接着进行光刻及/或蚀刻工艺，例如干蚀刻及/或湿蚀刻。利用图案化的掩模层18与光刻及/或蚀刻工艺，在封盖层16内形成一第二开口20而露出金属垫区12的一部分12a，如图2所示。在一些实施例中，第二开口20的直径大于或等于第一开口15的直径。取决于工艺控制，在至少一实施例中，第二开口20可露出一部分的保护层14，其邻近于金属垫区12的露出部分12a。
接着，请参照图3，自封盖层16上去除掩模层18。在掩模层18为干膜的情形中，可通过碱性溶液去除掩模层18。若掩模层18由光致刻蚀剂所构成，可利用丙酮、n-甲基比咯酮(n-methyl pyrrolidone，NMP)、二甲基亚砜(dimethyl sulfoxide，DMSO)、胺基乙氧基乙醇(aminoethoxy ethanol)等等。
请参照图4，在封盖层16的第二开口20内进行底层凸块金属化(UBM)层22的制作。UBM层22通过无电沉积(electroless deposition)或浸渍(immersion)技术而选择性形成于封盖层16的第二开口20内金属垫区12的露出部分12a上。在保护层14露出于第二开口20的情形中，UBM层22可形成于第二开口20内保护层14的露出部分上。在一实施例中，UBM层22包括一扩散阻障层，其由钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、钽(Ta)等等所构成，且其厚度约在500至2000埃
Figure BSA00000248572900061
的范围。在一实施例中，UBM层22包括厚度约在3000至5000埃的范围的一铜层，然而，其厚度可增加或减少。举例来说，铜层的厚度约在1至10微米(μm)的范围。
接着在UBM层22上进行凸块层24的制作，以填入第二开口20。凸块层24为具有焊料润湿性(solder wettability)的导电材料，其可通过适当的技术来制作，包括：物理气相沉积(physical vapor deposition，PVD)、化学气相沉积(chemical vapor deposition，CVD)、电化学沉积(electrochemicaldeposition，ECD)、分子束外延(mplecular beam epitaxy，MBE)、原子层沉积(atomic layer deposition，ALD)、电镀等等。需注意的是在一些实施例中，例如在基底10的整个表面沉积一顺应性(conformal)层的技术中(例如，PVD及CVD)，可能需进行蚀刻或平坦化工艺(例如，化学机械研磨(CMP))，以去除封盖层16的表面上多余的导电材料。凸块层24的厚度大于40微米。举例来说，凸块层24的厚度约在40至50微米范围，或约在40至70微米范围，然而，其厚度可增加或减少。
在一些实施例中，凸块层24为焊料层且由Sn、SnAg、Sn-Pb、SnAgCu(Cu的重量百分比小于0.3％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等等所构成。在热退火期间，焊料体积不会改变。在一些实施例中，凸块层24为金属层且由任何适当的导电材料所构成，包括Cu、Ni、Pt、Al或其组合等等。举例来说，铜(Cu)层所指的是实质上包括一膜层，其包括纯元素铜、含有不可避免杂质的铜、及铜合金(其含有少量的元素，例如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆)。在一些实施例中，可进行电化学电镀(electro-chemical plating，ECP)以形成铜层。
在一实施例中，凸块层24还包括一选择性上盖层，其可作为阻障层而防止凸块层24内的铜扩散进入接合材料，以增加封装的可靠度及接合强度。上盖层可由铜、镍(Ni)、金(Au)、银(Ag)、钯(Pd)、铟(In)、镍-钯-金(NiPdAu)、镍-金(NiAu)、其他相似材料或合金。上盖层可为多层结构或单层结构，厚度约在1至5微米的范围。如图4A所示，第一上盖层26a形成于凸块层24与UBM层22之间。此处，凸块层24为焊料层，第一上盖层26a包括铜层、镍层或其组合。如图4B所示，第二上盖层26b形成于凸块层24的上表面。此处，在凸块层24为铜层且厚度约在40至50微米的范围。第二上盖层26b包括镍层、锡层或其组合。如图4C所示，第三上盖层26c夹设于凸块层24的第一部24a与凸块层24的第二部24b之间。此处，第一部24a为厚度约在40至50微米范围的铜层，而第二部24b厚度约在5至10微米范围的焊料层且第三上盖层26c包括镍层、金层或其组合。
请参照图5，进行回蚀刻工艺(例如，干蚀刻工艺)或平坦化工艺(例如，化学机械研磨(CMP)工艺)28以去除封盖层16的上表面上多余的导电材料，直至凸块层24的上表面大体上与封盖层16的上表面共平面。
为了容许后续与封装基底上的预焊接(pre-solder)层直接接合，通过另一回蚀刻工艺或平坦化工艺30对封盖层16的上表面再进行蚀刻，直至凸块层24的顶部24p突出于封盖层16，如图6所示。突出于封盖层16上表面的顶部24p具有厚度T1，且凸块层24具有厚度T2，其中T1/T2的比率约在0至0.98的范围。在一实施例中，进行一缓冲工艺以轻微研磨基底10，使封盖层16的厚度达到最终目标厚度。其利用软研磨垫进行一预定研磨时间，以避免高速及低速研磨所造成的缺陷及刮伤。
完成的凸块结构32包括埋入于封盖层16内的UBM层22以及局部埋入于封盖层16内的凸块层24。凸块层24的顶部略为突出于封盖层16，其可在后续封装工艺中直接接合于预焊接层。取决于凸块层24的材料，可对凸块层24选择性进行一焊料回流(solder reflow)工艺。接着进行基底10切割及利用将焊球或铜凸块设置于一封装基底或另一芯片的接合垫上，而将基底10封装至一封装基底或另一芯片上。
相较于公知凸块工艺，本发明是在保护层14上形成具有第二开口20的封盖层16、在封盖层16的第二开口20内选择性形成UBM层22，接着在封盖层16的第二开口20内凸块层24，进而形成具有强化凸块强度及可靠度的坚固凸块结构32。其无需进行UBM蚀刻工艺，因此可避免UBM底切问题。同样地，由于封盖层16取代公知光致刻蚀剂掩模层，因此在形成凸块之后，无需再进行去除封盖层16的步骤。此降低凸块架桥问题而可实施于微间距凸块及结构或高凸块密度的设计。另外，凸块层24的顶部24p突出于封盖层16，其可直接与封装基底的预焊接层直接连接。
图7至图9示出根据一实施例的凸块结构的制造方法中各个阶段的剖面示意图，同时此处省略说明相同或相似于图1至图6中说明解释部分。
请参照图7，在形成具有第二开口20的封盖层16之后，在封盖层16的第二开口20内形成UBM层22a，以与金属垫区12接触。UBM层22a可通过适当的技术来制作，包括：物理气相沉积(PVD)、化学气相沉积(CVD)、电化学沉积(ECD)、原子层沉积(ALD)、电镀等等，例如在基底10的整个表面沉积一顺应性层。UBM层22a顺着第二开口20的底部及侧壁且延伸至封盖层16的上表面。
在UBM层22a上形成凸块层24，以填入第二开口20。凸块层24为具有焊料润湿性的导电材料，其可通过适当的技术来制作，包括：PVD、CVD、ECD、MBE、ALD、电镀等等。在一些实施例中，凸块层24为焊料层，且由Sn、SnAg、Sn-Pb、SnAgCu(Cu的重量百分比小于0.3％)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等等所构成。在一些实施例中，凸块层24为金属层且由任何适当的导电材料所构成，包括Cu、Ni、Pt、Al或其组合等等。在一实施例中，凸块层24还包括一选择性上盖层，其可作为阻障层而防止凸块层24内的铜扩散进入接合材料，以增加封装的可靠度及接合强度。
请参照图8，进行回蚀刻工艺(例如，干蚀刻工艺)或平坦化工艺(例如，化学机械研磨(CMP)工艺)28以去除封盖层16的上表面上多余的导电材料，直至凸块层24与UBM层22a的上表面大体上与封盖层16的上表面共平面。
为了容许后续与封装基底上的预焊接层直接接合，通过另一回蚀刻工艺或平坦化工艺30对封盖层16的上表面再进行蚀刻，直至凸块层24与UBM层22a的上表面突出于封盖层16，如图9所示。在一实施例中，进行一缓冲工艺以轻微研磨基底10，使封盖层16的厚度达到最终目标厚度。其利用软研磨垫进行一预定研磨时间，以避免高速及低速研磨所造成的缺陷及刮伤。
完成的凸块结构32a包括：局部埋入于封盖层16内，且具有顶部24p突出于封盖层16的凸块层24；以及局部埋入于封盖层16内，顺着凸块层24底部及侧壁，且具有顶部22p突出于封盖层16的UBM层22a。凸块结构32a的顶部24p及22p略为突出于封盖层16，其可在后续封装工艺中直接接合于预焊接层。
在以上的详细说明中，本发明已以特定实施例揭示如上。然而，在不脱离本发明的精神和范围内，当可作不同的更动、建造、制作、替代，如提出的保护范围所述。因此，本说明书及附图供作举例说明之用而并非用以限定本发明。可以理解的是本发明能够使用于不同的其他组合与环境，且能够在本发明的概念范围内，作替代及更动。

Claims (10)

1.一种半导体装置的制造方法，包括：
在具有一金属垫区的一半导体基底上方形成一封盖层，其中该封盖层具有一开口露出一部分的该金属垫区；
在该露出的金属垫区部分上方的该封盖层的该开口内形成一凸块下金属层；
在该凸块下金属层上方形成一凸块层，以填入该封盖层的该开口且延伸至该封盖层的上表面；以及
自该封盖层的该上表面去除该凸块层。
2.如权利要求1所述的半导体装置的制造方法，还包括去除该封盖层的该上表面，直至该凸块层的一顶部突出于该封盖层。
3.如权利要求1所述的半导体装置的制造方法，其中该封盖层由底胶材料或是介电材料所构成。
4.如权利要求1所述的半导体装置的制造方法，其中该凸块层包括一焊料层。
5.如权利要求1所述的半导体装置的制造方法，其中该凸块层包括一铜层，该铜层的厚度大于40微米。
6.如权利要求1所述的半导体装置的制造方法，其中该底层凸块金属化层包括：一钛层、一铜层或其组合。
7.如权利要求1所述的半导体装置的制造方法，其中该凸块下金属层顺着该封盖层的该开口的底部及侧壁且延伸至该封盖层的上表面，且形成该凸块层之后，还包括自该封盖层的该上表面去除该凸块下金属层。
8.一种半导体装置，包括：
一半导体基底，包括一金属垫区；
一封盖层，位于该半导体基底上方，且未覆盖该金属垫区的一第一部分；
一凸块层，局部形成于该封盖层内且电性连接至该金属垫区的该第一部分，其中该凸块层的一顶部突出于该封盖层的上表面；以及
一凸块下金属层，形成于该封盖层内且电性连接至该金属垫区的该第一部分，其中该凸块下金属层形成于该凸块层与该金属垫区的该第一部分之间。
9.如权利要求8所述的半导体装置，其中该凸块下金属层形成于该凸块层与该封盖层之间，且该凸块下金属层包括一顶部突出于该封盖层。
10.如权利要求8所述的半导体装置，其中该封盖层由底胶材料或是介电材料所构成，其中该凸块层包括一焊料层或厚度大于40微米的一铜层。
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