CN102194519A - Memory - Google Patents
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- CN102194519A CN102194519A CN2010101258845A CN201010125884A CN102194519A CN 102194519 A CN102194519 A CN 102194519A CN 2010101258845 A CN2010101258845 A CN 2010101258845A CN 201010125884 A CN201010125884 A CN 201010125884A CN 102194519 A CN102194519 A CN 102194519A
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- 238000012797 qualification Methods 0.000 description 1
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Abstract
The invention provides a memory. The memory comprises a plurality of memory regions, a voltage source, a voltage dividing unit and a precoding unit, wherein the voltage source is used for providing the read reference voltage to the memory regions; the voltage dividing unit comprises a plurality of memory region voltage dividing units corresponding to the memory regions; the precoding unit is connected with the voltage dividing unit and is used for selecting the corresponding memory region voltage dividing units according to the address signals input into the precoding unit; and the selected memory region voltage dividing units are used for outputting the divided read reference voltage as the read voltage provided to the corresponding memory regions after dividing the read reference voltage provided by the voltage source. The memory has the following advantages: the power consumption of the memory is reduced and the reading time of the memory can be optimized; and besides, crosstalk between the adjacent memory regions can be avoided from being easily caused when data of some memory regions are read for a long time.
Description
Technical field
The present invention relates to memory area, relate in particular to flash memory.
Background technology
In recent years, along with developing rapidly of semiconductor memory, advanced storeies such as DRAM, EEPROM, flash memory widely use owing to have the advantage of high density, low-power consumption and low price.
Fig. 1 is the structural representation of the storer of existing demonstration read method, and with reference to figure 1, existing memory comprises several storage arrays 103, is respectively storage array 1, storage array 2 ... storage array n; Line decoder 102 is connected with described some storage arrays 101; Voltage source 101, in the prior art, voltage source is generally voltage regulator (Regulator), be connected with described line decoder 102, during the data of in reading storer, storing, voltage source 101 provides to the storage array of correspondence by described line decoder 102 and reads voltage, realizes the data read to corresponding storage array.
The storer of the prior art, provide the identical voltage that reads to all storage arrays, yet, the storage unit (Cell) of different storage arrays (Array) to read characteristic inequality, the actual required size that reads voltage is also inequality, in order to realize data read to all storage arrays, need provide higher and read voltage to satisfy the requirement of reading voltage of all storage arrays, can cause the power consumption of storer big like this, reading speed is slow; In addition, a certain storage array is applied read the voltage ratio actual needs read voltage when high, when for a long time this storage array being carried out reading of data, cause easily and adjacent storage array between crosstalk phenomenon.
In addition, when the different situation of the array structure of different storage array correspondences, the number of corresponding line decoder can be different, thereby can need the line decoder driver of different size, and this will cause the storer difficult wiring; If measure-alike being beneficial to of all line decoder drivers connected up, will cause reading speed slack-off, and power consumption is big.
That application number is that 03100073.8 Chinese patent application discloses is a kind of " can reduce operating voltage memory element read circuit ", yet, do not solve the shortcoming of above-described prior art.
Summary of the invention
The present invention solves be the storer of prior art power consumption is big when reading, reading speed is slow and adjacent storage array between the phenomenon that can crosstalk.
Another problem that the present invention solves is the problem of storer difficult wiring when the line decoder driver size is identical, if perhaps line decoder driver size difference, time for reading that can not optimize storage and speed, the problem that power consumption is big.
For solving above technical matters, the invention provides a kind of storer, it comprises several storage areas; Voltage source provides to described storage area and to read reference voltage; Also comprise:
Partial pressure unit comprises that several are respectively corresponding to the storage area partial pressure unit of described several storage areas;
The pre-decode unit, be connected with described partial pressure unit, address signal according to this pre-decode unit of input, select corresponding storage area partial pressure unit, selecteed storage area partial pressure unit reads voltage output with reading after the reference voltage dividing potential drop of providing of described voltage source as what offer respective memory regions.
Optionally, described partial pressure unit also comprises voltage output end, and the described voltage that reads is by described voltage output end output.
Optionally, described storer comprises several storage arrays, and each storage array is a storage area.
Optionally, described storer comprises several storage arrays, and each storage array comprises some sectors respectively, and wherein, each sector of each storage array is a storage area.
Optionally, described storer comprises some storage arrays, and each storage array comprises some sectors respectively, and each sector comprises some pages or leaves respectively, and wherein, each page or leaf of each sector of each storage array is a storage area.
Optionally, described storage area partial pressure unit comprises: resistance, MOS transistor, control module;
Wherein, described resistance is parallel to the grid and the source electrode of described MOS transistor, and the drain electrode of MOS transistor is connected with described voltage output end, and the source electrode of described MOS transistor is connected with the output terminal of described voltage source;
Described control module is connected with the grid of described MOS transistor, is used for controlling when described storage area partial pressure unit is selected the unlatching of this MOS transistor.
Optionally, described voltage source is a voltage regulator.
Optionally, the described reference voltage that reads is 0.1～0.5V with the voltage difference scope that reads voltage.
Compared with prior art, the present invention has the following advantages:
During data in reading storage area, the storage area partial pressure unit with voltage source provide read the reference voltage dividing potential drop after offer corresponding storage area as reading voltage, the corresponding storage area partial pressure unit of each storage area, can be according to the characteristic that reads of the storage unit of different storage areas, the voltage that different storage areas is provided voltage source is after dividing potential drop respectively, offer different storage areas, can the voltage that read of each storage area be optimized respectively like this, thereby reduce the power consumption of storer, and time for reading that can optimize storage; In addition, can avoid to some storage area apply read the voltage ratio actual needs read the voltage height, when for a long time some storage area being carried out reading of data, cause easily and adjacent storage area between crosstalk phenomenon.
And, for storer is connected up easily, line decoder driver measure-alike, by the storage area partial pressure unit, with voltage source provide read the reference voltage dividing potential drop after, offer different storage areas, can the time for reading and the speed of different storage zone be optimized respectively, when solution line decoder driver size is identical, can't be to the time for reading of storer and the problem that speed is optimized and power consumption is big.
Description of drawings
Fig. 1 is the structural representation of existing memory;
Fig. 2 is the structural representation of the storer of the specific embodiment of the invention;
Fig. 3 is the electrical block diagram of the storage area partial pressure unit of the specific embodiment of the invention.
Embodiment
The storer of prior art, provide the identical voltage that reads to all storage arrays, yet, the storage unit (Cell) of different storage arrays (Array) to read characteristic inequality, the actual required size that reads voltage is also inequality, in order to realize data read to all storage arrays, need provide higher and read voltage to satisfy the requirement of reading voltage of all storage arrays, can cause the power consumption of storer big like this, reading speed is slow; The storer of the specific embodiment of the invention, the storage area partial pressure unit with voltage source provide read the reference voltage dividing potential drop after offer corresponding storage area as reading voltage, the corresponding storage area partial pressure unit of each storage area, can be according to the characteristic that reads of the storage unit of different storage areas, respectively to the different voltage that voltage source is provided after dividing potential drop, offer different storage areas, can the voltage that read of each storage area be optimized respectively like this, thereby reduce the power consumption of storer, and time for reading that can optimize storage.In addition, the storer of prior art, a certain storage area is applied read the voltage ratio actual needs read voltage when high, when for a long time this storage area being carried out reading of data, cause easily and adjacent storage area between crosstalk phenomenon; The storer of the specific embodiment of the invention, the characteristic that reads according to the storage unit of different storage zone, can provide the different voltage that reads to different storage areas respectively, when avoiding reading for a long time the data in the storage area and the crosstalk phenomenon between the adjacent storage area.
And, the storer of prior art, if the line decoder driver is measure-alike, then can make the time for reading of storer slack-off, if the size difference of line decoder driver, storer are not easy wiring, storer of the present invention, even the line decoder driver is measure-alike, by the storage area partial pressure unit; With reading after the reference voltage dividing potential drop that voltage source provides as reading voltage, offer different storage areas, can the time for reading of different storage zone be optimized respectively, when avoiding the line decoder driver size identical, the shortcoming that can't be optimized to the time for reading of storer, storer had both been connected up easily, can improve time for reading, the reduction power consumption of storer again.
In order to make those skilled in the art better understand essence of the present invention, specific embodiments of the invention are described in detail below in conjunction with accompanying drawing.
Fig. 2 is the structural representation of the storer of the specific embodiment of the invention, with reference to figure 2, storer of the present invention, comprise several storage areas 201, be respectively storage area 1, storage area 2 ... storage area n, wherein, the quantity of storage area is determined according to the actual needs, is not done qualification at this; Voltage source 202 is used to provide and reads reference voltage, and in specific embodiments of the invention, described voltage source 202 is a voltage regulator; Partial pressure unit 204, its input end is connected with the output terminal of described voltage source, this partial pressure unit 204 comprises that voltage output end Vout and several are respectively corresponding to the storage area partial pressure unit of described storage area, be respectively storage area partial pressure unit 1, storage area partial pressure unit 2 ... storage area partial pressure unit n, the quantity of storage area partial pressure unit and the quantity of storage area equate; Pre-decode unit 205, be connected with described partial pressure unit 204, according to the address signal (promptly will carry out the address of the storage area of read operation) of importing it, select corresponding storage area partial pressure unit, described selecteed storage area partial pressure unit reads voltage output with reading after the reference voltage dividing potential drop of providing of described voltage source 202 as what offer corresponding storage area, in specific embodiments of the invention, the described voltage that reads can be by described voltage output end Vout output.In this embodiment of the present invention, storer also comprises line decoder 203, its input end is connected with the voltage output end Vout of described partial pressure unit 204, output terminal is connected with described several storage areas 201, be used for described several storage areas 201 are carried out addressing, select corresponding storage area to read, for example, when 205 selection storage area partial pressure unit 1 are carried out dividing potential drop in described pre-decode unit, line decoder 203 is selected storage area 1, the voltage that reads of storage area partial pressure unit 1 output is exported to storage area 1 through line decoder 203, realizes the data read to storage area 1.
In other embodiments, the voltage output end Vout of partial pressure unit 204 output reads voltage (by selecteed storage area partial pressure unit output) and also can directly offer corresponding storage area without line decoder 203.In addition, the voltage that reads of each storage area partial pressure unit output of partial pressure unit 204 also can obstructed superpotential output end vo ut and directly offer corresponding storage area, for example, the output terminal of each storage area partial pressure unit is connected with the input end of corresponding storage area respectively
Fig. 3 is the electrical block diagram of the storage area partial pressure unit of the specific embodiment of the invention, Fig. 3 is to be example (having omitted line decoder 203 among the figure) with storage area partial pressure unit 1 and storage area 1, and the circuit structure of other storage area partial pressure unit and corresponding storage area is identical with the circuit structure of storage area partial pressure unit 1 and storage area 1.
With reference to figure 3, storage area partial pressure unit 1 comprises resistance R 1, MOS transistor 301, control module 302; Wherein, resistance R 1 is parallel to the grid and the source electrode of described MOS transistor 301, the drain electrode of MOS transistor 301 is connected with described voltage output end Vout, provides to storage area 1 and reads voltage, and the source electrode of described MOS transistor 301 is connected with the output terminal of described voltage source 202; Described control module 302 is connected with the grid of described MOS transistor 301, be used for when described storage area partial pressure unit 1 is selected, controlling the unlatching (conducting) of this MOS transistor 301, this control module 302 is added in the size of the voltage on the grid of described MOS transistor 301 by adjustment, control the unlatching of this MOS transistor 301; Described pre-decode unit 205 is connected with this control module 302,205 when selecting storage area partial pressure unit 1 in the pre-decode unit, control module 302 is adjusted the voltage that is added on MOS transistor 301 grids, makes MOS transistor 301 open (conducting), provides to described storage area 1 and reads voltage.The voltage V that voltage source 202 provides, through resistance R 1 and MOS transistor 301 voltage after partial is that V-Vr-Vt exports to storage area 1, Vr represents the voltage difference of resistance R 1 input end and output terminal, Vt represents the threshold voltage of MOS transistor 301, therefore the voltage of the drain electrode of MOS transistor output is V-Vr-Vt, the threshold voltage vt sum of the dividing potential drop Vr of resistance R 1 and MOS transistor is the input end of the regional partial pressure unit 1 of storage and the voltage difference of output terminal, can regulate the size of storage area partial pressure unit dividing potential drop by the size of adjusting resistance R 1.
In the practical application, resistance R 1 is designed to adjustable resistance, after the storer manufacturing is finished, can test storer: by adjusting the resistance of first resistance R 1, read operation to storage area is verified, can determine to be fit to the voltage that reads of described storage area 1, thereby determine the voltage difference of storage area partial pressure unit input end and output terminal.Usually the difference scope of the voltage of the voltage of storage area partial pressure unit input end (input read reference voltage) and output terminal (output read voltage) is 0.1V～0.5V, and the scope of the voltage difference of each storage area partial pressure unit input end and output terminal can be the same or different.
In a specific embodiment of the present invention, described storer comprises some storage arrays, be respectively storage array 1, storage array 2 ... storage array n, wherein, each storage array is a storage area, storage array 1 corresponding stored zone 1, storage array 2 corresponding stored zones 2, and the like, described storage area partial pressure unit 1 provides to storage array 1 and reads voltage, storage area partial pressure unit 2 provides to storage array 2 and reads voltage, and the like.In one example, storer comprises two storage arrays, is respectively data storage array and code storage array, and then the quantity of storage array is two, and storage array 1 is a data storage array, and storage array 2 is the code storage array.
In other embodiments of the invention, described storer comprises some storage arrays, each storage array comprises some sectors (Section) respectively, be respectively sector 1, sector 2 ... sector n, wherein, each sector of each storage array is a storage area, 1 corresponding stored zone 1, sector, 2 corresponding stored zones 2, sector, and the like, described storage area partial pressure unit 1 provides program/erase voltage to sector 1, and storage area partial pressure unit 2 provides program/erase voltage to sector 2, and the like.
Spirit of the present invention also can be generalized to littler storage area, for example, described storer comprises some storage arrays, each storage array comprises some sectors respectively, each sector comprises some pages or leaves (Bank) respectively, be respectively page or leaf 1, page or leaf 2 ... page or leaf n, wherein, each page or leaf of each sector of each storage array is a storage area, page or leaf 1 corresponding stored zone 1, page or leaf 2 corresponding stored zones 2, and the like, described storage area partial pressure unit 1 provides program/erase voltage to page or leaf 1, and storage area partial pressure unit 2 provides program/erase voltage to page or leaf 2, and the like.
The above only is specific embodiments of the invention; in order to make those skilled in the art better understand spirit of the present invention; yet protection scope of the present invention is not a limited range with the specific descriptions of this specific embodiment; any those skilled in the art is in the scope that does not break away from spirit of the present invention; can make an amendment specific embodiments of the invention, and not break away from protection scope of the present invention.
Claims (8)
1. storer, it comprises several storage areas; Voltage source provides to described storage area and to read reference voltage; It is characterized in that, also comprise:
Partial pressure unit comprises that several are respectively corresponding to the storage area partial pressure unit of described several storage areas;
The pre-decode unit, be connected with described partial pressure unit, address signal according to this pre-decode unit of input, select corresponding storage area partial pressure unit, described selecteed storage area partial pressure unit reads voltage output with reading after the reference voltage dividing potential drop of providing of described voltage source as what offer respective memory regions.
2. storer as claimed in claim 1 is characterized in that described partial pressure unit also comprises voltage output end, and the described voltage that reads is by described voltage output end output.
3. storer as claimed in claim 1 is characterized in that described storer comprises several storage arrays, and each storage array is a storage area.
4. storer as claimed in claim 1 is characterized in that described storer comprises several storage arrays, and each storage array comprises some sectors respectively, and wherein, each sector of each storage array is a storage area.
5. storer as claimed in claim is characterized in that, described storer comprises some storage arrays, each storage array comprises some sectors respectively, each sector comprises some pages or leaves respectively, and wherein, each page or leaf of each sector of each storage array is a storage area.
6. storer as claimed in claim 1 is characterized in that, described storage area partial pressure unit comprises: resistance, MOS transistor, control module;
Wherein, described resistance is parallel to the grid and the source electrode of described MOS transistor, and the drain electrode of MOS transistor is connected with described voltage output end, and the source electrode of described MOS transistor is connected with the output terminal of described voltage source;
Described control module is connected with the grid of described MOS transistor, is used for controlling when described storage area partial pressure unit is selected the unlatching of this MOS transistor.
7. as each described storer of claim 1～6, it is characterized in that described voltage source is that voltage is transferred device.
8. storer as claimed in claim 1 is characterized in that, the described reference voltage that reads is 0.1～0.5V with the voltage difference scope that reads voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010125884.5A CN102194519B (en) | 2010-03-08 | 2010-03-08 | Memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010125884.5A CN102194519B (en) | 2010-03-08 | 2010-03-08 | Memory |
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| CN102194519A true CN102194519A (en) | 2011-09-21 |
| CN102194519B CN102194519B (en) | 2015-06-17 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030147287A1 (en) * | 2002-02-02 | 2003-08-07 | Samsung Electronics, Co., Ltd. | Nonvolatile semiconductor memory with power-up read mode |
| US20050099874A1 (en) * | 2003-11-06 | 2005-05-12 | Susumu Shuto | Semiconductor integrated circuit device |
| CN1828764A (en) * | 2004-12-03 | 2006-09-06 | 旺宏电子股份有限公司 | Memory array with low power pre-charged bit lines |
| CN101027729A (en) * | 2004-07-29 | 2007-08-29 | 斯班逊有限公司 | Method for initializing non-volatile storage device, and non-volatile storage device |
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2010
- 2010-03-08 CN CN201010125884.5A patent/CN102194519B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030147287A1 (en) * | 2002-02-02 | 2003-08-07 | Samsung Electronics, Co., Ltd. | Nonvolatile semiconductor memory with power-up read mode |
| US20050099874A1 (en) * | 2003-11-06 | 2005-05-12 | Susumu Shuto | Semiconductor integrated circuit device |
| CN101027729A (en) * | 2004-07-29 | 2007-08-29 | 斯班逊有限公司 | Method for initializing non-volatile storage device, and non-volatile storage device |
| CN1828764A (en) * | 2004-12-03 | 2006-09-06 | 旺宏电子股份有限公司 | Memory array with low power pre-charged bit lines |
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| CN102194519B (en) | 2015-06-17 |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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