CN100492543C - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
- Publication number
- CN100492543C CN100492543C CNB200480005107XA CN200480005107A CN100492543C CN 100492543 C CN100492543 C CN 100492543C CN B200480005107X A CNB200480005107X A CN B200480005107XA CN 200480005107 A CN200480005107 A CN 200480005107A CN 100492543 C CN100492543 C CN 100492543C
- Authority
- CN
- China
- Prior art keywords
- bit line
- voltage
- semiconductor storage
- circuit
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000015654 memory Effects 0.000 claims abstract description 74
- 230000014509 gene expression Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004576 sand Substances 0.000 description 3
- 101100421142 Mus musculus Selenon gene Proteins 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 208000012839 conversion disease Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009452 underexpressoin Effects 0.000 description 1
Images
Landscapes
- Read Only Memory (AREA)
Abstract
A semiconductor storage device includes: a plurality of memory array cells (hereinafter, referred to as cells); a circuit arranged in each of the cells for precharge of each bit line of the cells to a predetermined voltage; and a circuit for comparing, for each bit line, an output voltage of each bit line of the cells selected for reading out data to an output voltage of each bit line of cells selected for reference. When the data is read out, the voltage value for precharge of the bit line of the cells selected for reading out data and the voltage value for precharge of the bit line of the cells selected for reference are temporarily set to different values. Thus, all the output bits of the cells selected for reading out data can be read out by a single read out operation.
Description
Technical field
The present invention relates to the invention of semiconductor storage.Particularly relate to the invention of reading of the Nonvolatile semiconductor memory device of flash memory (flash) or EEPROM etc.
Background technology
As existing Nonvolatile semiconductor memory device, be that example describes with the flash memories at this.Expression general flash memories summary configuration example in the past in Fig. 5.
In this configuration example, the memory array cell 51 that is made of a plurality of flash memories sends to multichannel recombiner (multi plexer) 52 with the output of 1024 bit line.The sensor amplifier 53 of outgoing side that is connected multichannel recombiner 52 is according to the ratio setting to 1 of 128 bit line.Therefore, on the outgoing side of multichannel recombiner 52, connect 8 sensor amplifiers 53.In addition, the reference unit 54 that on the reversed input terminal of each sensor amplifier 53, connects the output reference current.Also have, sensor amplifier 53 is current/voltage switching amplifiers.
Flash memories in the past has a plurality of circuit modules, and it constitutes (in Fig. 5, only having represented two circuit modules) by the above-mentioned memory array cell that constitutes 51, multichannel recombiner 52, sensor amplifier 53 and reference unit 54.
Reading in the action of the existing flash memories shown in Fig. 5, select a memory array cell of reading from a plurality of memory array cells, selecteed memory array cell Jie sends to the multichannel recombiner by 1024 bit line with the data of storing.The data that multichannel recombiner 52 will send from memory array cell output to each sensor amplifier 53 in turn.And each sensor amplifier 53 carries out exporting the voltage to the difference that should compare from the reference current of reference unit 54 outputs with from the comparison between the electric current of multichannel recombiner output.
The flash memories of Fig. 5 is the formation that a memory array cell is provided with 8 sensor amplifiers, owing to carry out the above-mentioned the sort of action of reading, therefore can only read 8 data in the action reading once.
Though by increasing the number of the sensor amplifier that a memory array cell is provided with, can be increased in and once read the data bits of reading in the action, but because the increase of the circuit area of the sensor amplifier of current/voltage conversion hysteria is therefore worthless from the angle of miniaturization.Thus, the number of the sensor amplifier that can be provided with a memory array cell is the upper limit with 16.Therefore, in existing flash memories once to read in the action to read 8～16 data be limit.Be that existing flash memories reading speed is slow.
Summary of the invention
The objective of the invention is to address the above problem, provide reading speed fast semiconductor storage.
In order to achieve the above object, in relevant semiconductor storage of the present invention, possess: a plurality of the 1st bit lines; A plurality of 2nd bit lines corresponding respectively with described a plurality of the 1st bit lines; A plurality of memory cells, it is provided with respectively each described the 1st bit line, is connected respectively with described the 1st bit line; Pre-charge circuit, it carries out precharge to described memory cell; With reference to using potential circuit, it provides with reference to using voltage to described the 2nd bit line; Comparator circuit, it is provided with respectively each described the 1st bit line, the output voltage of each described the 1st bit line and the reference of each described the 2nd bit line of correspondence is compared respectively with voltage, synchronously to read the data of being stored in described a plurality of memory cell.
According to this formation, by read operation once can read be used for sense data and selecteed main array element all output figure places (for example 1024).Thus, relevant semiconductor storage of the present invention and is only carried out 8～16 the semiconductor storage of reading in the past and is compared by 1 time the action of reading, and can leap the raising reading speed.
Description of drawings:
Fig. 1 represents the figure of the summary configuration example of relevant nonvolatile memory of the present invention.
The sequential chart of the each several part signal waveform of the nonvolatile memory of Fig. 2 presentation graphs 1.
The figure of the configuration example of the sensor amplifier that nonvolatile memory possessed of Fig. 3 presentation graphs 1.
The figure of another configuration example of the sensor amplifier that nonvolatile memory possessed of Fig. 4 presentation graphs 1.
Fig. 5 is the figure of the summary configuration example of the existing flash memories of expression.
Embodiment
With reference to the accompanying drawings one embodiment of the present invention is described.As relevant semiconductor storage of the present invention, be that example describes at this nonvolatile memory with flash memory or EEPROM etc.The summary configuration example of nonvolatile memory in Fig. 1 under expression and the identical storage size situation of relevant existing flash memories of the present invention.
To exist the memory array cell of memory array cell planted agent sense data to be called main array element.Main array element 2 possesses 1024 non-volatile memory cells 3.And each bit line of main array element 2 is connected on each output terminal of pre-charge circuit 1.Be that pre-charge circuit 1 has 1024 output terminals.In addition, each bit line Jie of main array element 2 is connected on non-inverting input of sensor amplifier 21 by P channel-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 4.
Equally the memory array cell 12 as the comparison other of main array element 2 possesses 1024 non-volatile storage unit 13.And each bit line of memory array cell 12 is connected on each output terminal of pre-charge circuit 11.Be that pre-charge circuit 11 has 1024 output terminals.In addition, each bit line Jie with cells of memory arrays 12 is connected on the reversed input terminal of sensor amplifier 21 by P channel-type MOSFET14.
And, input precharging signal Φ on pre-charge circuit 1
pAnd 1V precharging signal PR
s, input precharging signal Φ on pre-charge circuit 11
pAnd 1V precharging signal PR
DIn addition, difference input select signal SELn (n is the integer of 1 ≦ n ≦ 1024) on the grid of P channel-type MOSFET4 and 14.And import word-line signal WL simultaneously on the controller grid of each storage unit 3 in main array element 2
s, import word-line signal WL simultaneously on the control grid of each storage unit 13 in memory array cell 12
DThe action control signal SEN of switching controls that will carry out the action/non-action of sensor amplifier 21 in addition is input in each sensor amplifier 21 simultaneously.
Also have, sensor amplifier 21 is voltage amplifiers of exporting the voltage signal of the difference of amplifying two input voltages.Therefore, sensor amplifier 21 is compared with the current/voltage switching amplifier that is adopted in existing flash memories and can be reduced circuit area.In addition, though in Fig. 1, illustrate simply in order to make, only illustrate a circuit that constitutes by the above-mentioned pre-charge circuit that constitutes 1, main array element 2, P channel-type MOSFET4, pre-charge circuit 11, memory array cell 12, P channel-type MOSFET14 and sensor amplifier 21 (below, be called basic circuit), but in fact relevant nonvolatile memory of the present invention has a plurality of above-mentioned basic circuits, selects 1 basic circuit by selection signal SELn from these a plurality of basic circuits.In addition, also can the sensor amplifier of a plurality of basic circuits is identical, the mode that becomes n or m (m is the natural number of m ≦ n) according to the sensor amplifier with nonvolatile memory integral body is carried out.In this case, connect a plurality of P channel-type MOSFET on the input terminal of each sensor amplifier, these a plurality of P channel-type MOSFET are as multichannel recombiner performance function.
Then, the sequential chart explanation that sees figures.1.and.2 is in the action of reading of the relevant nonvolatile memory of the present invention shown in Fig. 1.At this, the action during to the m of readout memory array element 2 and 12 (natural number of m Shi ≦ n) data describes.Also have, in the following description and Fig. 2, omit the label of m.
Before reading action, precharging signal Φ
p, 1V precharging signal PR
s, 1V precharging signal PR
D, word-line signal WL
s, word-line signal WL
D, select signal SEL, action control signal SEN, output signal OUT to become low level.
Precharging signal Φ
pAnd to select signal SEL be high level from low transition at t1 constantly, kept high level at t8 constantly, constantly is converted to low level from high level at t8, keeps low level after this.Therefore, bit line signal BL
sAnd voltage signal DIO
sWith bit line signal BL
DAnd voltage signal DIO
DBecome the signal during t1～t8, it is indefinite to become during other.
The 1V precharging signal PR of the memory array cell of reading (main array element 2 (following identical)) side
sAt t3 is high level from low transition constantly, keeps high level at t6 constantly, constantly is converted to low level from high level at t6, keeps low level then.The 1V precharging signal PR of the memory array cell of not reading on the other hand, (memory array cell 12 (following identical)) side
DKeep low level.
The word-line signal WL of the memory array cell side of reading
sSlowly become big constantly from t2, reach high level constantly, kept high level constantly, constantly slowly diminish, reach low level constantly, keep low level after this at t7 from t6 at t6 at t3.
Therefore, because the storage unit under as the situation of writing unit of the storage unit 3 in the memory array cell read does not have conducting, so bit line signal BL
sAnd voltage signal DIO
sDuring t1～t3, keep 0.5V, constantly rise to 1V, kept 1V constantly, constantly slowly diminish, when reaching 0.5V, kept 0.5V at t8 constantly after this from t6 at t6 from 0.5V at t3.On the other hand, because storage unit 3 in the memory array cell of reading is not a memory cell conducts under the situation of writing unit, so bit line signal BL
sAnd voltage signal DIO
sDuring t1～t2, keep 0.5V, constantly slowly diminish, reach 0V constantly at t3 from t2, kept 0V at t6 constantly, constantly slowly become big from t6, reach 0.5V constantly, kept 0.5V (during t2～t7 with reference to the dotted portion among Fig. 2) constantly at t8 after this at t7.
The word-line signal WL of the memory array cell side of not reading
pKeep low level.Therefore, whether transistor memory unit 13 is not writing units, bit line signal BL
pAnd voltage signal DIO
pDuring t1～t8, keep 0.5V.
And action control signal SEN only becomes high level during t4～t5.Therefore, under the situation of the storage unit of the writing unit in reading the conduct memory array cell of reading, output signal OUT
m(m is the following natural number of 1 above n) only becomes high level during t4～t5.On the other hand, do not read under the situation of storage unit output signal OUT in the writing unit in the memory array cell of reading
1(1 is the following natural number of 1 above n) during t4～t5 also still for low level (about during t4～t5 with reference to the dotted portion among Fig. 2).
By carrying out this action, all carry-out bits of the memory array cell that can in read operation once, read.Promptly in 1 time read operation, can read the data of n position in the present embodiment.Furtherly, for example can once read 1024 data.Also have, read under the situation of output at the memory array cell 12 from the anti-phase input side that is connected sensor amplifier, by make output signal OUT by phase inverter
nAnti-phase, can obtain and the identical signal of output signal under the situation of memory array cell 2 sense datas of the noninverting input side that is connected sensor amplifier.In this case, owing to become the data of readout memory array element 12, therefore 12 become main array element.Also having, is 1024 situation though only represented data bits in the above description, can certainly be other figure place.In addition, though be suitable under the situation of the present invention in as a kind of flash memory of nonvolatile memory especially, the effect on the area is big, and the present invention is also applicable to the storer beyond the nonvolatile memory, i.e. volatile memory.Can exemplify the formation that the storage unit 3 and 12 of the nonvolatile memory of Fig. 1 is replaced into the storage unit of volatibility as a configuration example of relevant volatile memory of the present invention.
Then the concrete configuration example to sensor amplifier 21 describes.The configuration example of expression sensor amplifier 21 in Fig. 3.On the terminal that adds constant voltage Vcc, connect the source electrode of P channel-type MOSFET31 and the source electrode of P channel-type MOSFET32.The common grid of P channel-type MOSFET31 and the grid of P channel-type MOSFET32 of connecting.In addition, connect grid-drain electrode of P channel-type MOSFET31 jointly.
The drain electrode of P channel type MOS transistor 31 is connected in the drain electrode of N channel-type MOSFET33.In addition, the drain electrode with P channel-type MOSFET32 is connected transmission output voltage OUT
nTerminal and the drain electrode of N channel-type MOSFET34 on.
The terminal that is equivalent to non-inverting input (+) of sensor amplifier is connected on the grid of N channel-type MOSFET33.In addition, will be connected on the grid of N channel-type MOSFET34 at this terminal on the reversed input terminal (-) of sensor amplifier.
The source electrode of N channel-type MOSFET33 and the source electrode of N channel-type MOSFET34 are connected jointly, are connected in the drain electrode of N channel-type MOSFET35.The grid of N channel-type MOSFET35 is connected on the terminal of input action control signal SEN.In addition, with the source ground of N channel-type MOSFET35.
Then, other configuration example of expression sensor amplifier 21 in Fig. 4.Also have, the part identical with Fig. 3 paid identical symbol in Fig. 4, omits its detailed explanation.The sensor amplifier of Fig. 4 point different with the sensor amplifier of Fig. 3 is: do not connect the grid of P channel-type MOSFET31 and the grid of P channel-type MOSFET32 jointly, the grid of P channel-type MOSFET31 is connected on the connected node of drain electrode of the drain electrode of P channel-type MOSFET32, the terminal that sends output current OUT and N channel-type MOSFET34, the grid of P channel-type MOSFET32 is connected on the connected node of drain electrode of the drain electrode of P channel-type MOSFET31 and N channel-type MOSFET33, and the grid and the drain electrode that do not connect P channel-type MOSFET31 jointly.
Industrial utilizability
Nonvolatile semiconductor memory device of the present invention can utilize in computer etc.
Claims (6)
1, a kind of semiconductor storage is characterized in that, possesses:
A plurality of the 1st bit lines;
A plurality of 2nd bit lines corresponding respectively with described a plurality of the 1st bit lines;
A plurality of memory cells, it is provided with respectively each described the 1st bit line, is connected respectively with described the 1st bit line;
Pre-charge circuit, it carries out precharge to described memory cell;
With reference to using potential circuit, it provides with reference to using voltage to described the 2nd bit line;
Comparator circuit, it is provided with respectively each described the 1st bit line, the output voltage of each described the 1st bit line and the reference of each described the 2nd bit line of correspondence is compared respectively with voltage, synchronously to read the data of being stored in described a plurality of memory cell.
2, according to the semiconductor storage described in the claim 1, it is characterized in that, when the reading of described data, to the precharge magnitude of voltage of described memory cell, the reference that offers described the 2nd bit line with described reference with potential circuit temporarily is set to different values with magnitude of voltage with described pre-charge circuit.
According to the semiconductor storage described in the claim 1, it is characterized in that 3, described comparator circuit is a plurality of voltage amplifiers.
4, according to the semiconductor storage described in the claim 1, it is characterized in that, between each and described comparator circuit of described memory cell, possess on-off element, switch the selection/non-selection of described memory cell by the conduction and cut-off of described on-off element.
5, according to the semiconductor storage described in the claim 4, it is characterized in that possessing a plurality of basic circuits, this basic circuit is made of described a plurality of memory cells, described pre-charge circuit, described comparator circuit and described on-off element,
The comparator circuit of described a plurality of basic circuits is changed jointly.
6, according to each the described semiconductor storage in the claim 1～5, described memory cell is a flash memory cell.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003046770 | 2003-02-25 | ||
| JP46770/2003 | 2003-02-25 | ||
| JP39596/2004 | 2004-02-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1754229A CN1754229A (en) | 2006-03-29 |
| CN100492543C true CN100492543C (en) | 2009-05-27 |
Family
ID=36680305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200480005107XA Expired - Fee Related CN100492543C (en) | 2003-02-25 | 2004-02-23 | Semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100492543C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100781984B1 (en) * | 2006-11-03 | 2007-12-06 | 삼성전자주식회사 | Sense Amplifier Circuit with Self-Reference and Sensing Method Thereby |
| KR101248942B1 (en) * | 2007-10-17 | 2013-03-29 | 삼성전자주식회사 | Non-volatile memory device |
-
2004
- 2004-02-23 CN CNB200480005107XA patent/CN100492543C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1754229A (en) | 2006-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10475510B2 (en) | Leakage compensation read method for memory device | |
| KR101196936B1 (en) | Nonvolatile semiconductor memory device | |
| US20070211515A1 (en) | Resistive Memory Arrangement | |
| CN1366677A (en) | Reference cell for huigh speed sensing in non-volatile memories | |
| CN101802924B (en) | Reducing noise in semiconductore devices | |
| US8325536B2 (en) | Current sink system for source-side sensing | |
| US8976593B2 (en) | Nonvolatile semiconductor device | |
| US20100290278A1 (en) | Semiconductor memory device rewriting data after execution of multiple read operations | |
| JP2018133118A (en) | Semiconductor device | |
| US9817751B2 (en) | Multi-phase programming schemes for nonvolatile memories | |
| KR20030009316A (en) | Flash memory wordline tracking across whole chip | |
| JP3998908B2 (en) | Nonvolatile memory device | |
| JP2020155168A (en) | Semiconductor storage device | |
| CN107924364A (en) | System, method and device for parallel read and write operation | |
| CN100492543C (en) | Semiconductor storage device | |
| CN102194508A (en) | Memory device | |
| US8130543B2 (en) | Method and apparatus for increasing memory programming efficiency through dynamic switching of sense amplifiers | |
| CN103106920A (en) | Memory access method and flash memory using same | |
| US6795349B2 (en) | Method and system for efficiently reading and programming of dual cell memory elements | |
| US7263012B2 (en) | Semiconductor storage device | |
| CN100483551C (en) | Semiconductor memory device | |
| US12046288B2 (en) | Memory device comprising source switch to float source line of unselected memory cell block, memory array and program method using the same | |
| CN100401421C (en) | Integrated memory with voltage generating circuit for generating voltage for read and write amplifiers | |
| KR100729350B1 (en) | NOR flash memory device performing serial sensing operation | |
| JP3197858B2 (en) | Semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090527 Termination date: 20130223 |