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CN101361136B - Nand architecture memory devices and operation - Google Patents

Nand architecture memory devices and operation Download PDF

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Publication number
CN101361136B
CN101361136B CN2006800516644A CN200680051664A CN101361136B CN 101361136 B CN101361136 B CN 101361136B CN 2006800516644 A CN2006800516644 A CN 2006800516644A CN 200680051664 A CN200680051664 A CN 200680051664A CN 101361136 B CN101361136 B CN 101361136B
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memory cell
coupled
voltage
string
bit line
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CN101361136A (en
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弗朗姬·F·鲁帕尔瓦尔
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Micron Technology Inc
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Micron Technology Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

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  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit line may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device.

Description

NAND architecture memory devices and operation
Technical field
The present invention generally relates to semiconductor memory system, and in particular, the present invention relates to NAND architecture memory devices and operation thereof.
Background technology
Usually provide storage arrangement as the internal semiconductor integrated circuit in computing machine or other electronic installation.There are many dissimilar storeies, comprise random-access memory (ram), ROM (read-only memory) (ROM), dynamic RAM (DRAM), Synchronous Dynamic Random Access Memory (SDRAM) and flash memory.
Flash memory device has developed into and has been used for the generally source of the nonvolatile memory of electronic application widely.Flash memory device uses the one-transistor memory cells that allows high memory density, high reliability and low power consumption usually.The change of the threshold voltage of described unit is by determining the data value of each unit to the programming of charge storage or trapping layer or other physical phenomenon.The general service of flash memory comprises personal computer, PDA(Personal Digital Assistant), digital camera, digital media player, cellular phone and removable memory modules.
Flash memory uses one in two kinds of basic frameworks that are called NOR quickflashing and NAND quickflashing usually.Described title derives from being used to read the logic of described device.In the NOR flash architecture, a row memory cell is coupled in parallel with each memory cell that is coupled to bit line.In the NAND flash architecture, a row memory cell only with the coupling of the first memory units in series of the row that are coupled to bit line.
Along with the performance raising of the electronic system that adopts flash memory device, the performance of flash memory device also should improve.Performance improves to comprise and reduces power consumption, raising speed and improve memory density.
For above-mentioned reasons, and following other reason that after reading and understanding this instructions, will understand owing to the person of ordinary skill in the field, need substituting nand memory framework and operation thereof in the affiliated technical field.
Summary of the invention
The present invention solves problem referred to above and other problem of storage arrangement, and by reading and learning following instructions and will understand described problem.
Illustrate that non-volatile memory device uses modified NAND framework, wherein same bit line optionally is coupled at the two ends of the NAND of memory cell string.Can adopt the mode identical to finish the programming of described memory cell and wipe with traditional nand memory array.Yet reading of memory cell uses the electric charge technology of sharing that is similar to the read operation in the DRAM device to finish according to an embodiment of the invention.
The NAND framework of various embodiment comprises the field-effect transistor Nonvolatile memery unit string of two or more series coupled, and the data value of described unit is determined by its threshold voltage.In the memory cell of the series coupled of string first selects grid optionally to be coupled to bit line via first.Last person in the memory cell of the series coupled of described string selects grid optionally to be coupled to same bit line via second.Described string can logically be divided into two substrings, for example low string and higher string.During the read operation to the target memory cell of one in the described substring, remaining substring is as the memory node of the electric charge of the data value of the described target memory cell of expression.It should be noted that the part of the described substring that comprises described target memory cell also can be used as the part of described memory node, as will be explained in more detail below.
The present invention still further provides the method and apparatus with different range.
Description of drawings
Fig. 1 is the functional block diagram that has the electronic system of at least one storage arrangement according to an embodiment of the invention.
Fig. 2 is the synoptic diagram of a part of the exemplary nand memory array of prior art.
Fig. 3 is the synoptic diagram of the part of nand memory array according to an embodiment of the invention.
Fig. 4 is the process flow diagram that reads the method for memory cell according to an embodiment of the invention.
Fig. 5 is the functional block diagram that has the memory module of at least one storage arrangement according to an embodiment of the invention.
Embodiment
In following detailed description, with reference to forming a part of the present invention and wherein showing the accompanying drawing that to put into practice specific embodiments of the invention therein in the mode of graphic extension to the embodiment of the invention.Fully explain these embodiment so that the person of ordinary skill in the field can put into practice the present invention, but should be appreciated that, also can use other embodiment, and can under the situation that does not deviate from scope of the present invention, make process, electricity or mechanical alteration.Therefore, should not consider following detailed description in a limiting sense, and scope of the present invention is only defined by enclose claims and equivalent thereof.
Fig. 1 is the simplification calcspar of electronic system 100 according to an embodiment of the invention.Electronic system 100 comprises non-volatile memory device 102, and non-volatile memory device 102 comprises Nonvolatile memory unit array 104, address decoder 106, row access circuitry 108, row access circuit 110, control circuit 112, I/O (I/O) circuit 114 and address buffer 116.Nonvolatile memory unit array 104 has framework according to an embodiment of the invention.
Electronic system 100 comprises ppu 120 (for example, Memory Controller or host-processor), and it is electrically connected to storage arrangement 102 to be used for storage access.Storage arrangement 102 receives control signal from processor 120 at control link 122.Described memory cell is used for the data of storage via 124 accesses of data (DQ) link.Via address link 126 be received in address decoder 106 places through the address signal of decoding with access memory array 104 and application source current potential optionally.Address buffer circuit 116 latchs described address signal.Come the described memory cell of access in response to described control signal and described address signal.Control link 122, data link 124 and address link 126 can be referred to as access line.The person of ordinary skill in the field will understand, and additional circuit and control signal can be provided, and the storage arrangement of reduced graph 1 focuses on the present invention with help.
Fig. 2 is the synoptic diagram of a part of the exemplary nand memory array 200 of the prior art that is used to compare that comprised.As shown in Figure 2, memory array 200 comprises word line 202 1To 202 NAnd intersection this ground bit lines 204 1To 204 MFor ease of carrying out addressing in digital environment, the quantity of the quantity of word line 202 and bit line 204 is each certain power of 2 naturally usually.
Memory array 200 comprises NAND string 206 1To 206 MEach NAND string comprises transistor 208 1To 208 N, each is positioned at word line 202 and locates with the point of crossing of this ground bit lines 204.Transistor 208 (being depicted as floating grid transistor in Fig. 2) expression is used to store the Nonvolatile memery unit of data.The floating grid transistor 208 of each NAND string 206 from the source electrode to the drain electrode, be connected in series in drain selection grid 210 (for example, field-effect transistor (FET)) and drain electrode select grid 212 (for example, FET) between.Each drain selection grid 210 is positioned at the point of crossing of this ground bit lines 204 and drain selection line 214, and each drain electrode selects grid 212 to be positioned at the point of crossing of this ground bit lines 204 and drain electrode selection wire 215.
The source electrode of each drain selection grid 210 is connected to common source line 216.The drain electrode of each drain selection grid 210 is connected to the source electrode of first floating grid transistor 208 of corresponding NAND string 206.For instance, the drain electrode of drain selection grid 210 is connected to corresponding NAND string 206 1Floating grid transistor 208 1Source electrode.
Each drain electrode selects the drain electrode of grid 212 to be connected to this ground bit lines 204 of corresponding NAND string.For instance, grid 212 is selected in drain electrode 1Drain electrode be connected to corresponding NAND string 206 1This ground bit lines 204 1Each drain electrode selects the source electrode of grid 212 to be connected to the drain electrode of the last floating grid transistor 208 of corresponding NAND string 206.For instance, grid 212 is selected in drain electrode 1Source electrode be connected to corresponding NAND string 206 1Floating grid transistor 208 NDrain electrode.
The typical construction of floating grid transistor 208 comprise source electrode 230 and drain 232, floating grid 234 and control grid 236, as shown in Figure 2.Floating grid transistor 208 has its control grid 236 that is coupled to word line 202.One row floating grid transistor 208 is those NAND strings 206 that are coupled to this given ground bit lines 204.Delegation's floating grid transistor 208 is those transistors that are coupled to given word line 202 usually.
Be the memory cell in the prior art NAND architecture memory array that reads Fig. 2, memory cell block without selected word line usually as selected word line receives different CONTROLLED POTENTIAL and determines that to allow its data mode its electricity that is associated the burst memory unit leads by the grid operation.In general, drive the word line that is associated with selected column of memory cells with selected fetch stage voltage, described voltage is low-voltage (for example, 0V or ground connection) normally.In addition, (for example, 4.5V) drive the word line that is connected to each string by reading without the grid of word-select memory unit by voltage.This allows it to pass through electric current in the mode that is not subjected to its storage data value restriction.In read operation, electric current passes each string that is connected in series and flows to the row bit line from source electrode line then, and it only is subjected in each string through selecting the restriction with the memory cell that reads.Then, the data value of the selected memory cell of string is determined by the level that sensing passes the electric current of its string that is associated.
Fig. 3 is the synoptic diagram of the part of nand memory array 300 according to an embodiment of the invention.As shown in Figure 3, memory array 300 comprises word line 302 1To 302 NAnd intersection this ground bit lines 304 1To 304 MFor ease of carrying out addressing in digital environment, the quantity of the quantity of word line 302 and bit line 304 is each certain power of 2 naturally usually.
Memory array 300 comprises NAND string 306 1To 306 MEach NAND string comprises field-effect transistor 308 1To 308 N, each is positioned at word line 302 and locates with the point of crossing of this ground bit lines 304.Transistor 308 (being depicted as floating grid transistor in Fig. 3) expression is used to store the Nonvolatile memery unit of data.Though memory array 300 is depicted as the floating grid transistor array, also can use can passing threshold voltage change define other non-volatile memory technologies of data value, for example NROM, floating node, ferroelectric, magnetic and analog.Each data value is usually corresponding to the threshold voltage ranges of mutual exclusion.The floating grid transistor 308 of each NAND string 306 be connected in series in first select grid 312 (for example, FET) with second select grid 313 (for example, FET) between, described floating grid transistor with adjoin memory cell and share regions and source.Each first selection grid 312 is positioned at this ground bit lines 304 and first selection wire 315 1Point of crossing place, and each second selects grid 313 to be positioned at this ground bit lines 304 and second selection wire 315 2Point of crossing place.Be different from traditional nand memory array 200 of Fig. 2, nand memory array 300 does not have the selection grid that is coupled to source electrode line according to an embodiment of the invention.On the contrary, nand memory array 300 makes two of NAND string 306 to select grid 312 and 313 to be coupled to same bit line 304.
First regions and source of each first selection grid 312 is connected to bit line 304.Second regions and source of each first selection grid 312 is connected to first regions and source of first floating grid transistor 308 of corresponding NAND string 306.For instance, first select grid 312 1First regions and source be connected to bit line 304 1And first selects second regions and source of grid 3121 to be connected to corresponding NAND string 306 1Floating grid transistor 308 1First regions and source.Place, opposite end at described string, each second selects second regions and source of grid 313 to be connected to and the identical bit line 304 of its corresponding first drain selection grid 312, and each selects first regions and source of grid 313 to be connected to second regions and source of the last floating grid transistor 308 of corresponding NAND string 306.For instance, the drain selection grid 313 1First regions and source be connected to corresponding NAND string 306 1Floating grid transistor 308 NSecond regions and source and drain selection grid 313 1Second regions and source be connected to bit line 304 1
One rowed transistor or memory cell 308 are those NAND strings 306 that are coupled to this given ground bit lines 304.One row transistor or memory cell 308 are those transistors that are coupled to given word line 302 usually.Also the transistor 308 of other form together can be used with embodiments of the invention, for example NROM, magnetic or ferroelectric transistor and can taking through programming represented other transistor of one in two or more threshold voltages of data mode.
Can logically NAND string 306 be divided into two substrings.For instance, wherein N is certain power of 2, and first substring or low string can comprise memory cell 308 1To 308 N/2, and second substring or higher string can comprise memory cell 308 N/2+1To 308 N
By eliminating needs, can use littler circuit die area and treatment step still less to make memory array 300, thereby promote the raising and the higher memory density of output source electrode and source electrode connection.In addition, because traditional nand memory array 200 relies on the electricity of its NAND string 206 and leads and carry out read operation, therefore because the increase of resistance and do not encourage bigger string length (its often increase reading times and make between different data values, distinguish difficulty more).Yet, as will be explained in more detail below, because nand memory array 300 relies on the electric capacity of its NAND string 306 but not electricity is led and carried out read operation according to an embodiment of the invention, higher string length (promptly, each string has more multiple-unit) will be used to improve available electric capacity, thus incline to the difference of improving between the data value.
Can be similar to the programming of the memory cell 208 of prior art NAND array 200 and wipe and carry out the programming of the memory cell 308 of NAND array 300 and wipe.For instance, for target float gate memory cell 308 1Programming (that is, for improving its threshold voltage by adding electric charge to its floating grid) comprises target memory cell 308 1Word line 302 1Can receive program voltage, it is can be in conjunction with residue node voltage certain positive potential with the memory cell programming.For instance, described program voltage the chances are about 20V.Without selected word line 302 (that is, not with target memory cell 308 1The word line 302 that is associated 2-302 N) receive can cause described without the memory cell on the selected word line during the programming of selected word line as certain positive potential by grid.Described during the programming can be about 10V by voltage.Selected bit line 304 is (that is, with described target memory cell 308 1The bit line 304 that is associated 1) can receive earthing potential Vss, and without selected bit line 304 (that is, not with target memory cell 308 1The bit line 304 that is associated 2-304 M) can receive higher current potential, power supply potential Vcc for example.Though it should be noted that this example explanation, owing to can therefore can there be selected bit line 304 more than simultaneously with one on the given word line 302 above target memory cell 308 programmings only with 308 programmings of a target memory cell.
One group selection grid 312 or 313 can receive respectively and selection wire 315 1Or 315 2On the identical current potential of selected bit line 304, earthing potential Vss for example.Remaining set selects grid 313 or 312 can receive selection wire 315 respectively 2Or 315 1On certain positive potential (for example, power supply potential Vcc), it is enough to activate those that be coupled to selected bit line and selects grids.The bulk substrate that memory cell 308 forms therein can be remained on earthing potential Vss.
Usually will wiping to memory cell block while execute store unit 308.For instance, for wiping floating gate memory unit 308 (promptly, for reducing its threshold voltage) by removing electric charge from its floating grid, the bulk substrate that forms therein when memory cell 308 (for example boosts to certain erasing voltage, in the time of 20V), all word lines 302 can receive earthing potential Vss, and all bit lines 304 can float by electricity, and selection wire 315 1And 315 2Can float by electricity.
Above only expression is used to one group of technology of programming and wiping the memory cell of nand memory array 300.Should note, because typical programming and erase operation do not utilize the source electrode of traditional nand memory array to connect, therefore, be used to programme and many technology of wiping traditional nand memory array 200 also can be applicable to nand memory array 300 according to an embodiment of the invention.Yet,, therefore, depend on the typical read operations that the electricity of memory cell strings leads and be not suitable for embodiments of the invention because NAND string 306 is eliminated the needs that source electrode is connected according to an embodiment of the invention.
Opposite with the traditional read operations of nand memory array, each embodiment of the present invention depends on the part of memory cell strings during read operation electricity is led.Be positioned over electric charge on the memory cell strings that comprises target memory cell and optionally discharge described electric charge according to the data value that is stored in the described target memory cell then.Then, use the electric charge technology of sharing to read described target memory cell or unit with the voltage that raises or reduce on its associated bit line.If described electric charge is retained, so described associated bit line receives described electric charge and improves its voltage level.If described electric charge is released, so described associated bit line is leaked described electric charge to described string and is reduced its voltage level.Carry out read operation because no DC electric current flows through NAND string 306, therefore can promote to be better than remarkable power save based on the mobile traditional read operations of electric current.In addition, be used for described memory cell strings is carried out precharge, optionally discharges described electric charge and use the electric charge technology of sharing to read the desired time expection of described data value to be about hundreds of nanoseconds to being used for some microseconds of traditional electrical introduction extract operation.
Fig. 4 is the process flow diagram that reads the method for memory cell according to an embodiment of the invention.At 440 places, use the first predetermined voltage that the memory cell strings that comprises target memory cell (that is the memory cell that will read) is carried out precharge.Usually, read operation will read the memory cell 308 that is coupled to the selected word line 302 that passes a plurality of bit lines 304.
For NAND is gone here and there 306 1Carry out precharge, can be with bit line 304 1Be driven into first predetermined voltage (for example, power supply potential Vcc) and can be with word line 302 1-302 NBe driven into certain current potential (for example, reading voltage Vread).Described read voltage Vread normally greater than Vcc and be enough to memory cell 308 as by grid operation and no matter its data value certain voltage how (for example, 4.5V).(for example, the NAND string 306 in the described selection wire 1The selection wire 315 at an end place 2) it is associated and selects grid 313 with deactivation will to receive current potential (for example, earthing potential Vss) 1With with described string 306 1Described end and bit line 304 1Isolate.Remaining selection wire (is a selection wire 315 in the case 1) will receive current potential to activate its selection grid 312 that is associated 1Thereby, with NAND string 306 1Be coupled to bit line 304 1
If selection wire 315 1Reception is than the high grid 312 of selecting of described first predetermined voltage 1The current potential of at least one threshold voltage, the NAND string 306 so 1Can be precharged near described first predetermined voltage.For instance, can be with selection wire 315 1Be driven into and read voltage Vread.For for simplicity, can only need also to drive selection wire 315 with power supply potential Vcc 1Thereby, cause NAND 306 1Be charged as near Vcc and deduct selection grid 312 in this example 1Threshold voltage.Also can use other voltage.Yet low precharge level will reduce to be represented through program memory cells through wiping the voltage difference of memory cell, because it will reduce the amount of institute's stored charge.It should be noted that described institute stored charge can be the plus or minus electric charge, this depends on selected voltage.
Though can going here and there 306 arbitrary end from NAND, precharge takes place, preferably from NAND string 306 being carried out precharge from target memory cell 308 end farthest.For instance, wherein NAND string 306 logically is split into low and higher string, when the arbitrary memory cell 308 in the described low string just is being read, will by deactivation the selection grid 313 of close described higher string NAND string 306 and bit line 304 are isolated, and when the arbitrary memory cell 308 in the described higher string just is being read, will NAND string 306 and bit line 304 be isolated by the selection grid 312 of the most close described low string of deactivation.This can simplify, and which selects the logic of grid in order to the decision deactivation.In any case, need with charge storage NAND string 306 in target memory cell 308 and selection grid 312 or 313 one between in the available largest portion.For other embodiment, hypothetical target memory cell 308 X+1If (N-(x+1)), can use NAND string 306 so greater than x 1At memory cell 308 X+1With selection grid 313 1Between part charge storage region is provided, and no matter whether NAND string 306 logically is split into low and higher string.Otherwise, can use NAND string 306 1At memory cell 308 X+1With selection grid 312 1Between part described charge storage region is provided.
After precharge, selection wire 315 1Can receive current potential (for example, earthing potential), select grid 312 with deactivation 1So that NAND is gone here and there 306 1With bit line 304 1Isolation is to keep its electric charge.Yet described read operation can not go here and there 306 with NAND 1Two ends and bit line 304 1Proceed under the situation of isolating.
At 442 places, the data value of based target memory cell optionally removes the electric charge that is stored on the NAND string.For optionally removing electric charge, what preferably described NAND went here and there keeps isolating with its associated bit line from described target memory cell end farthest.This allows the memory node of the largest portion of described string as any residual charge.As an example, be coupled to target memory cell 308 1Selected word line 302 1Can receive current potential and activate described memory cell when having first data value (for example, " 1 " or wipe) at described memory cell, and when described memory cell has second data value (for example, " 0 " or programming) the described memory cell of deactivation.For instance, in the gate-floating memory cell, have usually through wiping memory cell that memory cell by programming may have about 1V or higher threshold voltage less than the threshold voltage of 0V.Therefore, by earthing potential Vss is applied to selected word line 302 1If, target memory cell 308 1If it will be activated and it has described second data value it will be by deactivation so so to have described first data value.By with bit line 304 1Drop to earthing potential Vss, when selecting grid 313 1During by deactivation, select grid 312 1Be activated and without selected word line as by grid, if memory cell 308 1NAND string 306 so is activated 1To lose its charge to bit line 304 1Yet, if memory cell 308 1By deactivation, electric charge will be retained in NAND string 306 so 1In target memory cell 308 1With selection grid 313 1Between described part in.
At 444 places, the bit line 304 that will read is precharged to second predetermined voltage.Described precharge can be gone here and there at NAND and 306 isolates with bit line 304 and be taken place under the situation of (for example, select by deactivation grid 312 and 313 both).Another is chosen as, described precharge can be gone here and there at NAND and be taken place when an end of 306 keeps being coupled to bit line 304 after optionally removing any institute stored charge, if at first drive selected word line 302 with its all memory cells 308 of deactivation no matter its data value how.
For an embodiment, described second predetermined voltage is at described first predetermined voltage and is optionally going here and there the intermediate value between the employed bit-line voltage when removing electric charge from described NAND.In this way, if stored charge is retained, electric charge is shared and will be tended to drive described bit line from described second predetermined voltage to a direction so, if and stored charge is removed, electric charge is shared and will be tended to drive described bit line round about from described second predetermined voltage so.For instance, if NAND string 306 is charged to power supply potential Vcc, and gained institute stored charge is retained at least in half of described string, if bit line 304 is precharged to Vcc/2 or the second lower predetermined voltage then shares the current potential that will tend to improve bit line 304 from institute's stored charge of NAND string 306 so.Equally, if NAND string 306 is discharged to earthing potential Vss, if bit line 304 is precharged to second predetermined voltage greater than Vss so, then the electric charges of sharing with NAND string 306 will tend to reduce the current potential of bit line 304.In this example, so described second predetermined voltage is selected as greater than Vss and is less than or equal to certain value of Vcc/2.For instance, in this sight, can use second predetermined voltage of Vcc/3.If the described part that is not used as memory node of NAND string 306 is precharged to described second predetermined voltage, or wherein electric charge is shared the end that is used as described memory node that passes NAND string 306 and is taken place, the action pane of broad is possible so, because do not lose electric charge in balance NAND string 306.In this case, second predetermined voltage can be chosen as greater than Vss and be less than or equal to certain value (under the condition of above-mentioned example) of Vcc.For some embodiment, described second predetermined voltage can further have and equals in the value of employed bit-line voltage when described NAND string removes electric charge optionally.Yet in this sight, if remove described electric charge at 442 places, the data value of described memory cell will be indicated by the no change of described bit-line voltage after balanced with NAND string 306 so.
At 446 places, electric charge is shared by making NAND string 306 and 304 equilibriums of its associated bit line and is taken place between it.Though,, share but the end as the capacitive character memory node that preferably passes NAND string 306 carries out electric charge can arbitrary the bringing in of passing NAND string 306 carried out electric charge and shared.Yet as mentioned above, the suitable selection of pairs of bit line pre-charge voltage will allow to operate in arbitrary mode.As an example, can by in activate selecting grid 312 or 313 one or all word lines 302 are urged to by voltage Vpass to share as finish electric charge by grid its both the time.Another is chosen as, and selected word line can continue to receive and reads voltage Vread and receive by voltage Vpass without selected word line.Then, can activate the selection grid 312 or 313 that is associated with the end as charge-storage node of NAND string 306.Make its transistor be activated if target memory cell 308 has second data value, the bit line 304 that is associated so will with whole NAND string 306 (its electric charge is removed at 442 places) balance.Make its transistor by deactivation if target memory cell 308 has second data value, the institute in the first of NAND string 306 keeps electric charge and will be shared with bit line 304 so, and NAND goes here and there 306 remainder and can keep and bit line 304 isolation.
At 448 places, but the gained voltage of the associated bit line 304 of based target memory cell 308 changes to determine the data value of target memory cell 308.Understand the data value sensing of this mode well and it is generally used in the DRAM device.As an example, can use the difference detection technology.In this technology, during the precharge (at 444 places) of bit line, also can carry out precharge and make itself and just sensed bit line equalization reference bit lines.Carrying out electric charge shared (at 446 places) before with described reference bit lines and just sensed bit line isolation.By described reference bit lines and just sensed bit line are coupled to the difference sensing amplifier, after sharing electric charge, can determine that the voltage whether just sensed bit line experiences with respect to described reference bit lines rises or voltage decline with selected NAND string.This changes the data value of expression target memory cell.Another is chosen as, and also can use single-ended detection technology.Single-ended sensing apparatus has the single input of being coupled to the target bit line and often comprises the transducer of the output signal of the potential level data value of described target memory cell (thereby represent) that the described target bit line of expression is provided.Described transducer will have the threshold point near precharge potential usually.
Fig. 5 is the graphic extension of exemplary memory module 500.Memory module 500 is illustrated as memory card, but the notion that combined memory module 500 is discussed is applicable in the extractable and changeable or pocket memory (for example USB flash drive) of other type and the set scope that belongs to as used herein " memory module ".In addition, although described an exemplary forms factor in Fig. 5, these notions also are applicable to other form factor.
In certain embodiments, memory module 500 will comprise shell 505 (as depicted) sealing one or more storage arrangements 510, but described shell to use for all devices or device be not most important.At least one storage arrangement 510 is to have the nonvolatile memory of NAND framework according to an embodiment of the invention.If present, shell 505 comprises one or more contacts 515 that are used for communicating with host apparatus.The example of host apparatus comprises digital camera, digital recording and playback reproducer, PDA, personal computer, memory card readers, interface hub and similar device.For some embodiment, contact 515 is the form of standard interface.For instance, for the USB flash drive, contact 515 can be the form of USB type A plug-in connector.For some embodiment, contact 515 is forms of half proprietary interface, for example is found in the CompactFlash by bright dish company (SanDisk Corporation) permission TMMemory card, by the Memory Stick of Sony (SonyCorporation) permission TMMemory card, by the SD Secure Digital of Toshiba (Toshiba Corporation) permission TMOn memory card and the similar storage card.Yet in general, contact 515 is provided in memory module 500 and has the interface that transmits control, address and/or data-signal between the main frame to the receiver of contact 515 compatibilities.
Memory module 500 can optionally comprise additional circuit 520, and it can be one or more integrated circuit and/or discrete component.For some embodiment, additional circuit 520 can comprise the Memory Controller that is used to control the access of passing a plurality of storage arrangements 510 and/or is used to provide the conversion layer between external host and the storage arrangement 510.For instance, a plurality of contacts 515 are with corresponding one to one to may not existing between a plurality of I/O connections of one or more storage arrangements 510.Therefore, the optionally I/O connection of coupled storage apparatus 510 of Memory Controller (demonstration among Fig. 5) provides proper signal in suitable I/O junction reception proper signal or in due course at suitable 515 places, contact between in due course.Equally, main frame can be different with access memory device 510 needed agreements with communication protocol between the memory module 500.So, Memory Controller can be converted to the appropriate command sequence from the command sequence that main frame receives to realize the required access to storage arrangement 510.Except that command sequence, described conversion can further comprise the change of signal voltage level.
Additional circuit 520 can further comprise and irrelevant functional of the control of storage arrangement 510, for example, and the executable logic function of ASIC (special IC).And additional circuit 520 can comprise in order to the circuit that read or write access of restriction to memory module 500, for example cryptoguard, bio-measurement or analog.Additional circuit 520 can comprise the circuit in order to the state of instruction memory module 500.For instance, whether additional circuit 520 can comprise in order to determine whether electric power just is being supplied to memory module 500 and memory module 500 current just by access and show indication (for example, be solid state lamp when the energising and be flashing lamp) functional of its state when just by access.Additional circuit 520 can further comprise passive device (for example, decoupling capacitance device) and need with the power that helps to regulate in the memory module 500.
Sum up
The nand memory array architecture of the Nonvolatile memery unit string with series coupled has been described and has used the electric charge technology of sharing to read the method for nand memory array, bit line optionally is coupled at the two ends of wherein said string.When comparing with traditional nand memory array architecture, described method and apparatus promotes raising, the minimizing of making step and the quickening of read operation of memory density.
Although this paper is graphic extension and explanation specific embodiment, the person of ordinary skill in the field will understand, and will be any as calculated with the alternative shown specific embodiment of the layout that realizes identical purpose.The person of ordinary skill in the field will understand many changes of the present invention.Therefore, set any change of the present invention or the version contained of this application case.The present invention is clear and definite setly only to be limited by above claims and equivalent thereof.

Claims (22)

1. nand memory array, it comprises:
At least one bit line; And
The Nonvolatile memery unit string of at least one series coupled;
Wherein first end of the Nonvolatile memery unit string of first series coupled optionally is coupled to first bit line;
Second end of the Nonvolatile memery unit string of wherein said first series coupled optionally is coupled to described first bit line;
The source electrode that wherein said memory array does not have arbitrary end of the Nonvolatile memery unit string that is coupled to described first series coupled connects; And
Each memory cell of the Nonvolatile memery unit string of wherein said at least one series coupled can passing threshold voltage change define data value.
2. nand memory array as claimed in claim 1, the Nonvolatile memery unit string of wherein said at least one series coupled comprises a plurality of field-effect transistors from the source electrode to the drain coupled.
3. nand memory array as claimed in claim 2, wherein said a plurality of field-effect transistors can passing threshold voltage change define data value.
4. nand memory array as claimed in claim 1, described first and second end of the Nonvolatile memery unit string of wherein said first series coupled optionally is coupled to described first bit line via field-effect transistor.
5. nand memory array as claimed in claim 1, it further comprises:
Nonvolatile memory unit array, it is arranged with row and row; And
A plurality of word lines, it is coupled to the row of described memory cell;
Wherein said at least one bit line comprises a plurality of bit lines, and described a plurality of bit lines optionally are coupled to the row of described memory cell,
The described row of wherein said memory cell further are grouped into the memory cell strings of described series coupled, each string comprises that each in the wherein said selection grid is coupled to same bit line with a plurality of memory cells of coupled in series between two selection grids.
6. nand memory array as claimed in claim 5 wherein defines data value with coupled in series two changes of selecting described a plurality of memory cells between the grid to comprise that further a plurality of field-effect transistors from the source electrode to the drain coupled and each can passing threshold voltages.
7. nand memory array as claimed in claim 5, wherein said selection grid is a field-effect transistor.
8. nand memory array as claimed in claim 1, it further comprises:
With the Nonvolatile memory unit array that row and row are arranged, each memory cell comprises the field-effect transistor of one in the threshold voltage ranges that can have two or more mutual exclusions through programming; And
A plurality of word lines, it is coupled to the row of described memory cell;
Wherein said at least one bit line comprises a plurality of bit lines, and described a plurality of bit lines optionally are coupled to the row of described memory cell,
The described row of wherein said memory cell further are grouped into the Nonvolatile memery unit string of described series coupled;
The Nonvolatile memery unit string of wherein said first series coupled comprises a plurality of memory cells from the source electrode to the drain coupled;
The first memory unit of the Nonvolatile memery unit string of wherein said first series coupled has the regions and source of first regions and source that is coupled to the first selection grid;
The last memory cell of the Nonvolatile memery unit string of wherein said first series coupled has the regions and source of first regions and source that is coupled to the second selection grid;
Wherein said first selects grid to have the residue regions and source that is coupled to described first bit line; And
Wherein said second selects grid to have the residue regions and source that is coupled to described first bit line.
9. method that reads the target memory cell of storage arrangement, it comprises:
Use first voltage that the first at least of the memory cell strings of the series coupled that comprises described target memory cell is carried out precharge;
Data value based on described target memory cell optionally removes electric charge from the described first of described string;
Bit-line pre-charge to the second voltage that will be associated with described string;
Make the described at least first of described string and described through precharge bit line equalization; And
With the described at least first equilibrium of described string after change to determine the described data value of described target memory cell in response to described voltage through bit line precharge.
10. method as claimed in claim 9, wherein said first voltage is positive potential.
11. method as claimed in claim 10, wherein said first voltage is power supply potential Vcc.
12. method as claimed in claim 9 is wherein used first voltage that the first at least of the memory cell strings of the series coupled that comprises described target memory cell is carried out precharge and is further comprised:
Described first voltage is applied to described bit line;
To be applied to each memory cell of described string by voltage, described by voltage be suitable for activating each memory cell and no matter its data value separately how; And
At least one end of described string is coupled to described bit line.
13. method as claimed in claim 9 wherein optionally removes electric charge from the described at least first of described string based on the data value of described target memory cell and further comprises:
The described first and the described bit line of described string are isolated;
Earthing potential is applied to described bit line;
To read voltage and be applied to described target memory cell, describedly read that voltage is suitable for activating described target memory cell when described target memory cell has first data value and the described target memory cell of deactivation when described target memory cell has second data value; And
When described target memory cell receives describedly when reading voltage, the remainder of described string is coupled to described bit line.
14. method as claimed in claim 9 wherein optionally removes electric charge from the described at least first of described string based on the data value of described target memory cell and further comprises:
First end and the described bit line of the described first of the most approaching described string of described string are isolated;
To read voltage and be applied to described target memory cell, describedly read that voltage is suitable for activating described target memory cell when described target memory cell has first data value and the described target memory cell of deactivation when described target memory cell has second data value; And
When described target memory cell receives describedly when reading voltage, earthing potential is applied to described bit line, second end of the remainder of the most approaching described string of wherein said string is coupled to described bit line.
15. method as claimed in claim 9 wherein makes the described at least first of described string and describedly further comprises through the bit line precharge equilibrium:
To be applied to each memory cell of described string by voltage, described by voltage be suitable for activating each memory cell and no matter its data value separately how; And
At least one end of described string is coupled to described bit line.
16. method as claimed in claim 9 wherein makes the described at least first of described string and describedly further comprises through the bit line precharge equilibrium:
To be applied to each memory cell of the described first of described string by voltage, described by voltage be suitable for activating each memory cell and no matter its data value separately how; And
The end of the described first of approaching described string of described string is coupled to described bit line.
17. method as claimed in claim 9 is wherein used first voltage that the first at least of the memory cell strings of the series coupled that comprises described target memory cell is carried out precharge and is comprised:
Grid voltage is applied to each memory cell of the memory cell strings of described series coupled, described grid voltage be suitable for activating described memory cell and no matter be stored in the described memory cell data value how;
The memory cell strings of described series coupled is coupled to described bit line; And
Described first voltage is applied to described bit line;
18. method as claimed in claim 17 wherein optionally removes electric charge from the described at least first of described string based on the data value of described target memory cell and comprises:
The memory cell strings of described series coupled and described bit line are isolated, and the remainder that the described first of the memory cell strings of wherein said series coupled comprises the memory cell strings of memory cell between first end of memory cell strings of described target memory cell and described series coupled and wherein said series coupled comprises the memory cell between second end of memory cell strings of described target memory cell and described series coupled;
Tertiary voltage is applied to described bit line;
Grid voltage is applied to described target memory cell, and described grid voltage is suitable for activating described target memory cell and is suitable for the described target memory cell of deactivation when described target memory cell has second data value when described target memory cell has first data value;
Grid voltage is applied to remaining memory unit in the memory cell strings of described series coupled to activate described remaining memory unit no matter be stored in the described remaining memory unit data value how; And
The described remainder of the memory cell strings of described series coupled is coupled to described bit line.
19. method as claimed in claim 18 wherein makes the described at least first of described string and describedly comprises through the bit line precharge equilibrium:
To be applied to each memory cell of described first of the memory cell strings of described series coupled by voltage, described by voltage be suitable for activating each memory cell and no matter its data value separately how; And
Described first end of the memory cell strings of described series coupled is coupled to described bit line.
20. method as claimed in claim 19, wherein said second voltage are the medium voltages between described first voltage and the described tertiary voltage.
21. method as claimed in claim 20, wherein said first voltage are that positive potential and described tertiary voltage are earthing potentials.
22. method as claimed in claim 19 is wherein determined in response to the voltage level of described bit line that the described data value of described target memory cell further comprises and is used difference or single-ended sensing to determine described data value.
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Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7489546B2 (en) 2005-12-20 2009-02-10 Micron Technology, Inc. NAND architecture memory devices and operation
US7859903B1 (en) * 2008-02-14 2010-12-28 Flashsilicon, Inc. Methods and structures for reading out non-volatile memory using NVM cells as a load element
KR20090120205A (en) * 2008-05-19 2009-11-24 삼성전자주식회사 Flash memory device and its operation method
US8514624B2 (en) 2011-06-21 2013-08-20 Micron Technology, Inc. In-field block retiring
US8582380B2 (en) 2011-12-21 2013-11-12 Micron Technology, Inc. Systems, circuits, and methods for charge sharing
US8659963B2 (en) * 2012-01-05 2014-02-25 International Business Machines Corporation Enhanced power savings for memory arrays
US8861285B2 (en) 2012-02-09 2014-10-14 Micron Technology, Inc. Apparatuses and methods for line charge sharing
US8755228B2 (en) * 2012-08-09 2014-06-17 Kabushiki Kaisha Toshiba Writing method of nonvolatile semiconductor memory device
US8780633B2 (en) * 2012-11-09 2014-07-15 SanDisk Technologies, Inc. De-duplication system using NAND flash based content addressable memory
US8817541B2 (en) * 2012-11-09 2014-08-26 Sandisk Technologies Inc. Data search using bloom filters and NAND based content addressable memory
US8792279B2 (en) * 2012-11-09 2014-07-29 Sandisk Technologies Inc. Architectures for data analytics using computational NAND memory
US9104551B2 (en) * 2012-11-09 2015-08-11 Sandisk Technologies Inc. NAND flash based content addressable memory
US8811085B2 (en) * 2012-11-09 2014-08-19 Sandisk Technologies Inc. On-device data analytics using NAND flash based intelligent memory
US8634248B1 (en) * 2012-11-09 2014-01-21 Sandisk Technologies Inc. On-device data analytics using NAND flash based intelligent memory
US8780634B2 (en) * 2012-11-09 2014-07-15 Sandisk Technologies Inc. CAM NAND with OR function and full chip search capability
US8773909B2 (en) * 2012-11-09 2014-07-08 Sandisk Technologies Inc. CAM NAND with or function and full chip search capability
US8780632B2 (en) * 2012-11-09 2014-07-15 Sandisk Technologies Inc. De-duplication techniques using NAND flash based content addressable memory
US8780635B2 (en) * 2012-11-09 2014-07-15 Sandisk Technologies Inc. Use of bloom filter and improved program algorithm for increased data protection in CAM NAND memory
US9075424B2 (en) 2013-03-06 2015-07-07 Sandisk Technologies Inc. Compensation scheme to improve the stability of the operational amplifiers
TW201621670A (en) * 2014-09-06 2016-06-16 Neo半導體股份有限公司 Method and apparatus for writing nonvolatile memory using multiple-page programming
US9761310B2 (en) 2014-09-06 2017-09-12 NEO Semiconductor, Inc. Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions
TWI622055B (en) * 2014-09-24 2018-04-21 Neo半導體股份有限公司 Method and apparatus for storing information using a memory able to perform both nvm and dram functions
US10096356B2 (en) * 2015-12-04 2018-10-09 Toshiba Memory Corporation Method of operation of non-volatile memory device
US10418085B2 (en) * 2017-07-20 2019-09-17 Micron Technology, Inc. Memory plate segmentation to reduce operating power
US10685702B2 (en) * 2017-08-28 2020-06-16 Micron Technology, Inc. Memory array reset read operation
US10522202B2 (en) * 2018-04-23 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and compensation method therein
US11081162B1 (en) 2020-02-24 2021-08-03 Sandisk Technologies Llc Source side precharge and boosting improvement for reverse order program
US11227869B1 (en) 2020-12-04 2022-01-18 Micron Technology, Inc. Memory array structures for capacitive sense NAND memory
US11670379B2 (en) 2020-12-04 2023-06-06 Micron Technology, Inc. Sense line structures in capacitive sense NAND memory
US11386966B2 (en) 2020-12-04 2022-07-12 Micron Technology, Inc. Access operations in capacitive sense NAND memory
US11437106B2 (en) 2020-12-04 2022-09-06 Micron Technology, Inc. Capacitive sense NAND memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898615A (en) * 1997-03-19 1999-04-27 Fujitsu Limited Semiconductor memory device having non-volatile memory cells connected in series
US5909392A (en) * 1997-10-09 1999-06-01 Programmable Microelectronics Corporation PMOS memory array having OR gate architecture
CN1431712A (en) * 2002-01-11 2003-07-23 力旺电子股份有限公司 Random Programmable Non-Volatile Semiconductor Memory
CN1536578A (en) * 2003-04-03 2004-10-13 �����ɷ� Method of operation of non-volatile memory cell array

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US622762A (en) * 1899-04-11 Steam-engine
US4870770A (en) * 1984-12-10 1989-10-03 Ultra Light Arms, Inc. Safety mechanism for firearms
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US5729493A (en) 1996-08-23 1998-03-17 Motorola Inc. Memory suitable for operation at low power supply voltages and sense amplifier therefor
KR100281127B1 (en) * 1998-11-19 2001-03-02 김영환 NAND type nonvolatile ferroelectric memory cell and nonvolatile ferroelectric memory device using the same
JP3866460B2 (en) * 1998-11-26 2007-01-10 株式会社東芝 Nonvolatile semiconductor memory device
US6147910A (en) 1999-08-31 2000-11-14 Macronix International Co., Ltd. Parallel read and verify for floating gate memory device
US6747892B2 (en) * 2000-11-21 2004-06-08 Sandisk Corporation Sense amplifier for multilevel non-volatile integrated memory devices
JP3829088B2 (en) * 2001-03-29 2006-10-04 株式会社東芝 Semiconductor memory device
US7177197B2 (en) * 2001-09-17 2007-02-13 Sandisk Corporation Latched programming of memory and method
US6870770B2 (en) 2001-12-12 2005-03-22 Micron Technology, Inc. Method and architecture to calibrate read operations in synchronous flash memory
US6907497B2 (en) * 2001-12-20 2005-06-14 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device
US6646914B1 (en) * 2002-03-12 2003-11-11 Advanced Micro Devices, Inc. Flash memory array architecture having staggered metal lines
US7052497B2 (en) 2002-08-14 2006-05-30 Sdgi Holdings, Inc. Techniques for spinal surgery and attaching constructs to vertebral elements
AU2003300007A1 (en) 2002-12-31 2004-07-29 Matrix Semiconductor, Inc. Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US7050346B2 (en) 2003-07-29 2006-05-23 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and electric device with the same
JP4322686B2 (en) 2004-01-07 2009-09-02 株式会社東芝 Nonvolatile semiconductor memory device
US7072217B2 (en) 2004-02-24 2006-07-04 Micron Technology, Inc. Multi-state memory cell with asymmetric charge trapping
DE602004010239T2 (en) 2004-05-20 2008-09-25 Stmicroelectronics S.R.L., Agrate Brianza Improved page memory for a programmable memory device
JP4271168B2 (en) * 2004-08-13 2009-06-03 株式会社東芝 Semiconductor memory device
US7379333B2 (en) * 2004-10-28 2008-05-27 Samsung Electronics Co., Ltd. Page-buffer and non-volatile semiconductor memory including page buffer
US7489546B2 (en) * 2005-12-20 2009-02-10 Micron Technology, Inc. NAND architecture memory devices and operation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898615A (en) * 1997-03-19 1999-04-27 Fujitsu Limited Semiconductor memory device having non-volatile memory cells connected in series
US5909392A (en) * 1997-10-09 1999-06-01 Programmable Microelectronics Corporation PMOS memory array having OR gate architecture
CN1431712A (en) * 2002-01-11 2003-07-23 力旺电子股份有限公司 Random Programmable Non-Volatile Semiconductor Memory
CN1536578A (en) * 2003-04-03 2004-10-13 �����ɷ� Method of operation of non-volatile memory cell array

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US8472254B2 (en) 2013-06-25
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US20070140012A1 (en) 2007-06-21
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