CN102169879B - Highly integrated wafer fan-out packaging structure - Google Patents

Abstract

The invention relates to a highly integrated wafer fan-out packaging structure, comprising: a packaged unit including a chip and a passive device, the packaged unit has a functional surface; the other surface opposite to the functional surface of the packaged unit is formed with a sealing material The encapsulating material layer encapsulates and solidifies the encapsulated units, and the surface of the encapsulating material layer is provided with grooves corresponding to the encapsulated units. Compared with the prior art, the highly integrated wafer fan-out packaging structure claimed in the present invention integrates chips and passive devices and then packages them together, which is the final package that includes the overall system function rather than a single chip function product. In addition, the whole chip package of the sealing material layer is decomposed into multiple packaged units, and the internal stress of the sealing material layer is reduced through the grooves between the packaged units, thereby preventing the sealing material layer from being damaged in the subsequent process of wafer packaging. Warpage occurs, which improves the quality of the finished wafer package.

Description

Highly integrated wafer fan-out packaging structure

technical field

The invention relates to semiconductor technology, in particular to a highly integrated wafer fan-out packaging structure.

Background technique

Wafer Level Packaging (WLP) technology is a technology that performs packaging and testing on the entire wafer and then cuts it to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip size packaging technology has completely subverted traditional packaging such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier), etc. Small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology has reached a high degree of miniaturization, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a technology that can integrate IC design, wafer manufacturing, packaging testing, and substrate manufacturing. It is a hot spot in the current packaging field and a future development trend.

Fan-out wafer packaging is a type of wafer-level packaging. For example, Chinese Invention Patent Application No. 200910031885.0 discloses a wafer-level fan-out chip packaging method, which includes the following process steps: sequentially encapsulating a peel-off film and a thin film dielectric layer I on the surface of a carrier wafer, and forming a photolithographic pattern on the thin film dielectric layer I. Graphical opening I; metal electrodes connected to the substrate end and redistributed metal traces are realized on the graphical opening I and its surface; surface packaging of the metal electrode surface connected to the substrate end, the redistributed metal trace surface, and the thin film dielectric layer I Thin-film dielectric layer II, and form a photolithography pattern opening II on the film dielectric layer II; realize the metal electrode connected to the chip end at the photolithography pattern opening II; flip the chip to the metal electrode connected to the chip end and perform injection molding material layer and solidified to form a package with a plastic encapsulant layer; separate the carrier wafer and release film from the package with a plastic encapsulant layer to form a plastic encapsulation wafer; reflow the balls to form solder ball bumps; monolithic Dicing to form the final fan-out chip structure.

The final product packaged and manufactured according to the above method has only a single chip function. To realize complete system functions, it is necessary to add peripheral circuits including various capacitors, inductors or resistors to the final product.

Contents of the invention

The technical problem solved by the invention is: how to realize a highly integrated wafer fan-out packaging structure.

In order to solve the above technical problems, the present invention provides a highly integrated wafer fan-out packaging structure, including:

A packaged unit includes a chip and a passive device, and the packaged unit has a functional surface;

The other surface opposite to the functional surface of the packaged unit is formed with a sealing material layer, which encapsulates and solidifies the packaged unit, and grooves are provided on the surface of the sealing material layer corresponding to the packaged units.

Optionally, the functional surface refers to the surface where the metal electrodes of the chips and the pads of the passive devices in the packaged unit are located.

Optionally, the encapsulant layer also fills the space between the chips, between the chip and the passive device, and/or between the passive device and the passive device.

Optionally, the passive components include capacitors, resistors and inductors.

Optionally, the material of the sealing material layer is epoxy resin.

Optionally, the encapsulant layer is formed on the chip and passive devices by means of transfer, compression or printing.

Optionally, there are multiple grooves, and each groove is closed around the packaged unit.

Optionally, the shape enclosed by each groove includes a square, a rectangle or a circle.

Optionally, keep the same distance between each groove.

Optionally, the grooves are arranged in a matrix.

Optionally, the groove has a U-shaped, V-shaped or concave cross-section.

Optionally, the chip includes a plurality of different chips.

Optionally, a metal interconnection structure is formed on the functional surface of the packaging unit.

Optionally, the metal interconnection structure includes: a metal rewiring layer and an under-ball metal layer sequentially located on the functional surfaces of the chip and passive devices, and metal solder balls located on the surface of the under-ball metal layer. A protective film is also formed between the metal layer and the metal rewiring layer.

Compared with the prior art, the highly integrated wafer fan-out packaging structure claimed in the present invention integrates chips and passive devices and then packages them together, which is a packaging structure that includes the overall system function rather than a single chip function , Compared with the existing system-level packaging structure, the highly integrated wafer-level packaging structure reduces the interference factors such as internal resistance and inductance of the system, and can better meet the trend of thin and short semiconductor packaging. In addition, the entire package of the encapsulant layer is decomposed into multiple small packaged units, and the grooves provided between the encapsulated units can reduce the internal stress of the encapsulant layer, which can prevent the subsequent encapsulation of the encapsulant layer in the wafer package. Warpage occurs during the process, which improves the quality of the finished wafer package.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a highly integrated wafer fan-out package structure in an embodiment of the present invention;

FIG. 2 is a schematic top view of a highly integrated wafer fan-out packaging structure in an embodiment of the present invention;

3 is a flowchart of a method for forming a highly integrated wafer fan-out packaging structure in an embodiment of the present invention;

4 is a flowchart of a method for forming a highly integrated wafer fan-out packaging structure in another embodiment of the present invention;

5 to 13 are schematic diagrams of the packaging structure in the process shown in FIG. 4 .

Detailed ways

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

The packaging structure in the prior art only has a single chip function. To realize complete system functions, it is necessary to add peripheral circuits including various capacitors, inductors or resistors to the final product.

In order to solve the above problems, the present invention provides a highly integrated wafer fan-out packaging structure, including: a packaged unit, including a chip and a passive device, and the packaged unit has a functional surface;

The other surface opposite to the functional surface of the packaged unit is formed with a sealing material layer, which encapsulates and solidifies the packaged unit, and grooves are provided on the surface of the sealing material layer corresponding to the packaged units.

The highly integrated wafer fan-out packaging structure of the present invention will be described in detail below with reference to the accompanying drawings.

As shown in Figure 1, the highly integrated wafer fan-out packaging structure of the present invention includes: a sealing material layer 05, a number of packaged units encapsulated by the sealing material layer 05, and the packaged units include chips 03 and Passive Components 04. Wherein, the functional surface of the chip 03 and the passive device 04 is electrically connected to the metal interconnection structure, and the functional surface refers to the surface where the metal electrodes of the chip 03 and the pads of the passive device 04 in the packaged unit are located.

The metal interconnection structure includes a metal rewiring layer 06 and an under-ball metal layer 08 located on the functional surfaces of the chip 03 and the passive device 04 in sequence, and a metal solder ball 09 located on the surface of the under-ball metal layer. A protective film 07 is also formed between the metal layer 08 and the metal rewiring layer 06 .

In a preferred embodiment of the present invention, the chip 03 may be a plurality of different chips, and each of these chips becomes a part of a system-in-package product, and each implements one or more individual functions in the system-level functions .

In the present invention, the passive device 04 is an external circuit device that realizes the system-level function of the packaged unit together with the chip 03, including capacitors, resistors, and inductors. Combining the passive device 04 and the chip 03 with different functions to form a packaged unit and packaging can realize the required system-level functions.

In a preferred embodiment of the present invention, the combination of the chip 03 and the passive device 04 is designed according to the system function of the packaged unit. Therefore, around a chip 03, there may be other chips 03 that are the same or different, or passive devices 04 such as the same or different capacitors, resistors or inductances; similarly, around a passive device 04, there may be The same or different other passive components 04, or one or more same or different chips 03.

Continuing to refer to FIG. 1 , the encapsulant layer 05 is formed by encapsulating and curing the packaged unit including the chip 03 and the passive device 04 with a plastic encapsulant layer. In the subsequent process, the encapsulation layer 05 can protect other surfaces except the functional surface of the chip 03 and the passive device 04 , and can also serve as a carrier for the subsequent process.

In one embodiment of the present invention, the material of the sealing material layer 05 is epoxy resin. This material has good sealing performance and is easy to shape, so it is a better material for forming the sealing material layer 05 . Wherein, the method of forming the encapsulant layer 05 may be, for example, transfer, compression or printing.

Continuing to refer to FIG. 1, as mentioned above, around a chip 03, there may be other chips 03 or passive devices 04; around a passive device 04, there may also be other same or different passive components. Device 04, or one or more same or different chips 03. Therefore, there will be voids around the chip 03 or the passive device 04 . In order to better protect the chip 03 and the passive device 04, the encapsulant layer 05 is also filled between the chip 03 and the chip 03, between the chip 03 and the passive device 04, and/or between the passive device 04 and the passive device 04 space between.

Since the chip 03 and the passive device 04 have different thicknesses, the chip 03 may be thicker, and the passive device 04 may be thicker. Therefore, the thickness of the encapsulant layer 05 should be greater than the thickness of the thickest one among the chips 03 and the passive devices 04 , so as to provide optimal protection for the chips 03 and the passive devices 04 .

Continuing to refer to FIG. 1 and referring to FIG. 2 at the same time, a groove 50 is provided between each packaged unit of the encapsulant layer 05 . These grooves 50 are formed after printing through the design of the opening and depth of the stencil screen. After the groove 50 is formed, the stress in the encapsulant layer 05 can be balanced, so as to avoid warping and deformation in the subsequent process of wafer packaging.

The cross-section of the groove 50 can be designed differently according to the stress in the encapsulant layer 05 and the profile of the device to be packaged. In a preferred embodiment, the cross section of the groove 50 includes a U shape, a V shape or a concave shape.

The depth of the groove 50 is related to the design of the stencil stencil. The thickness of the groove 50 set according to the design of the stencil stencil can effectively balance the internal stress of the sealing material layer 05 .

Referring to FIG. 1 and FIG. 2 at the same time, in a preferred embodiment of the present invention, there are multiple grooves 50, and each groove 50 is closed into a ring around a packaged unit. This annular structure can effectively reduce the stress of the encapsulant layer 05 around the chip 03 and the passive device 04 , thereby further balancing the stress distribution inside the encapsulant layer 05 . The ring formed by each groove 50 includes a square, a rectangle or a circle. The packaged unit delimited by each annular groove 50 may contain multiple chips 03 , or combine passive devices 04 . The packaged units are arranged in a matrix, and the grooves 50 are arranged between the packaged units, similar to criss-crossing rice paddies.

The annular groove 50 has multiple arrangements, which can adapt to different arrangements of the chip 03 and the passive device 04 . In another preferred embodiment of the present invention, a plurality of annular grooves 50 are arranged in a matrix.

The highly integrated wafer fan-out packaging structure of the present invention integrates the chip 03 and the passive device 04 and then packages them together. It is a packaging structure that includes the overall system function rather than a single chip function. Compared with the existing system Level packaging structure, the highly integrated wafer level packaging structure reduces the interference factors such as internal resistance and inductance of the system, and can better comply with the trend of light, thin and short semiconductor packaging. In addition, the entire package of the encapsulant layer is decomposed into multiple small packaged units, and the grooves 50 provided between the encapsulated units can reduce the internal stress of the encapsulant layer, thereby preventing the encapsulant layer from being damaged in the subsequent process of wafer encapsulation. Warpage occurs during the process, which improves the quality of the finished wafer package.

The method for forming the highly integrated wafer fan-out packaging structure of the present invention will be described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 3, in one embodiment of the present invention, a method for forming a highly integrated wafer fan-out packaging structure is provided, including steps:

S101, forming an adhesive layer on the carrier plate;

S102, affixing the functional surface of the packaged unit composed of the chip and the passive device on the adhesive layer;

S103, forming a sealing material layer on the side of the carrier board on which the chip and the passive device are pasted, and performing encapsulation and curing, and the surface of the sealing material layer is provided with grooves corresponding to the units to be packaged;

S104 , removing the carrier board and the adhesive layer.

As shown in FIG. 4, in another embodiment of the present invention, a method for forming a highly integrated wafer fan-out packaging structure is provided, including steps:

S201, forming an adhesive layer on the carrier plate;

S202, affixing the functional surface of the packaged unit composed of the chip and the passive device on the adhesive layer;

S203, forming a sealing material layer on the side of the carrier board on which the chip and the passive device are pasted, and performing encapsulation and curing, and the surface of the sealing material layer is provided with grooves corresponding to the units to be packaged;

S204, removing the adhesive layer;

S205, separating the carrier board from the functional surface of the chip and the passive device;

S206, cleaning the functional surface of the chip and the passive device;

S207, performing metal rewiring on exposed functional surfaces of chips and passive components;

S208, forming a protective film on the surface where the metal rewiring is located, and forming an opening exposing the metal surface on the protective film;

S209, forming an under-ball metal layer on the metal surface in the opening of the protective film;

S210, forming metal solder balls on the surface of the under-ball metal layer.

In this embodiment, step S201 is first performed to form an adhesive layer 102 on the carrier 101 to form the structure shown in FIG. 5 .

In this step, the carrier board 101 is the basis for carrying subsequent chips 103 and passive devices 104 .

In this embodiment, the substrate 101 is made of glass, which can provide better hardness and flatness, and reduce the failure ratio of packaged devices. In addition, since the carrier 101 will be peeled off in subsequent steps, and the carrier 101 made of glass is easy to peel off, has strong corrosion resistance, and will not change its physical and chemical properties due to contact with the adhesive layer 102, so it can be carried out. reuse. Certainly, those skilled in the art understand that the object of the present invention can also be achieved by using, for example, a silicon compound as the carrier 101 .

The adhesive layer 102 formed on the carrier 101 is used to fix the packaged unit composed of the chip 103 and the passive device 104 on the carrier 101 . The adhesive layer 102 can be made of various materials, and in a preferred embodiment of the present invention, the adhesive layer 102 is made of UV glue. UV glue is a bonding material that responds to ultraviolet light of a specific wavelength. UV glue can be divided into two types according to the change of viscosity after ultraviolet light irradiation. One is UV curing glue, that is, the photoinitiator or photosensitizer in the material absorbs ultraviolet light under ultraviolet irradiation to generate active free radicals or cations, triggering Monomer polymerization, cross-linking and branching chemical reactions make the UV-curable glue change from liquid to solid in a few seconds, thereby bonding the surface of the object in contact with it; the other is UV glue that is not exposed to ultraviolet light The viscosity is very high, and the cross-linking chemical bonds in the material are interrupted after ultraviolet light irradiation, resulting in a significant decrease or disappearance of the viscosity. The UV glue used in the adhesive layer 102 here is the latter.

The method of forming the adhesive layer 102 on the carrier 101 may be, for example, coating the adhesive layer 102 on the carrier 101 by spin coating or printing. Such methods are well known to those skilled in the art in the field of semiconductor manufacturing and will not be repeated here.

After the adhesive layer 102 is formed on the carrier board 101 , step S202 can be performed to paste the functional surface of the packaged unit composed of the chip 103 and the passive device 104 on the adhesive layer 102 to form a structure as shown in FIG. 6 .

In a specific embodiment of the present invention, the functional surface of the packaged unit composed of the chip 103 and the passive device 104 refers to the surface where the metal electrodes of the chip 103 and the pads of the passive device 104 are located in the packaged unit.

In a preferred embodiment of the present invention, the plurality of chips 103 bonded on the adhesive layer 102 may be a plurality of different chips, and each of these chips becomes a part of a system-in-package product, and each completes the realization of system-level functions. One or more individual functions in .

The passive device 104 is an external circuit device that together with the chip 103 realizes the system-level function of the packaged unit, including capacitors, resistors, and inductors. Combining and packaging the passive device 104 and the chip 103 with different functions can realize the required system-level functions.

In a preferred embodiment of the present invention, the combination of the chip 103 and the passive device 104 is designed according to the system function of the packaged unit. Therefore, around a chip 103, there may be other chips 103 that are the same or different, or passive devices 104 such as the same or different capacitors, resistors or inductances; similarly, around a passive device 104, there may be The same or different other passive components 104 , or one or more same or different chips 103 .

Then step S203 is executed, encapsulating and curing the surface of the substrate with the chip and passive components in a plastic encapsulant layer to form a package with an encapsulant layer 105 , that is, to form the structure shown in FIG. 7 . In the subsequent process, the package can protect other surfaces except the functional surface of the chip 103 and the passive device 104 , and can also serve as a carrier for the subsequent process.

In one embodiment of the present invention, the material forming the encapsulant layer 105 is epoxy resin. This material has good sealing performance and is easy to shape, so it is a better material for forming the sealing material layer 105 . The method of forming the encapsulant layer 105 may be, for example, transfer, compression or printing. The specific steps of these methods are well known to those skilled in the art and will not be repeated here.

As mentioned above, around a chip 103, there may be another chip 103, or a passive device 104; around a passive device 104, there may also be the same or different other passive devices 104, or a or multiple identical or different chips 103 . Therefore, there will be voids around the chip 103 or the passive device 104 . In order to better protect the chip 103 and the passive device 104, the encapsulant layer 105 is also filled between the chip 103 and the chip 103, between the chip 103 and the passive device 104 and/or between the passive device 104 and the passive device 104 spaces between.

Since the chip 103 and the passive device 104 have different thicknesses, the chip 103 may be thicker, and the passive device 104 may be thicker. Therefore, the thickness of the encapsulant layer 105 should be greater than the thickness of the thickest one among the chips 103 and the passive devices 104 to provide optimal protection for the chips 103 and the passive devices 104 .

Due to the different thermal shrinkage ratios of the two materials of the sealing material layer 105 and the carrier plate 101, the internal stress of the sealing material layer 105 is uneven, which will cause the sealing material layer 105 to warp and deform in the subsequent process of wafer packaging, thereby affecting to the quality of the packaged finished product.

Therefore, as shown in FIG. 8 , in a specific embodiment of the present invention, a groove 150 is provided between each packaged unit of the encapsulant layer 105 . These grooves 150 are formed after printing through the design of the opening and depth of the stencil screen. After the groove 150 is formed, the stress in the encapsulant layer 105 can be balanced, so as to avoid warping and deformation in the subsequent process of wafer packaging.

The cross-section of the groove 150 can be designed differently according to the stress in the encapsulant layer 105 and the profile of the device to be packaged. In a preferred embodiment, the cross section of the groove 150 includes a U shape, a V shape or a concave shape.

The depth of the groove 150 is related to the design of the stencil stencil. The thickness of the groove 150 set according to the design of the stencil stencil can effectively balance the internal stress of the encapsulant layer 105 .

In a preferred embodiment of the present invention, there are multiple grooves 150, and each groove 150 is surrounded by a packaged unit to form a ring. This annular structure can effectively reduce the stress of the encapsulant layer 105 around the chip 103 and the passive device 104 , thereby further balancing the stress distribution inside the encapsulant layer 105 . The ring formed by each groove 150 includes a square, a rectangle or a circle. The packaged unit delimited by each annular groove 150 may contain multiple chips 103 , or combine passive devices 104 . The packaged units are arranged in a matrix, and the grooves 150 are arranged between the packaged units, similar to criss-crossing rice paddies.

The annular groove 150 has multiple arrangements, which can adapt to different arrangements of the chip 103 and the passive device 104 . In another preferred embodiment of the present invention, a plurality of annular grooves 150 are arranged in a matrix.

Step S204 is then executed to remove the adhesive layer 102 . Since the adhesive layer 102 is an organic material, it can be dissolved in a specific organic solvent. Therefore, an organic solvent cleaning method may be used to dissolve the adhesive layer 102 in the organic solvent.

Then step S205 is executed to separate the carrier board 101 from the functional surfaces of the chip 103 and the passive device 104 . That is to say, after step S204 is performed, the adhesive layer 102 has been removed from the solvent, or is in a peelable molten state, and the carrier 101 can be easily peeled off from the functional surfaces of the chip 103 and the passive device 104, thereby exposing The functional surfaces of the chip 103 and the passive device 104 are shown.

Step S206 is then executed to clean the functional surfaces of the chip 103 and the passive device 104, and form the structure shown in FIG. 9 with the adhesive layer 102 remaining on the functional surface. At this time, the chip 103 and the passive device 104 no longer penetrate the carrier board It is fixed together by the package body, and the metal electrodes of the chip and the pads of the passive devices are also exposed.

As shown in Figures 10 to 13, step S207 to step S210 are then performed, including: metal rewiring 106 is performed on the exposed functional surface of the chip and passive devices, so that the metal electrodes of the chip and the pads of the passive devices are transparent The redistributed metal lines realize functional system interconnection and routing; a protective film 107 is formed on the surface where the metal rewiring is located, and an opening required by the design is formed on the protective film to expose the metal rewiring 106; the metal in the opening of the protective film An under-ball metal layer 108 is formed on the wiring 106 ; metal solder balls 109 are formed on the surface of the under-ball metal layer 108 . Steps S207 to S210 are the same as the conventional fan-out wafer packaging method, and will not be repeated here.

After the above steps, the system-in-package has been basically completed.

Although the present invention has been disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (12)

1. high integration wafer fan-out encapsulating structure is characterized in that, comprising:

Packed unit comprises chip and passive device, and described packed unit has the function face;

The another side relative with the function face of packed unit is formed with the envelope bed of material, and the described envelope bed of material carries out package curing to packed unit;

The function face of described packed unit is formed with metal interconnect structure, and the described envelope bed of material is as the supporting body of packed unit and metal interconnect structure;

Described envelope bed of material surface is corresponding to being provided with groove between the packed unit, and described groove seals into ring around packed unit, and described groove does not expose the metal interconnect structure between the adjacent packed unit.

2. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described function face refers to the surface, pad place of metal electrode and the passive device of packed unit chips.

3. high integration wafer fan-out encapsulating structure as claimed in claim 1 is characterized in that: the described envelope bed of material also is filled between described chip and the chip, between chip and the passive device and/or the space between passive device and the passive device.

4. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described passive device comprises electric capacity, resistance and inductance.

5. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: the material of the described envelope bed of material is epoxy resin.

6. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: the described envelope bed of material is formed on described chip and the passive device by metaideophone, compression or method of printing.

7. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described groove has many, and the shape that each bar groove surrounds comprises square, rectangle or circle.

8. high integration wafer fan-out encapsulating structure as claimed in claim 7 is characterized in that: keep same distance between each bar groove.

9. high integration wafer fan-out encapsulating structure as claimed in claim 8 is characterized in that: described groove becomes matrix to arrange.

10. high integration wafer fan-out encapsulating structure as claimed in claim 9 is characterized in that: the cross section of described groove comprises U-shaped, V-type or matrix.

11. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described chip comprises a plurality of different chips.

12. high integration wafer fan-out encapsulating structure as claimed in claim 1; it is characterized in that: described metal interconnect structure comprises: be positioned at metal wiring layer and ball lower metal layer again on the function face of chip and passive device successively; and being positioned at the metal soldered ball on ball lower metal layer surface, described ball lower metal layer and metal also are formed with diaphragm again between wiring layer.

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