CN110120355A - A method of reducing fan-out package warpage - Google Patents
A method of reducing fan-out package warpage Download PDFInfo
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- CN110120355A CN110120355A CN201910446517.6A CN201910446517A CN110120355A CN 110120355 A CN110120355 A CN 110120355A CN 201910446517 A CN201910446517 A CN 201910446517A CN 110120355 A CN110120355 A CN 110120355A
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Abstract
一种降低扇出型封装翘曲的方法，在扇出型封装的注塑步骤后，在注塑材料固化前，在封装体指定位置打出应力释放孔或者应力释放槽阵列。本发明根据上述内容提出一种降低扇出型封装翘曲的方法，通过在封装体指定位置预制应力释放孔或者应力释放槽阵列，从而阻断注塑材料冷却收缩过程中的横向应力传递路径，达到控制内应力，进而减少封装结构翘曲。
A method for reducing the warpage of fan-out packaging. After the injection molding step of the fan-out packaging, before the injection molding material is solidified, a stress relief hole or a stress relief groove array is punched at a designated position of the package body. According to the above content, the present invention proposes a method for reducing the warping of fan-out packages. By prefabricating stress relief holes or stress relief groove arrays at designated positions of the package body, the transverse stress transmission path during the cooling and shrinkage process of the injection molding material is blocked to achieve Internal stress is controlled to reduce package structure warpage.
Description
技术领域technical field
本发明涉及芯片封装技术领域，尤其涉及一种降低扇出型封装翘曲的方法及结构。The invention relates to the technical field of chip packaging, in particular to a method and structure for reducing warping of fan-out packaging.
背景技术Background technique
随着电子产品小型化和集成化的潮流，微电子封装技术的高密度化已在新一代电子产品上逐渐成为主流。为了顺应新一代电子产品的发展，尤其是手机、笔记本等产品的发展，芯片向密度更高、速度更快、尺寸更小、成本更低等方向发展。扇出型方片级封装技术(Fan-out Panel Level Package，FOPLP)的出现，作为扇出型晶圆级封装技术(FanoutWafer Level Package，FOWLP)的升级技术，拥有更广阔的发展前景。与传统的引线键合芯片相比，扇出型封装大大增加芯片的引脚数目，减小了封装尺寸，简化封装步骤，缩短了芯片与载板之间的距离，提高了芯片功能。具有支持10nm以下工艺制程芯片、互连路径短、高集成度、超薄厚度、高可靠性，高散热能力等优势。With the trend of miniaturization and integration of electronic products, the high density of microelectronic packaging technology has gradually become the mainstream in the new generation of electronic products. In order to comply with the development of the new generation of electronic products, especially the development of mobile phones, notebooks and other products, chips are developing in the direction of higher density, faster speed, smaller size and lower cost. The emergence of Fan-out Panel Level Package (FOPLP), as an upgraded technology of Fan-out Wafer Level Package (FOWLP), has a broader development prospect. Compared with traditional wire-bonded chips, fan-out packaging greatly increases the number of chip pins, reduces the size of the package, simplifies the packaging steps, shortens the distance between the chip and the carrier, and improves the function of the chip. It has the advantages of supporting process chips below 10nm, short interconnection path, high integration, ultra-thin thickness, high reliability, and high heat dissipation capacity.
扇出型封装的基本工序为：在载板上覆盖临时键合胶，安装芯片，进行注塑并固化，移除临时键合胶和载板，覆盖介电层(ABF)和再布线层(RDL)。这样的工序也带来了扇出型封装的两大基本问题，即芯片漂移和翘曲行为。在注塑阶段，如果临时键合胶与芯片连接过松，就会造成芯片漂移。如果结合过紧，又会给后续移除临时键合胶和载板的过程带来困难，并且会造成更高内应力与翘曲。在封装过程中，由于塑胶、硅及金属等材料的热胀系数的差别，会造成翘曲和内应力。其中，芯片与注塑材料热膨胀系数的区别使注塑材料冷却过程中产生的翘曲是大板级扇出封装技术中翘曲产生的最主要原因。The basic process of fan-out packaging is: cover the temporary bonding adhesive on the carrier board, install the chip, perform injection molding and curing, remove the temporary bonding adhesive and the carrier board, cover the dielectric layer (ABF) and the rewiring layer (RDL ). Such a process also introduces two fundamental issues with fan-out packaging, namely die drift and warpage behavior. During the injection molding stage, if the temporary bonding glue is too loosely connected to the chip, it will cause the chip to drift. If the bond is too tight, it will make it difficult to remove the temporary bonding adhesive and the carrier plate later, and will cause higher internal stress and warpage. During the packaging process, due to the difference in thermal expansion coefficients of materials such as plastic, silicon, and metal, warpage and internal stress will be caused. Among them, the difference in thermal expansion coefficient between the chip and the injection molding material causes the warping of the injection molding material during the cooling process to be the most important cause of warping in the large board-level fan-out packaging technology.
如何改善翘曲问题成为了当前扇出型封装和高密度集成微电子系统的重要问题，需要发展新型的扇出封装方法与技术。How to improve the warpage problem has become an important issue in current fan-out packaging and high-density integrated microelectronic systems, and it is necessary to develop new fan-out packaging methods and technologies.
发明内容Contents of the invention
本发明的目的在于提出一种降低扇出型封装翘曲的方法，通过在封装体指定位置预制应力释放孔或者应力释放槽阵列，从而阻断注塑材料冷却收缩过程中的横向应力传递路径，达到控制内应力，进而减少封装结构翘曲。。The purpose of the present invention is to propose a method for reducing the warping of fan-out packages, by prefabricating stress relief holes or stress relief groove arrays at designated positions of the package body, thereby blocking the lateral stress transmission path during the cooling and shrinking process of injection molding materials, and achieving Internal stress is controlled to reduce package structure warpage. .
为达此目的，本发明采用以下技术方案：For reaching this purpose, the present invention adopts following technical scheme:
一种降低扇出型封装翘曲的方法，在扇出型封装的注塑步骤后，在注塑材料固化前，在封装体指定位置打出应力释放孔或者应力释放槽阵列。A method for reducing the warpage of fan-out packaging. After the injection molding step of the fan-out packaging, before the injection molding material is solidified, a stress relief hole or a stress relief groove array is punched at a designated position of the package body.
优选的，所述应力释放孔或者应力释放槽的位置设置在芯片或模块的间隔处，即后续的切割位置。Preferably, the position of the stress relief hole or the stress relief groove is set at the interval between chips or modules, that is, the subsequent cutting position.
优选的，所述应力释放孔为是通孔或者盲孔。Preferably, the stress relief hole is a through hole or a blind hole.
优选的，所述应力释放槽为通槽或者浅槽。Preferably, the stress relief groove is a through groove or a shallow groove.
优选的，所述应力释放孔或者应力释放槽通过高能量密度激光加工或共聚焦原理激光加工而成，共聚焦激光加工适用于对封装体内部进行精准定位打孔，激光对单个应力释放孔或应力释放槽的打孔的方式包括一次打孔或者多次打孔。Preferably, the stress relief holes or stress relief grooves are formed by high-energy-density laser processing or confocal laser processing. Confocal laser processing is suitable for precise positioning and drilling of the inside of the package. The way of punching the stress relief groove includes one punching or multiple punching.
优选的，所述扇出型封装的范围是板级或者晶圆级扇出封装。Preferably, the scope of the fan-out packaging is board-level or wafer-level fan-out packaging.
优选的，所述应力释放槽是直槽或者带有弧度的弯槽。Preferably, the stress relief groove is a straight groove or a curved groove with a radian.
优选的，所述应力释放孔或者应力释放槽的分布是对称的阵列式、发散式或者非对称式的图案Preferably, the distribution of the stress relief holes or stress relief grooves is a symmetrical array, divergent or asymmetric pattern
优选的，所述应力释放孔或者应力释放槽的深度范围是在0至100％封装厚度内进行调整的。Preferably, the depth range of the stress relief hole or the stress relief groove is adjusted within 0 to 100% of the package thickness.
优选的，打出应力释放孔或者应力释放槽阵列时是分别在封装体注塑材料一侧和再布线层的一侧进行两面同时打孔或者打槽；Preferably, when the stress relief hole or the stress relief groove array is punched, holes or grooves are simultaneously drilled on both sides of the package injection molding material side and the rewiring layer side respectively;
封装体注塑材料的一侧和再布线层的一侧是不同的图案。The side of the package injection molding material and the side of the redistribution layer have different patterns.
本发明的有益效果：1、通过在注塑材料固化前，在封装体指定位置打出应力释放孔或应力释放槽阵列的方式，实现了改善封装翘曲，减少封装内应力的目的，提高了封装质量与可靠性；2、应力释放孔或者应力释放槽阵列的位置设置在芯片或模块的间隔处，不会对后续的切割和芯片性能造成影响。Beneficial effects of the present invention: 1. By punching stress relief holes or arrays of stress relief grooves at designated positions of the package before the injection molding material is solidified, the purpose of improving package warpage and reducing package internal stress is achieved, and the package quality is improved and reliability; 2. The position of the stress relief hole or the stress relief groove array is set at the interval of the chip or the module, which will not affect the subsequent cutting and chip performance.
附图说明Description of drawings
图1为本发明一种降低扇出型封装翘曲的方法的过程截面结构示意图。FIG. 1 is a schematic diagram of a process cross-sectional structure of a method for reducing warpage of a fan-out package according to the present invention.
图2为使用本发明一种降低扇出型封装翘曲的方法的阵列槽三维构示意图。FIG. 2 is a schematic diagram of a three-dimensional structure of an array groove using a method for reducing warpage of a fan-out package according to the present invention.
图3为使用本发明另一种降低扇出型封装翘曲的方法的制造的十字槽三维结构示意图。FIG. 3 is a schematic diagram of a three-dimensional cross-recessed structure manufactured using another method for reducing the warpage of a fan-out package according to the present invention.
图4为使用本发明另一种降低扇出型封装翘曲的方法的制造的井字槽三维结构示意图。FIG. 4 is a schematic diagram of a three-dimensional structure of a well-tac-toe groove manufactured using another method for reducing the warpage of a fan-out package according to the present invention.
图5为使用本发明另一种降低扇出型封装翘曲的方法的制造的圆孔槽三维结构示意图。FIG. 5 is a schematic diagram of a three-dimensional structure of a round hole slot manufactured using another method for reducing the warpage of a fan-out package according to the present invention.
其中：1-载板2-热释放层3-介电层4-再布线层5-芯片6-注塑材料7-应力释放槽71-应力释放孔8-焊球Among them: 1-carrier 2-heat release layer 3-dielectric layer 4-rewiring layer 5-chip 6-injection material 7-stress relief groove 71-stress relief hole 8-solder ball
具体实施方式Detailed ways
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation methods.
如图1-5所示，一种降低扇出型封装翘曲的方法，在扇出型封装的注塑步骤后，在注塑材料6固化前，在封装体指定位置打出应力释放孔71或者应力释放槽7，达到释放应力，减少翘曲的目的，提高了封装质量与可靠性。As shown in Figure 1-5, a method for reducing the warping of fan-out packages, after the injection molding step of fan-out packages, before the injection molding material 6 is cured, punch out stress relief holes 71 or stress relief The groove 7 achieves the purpose of releasing stress and reducing warpage, and improves packaging quality and reliability.
封装体指定位置，包括在注塑材料6的一侧，或者再布线层4的一侧，或者封装体内部特定位置进行打孔。应力释放孔71或者应力释放槽7在打孔方向上的形态包扩连续孔洞或者一系列非连续孔洞。The specified position of the package includes punching holes on one side of the injection molding material 6, or one side of the rewiring layer 4, or a specific position inside the package. The shape of the stress relief hole 71 or the stress relief groove 7 in the drilling direction includes continuous holes or a series of discontinuous holes.
优选的，所述应力释放孔71或者应力释放槽7的位置设置在芯片5或模块的间隔处，即后续的切割位置，不会对芯片5性能造成影响。Preferably, the position of the stress relief hole 71 or the stress relief groove 7 is set at the interval between the chip 5 or the module, that is, the subsequent cutting position, which will not affect the performance of the chip 5 .
优选的，所述应力释放孔71为是通孔或者盲孔，所述应力释放槽7为通槽或者浅槽，深度的设置取决于扇出封装中芯片5与注塑材料6的几何结构与物理性质。Preferably, the stress relief hole 71 is a through hole or a blind hole, the stress relief groove 7 is a through groove or a shallow groove, and the setting of the depth depends on the geometric structure and physical structure of the chip 5 and the injection molding material 6 in the fan-out package. nature.
优选的，所述应力释放孔71或者应力释放槽7通过高能量密度激光加工，尽量不引入多余的能量与残余应力。Preferably, the stress release hole 71 or the stress release groove 7 is processed by a high energy density laser, so as not to introduce excess energy and residual stress as much as possible.
预制所述应力释放孔71或者应力释放槽7的方法同样可用于其他类似封装条件下的应力释放与减少翘曲。The method of prefabricating the stress relief hole 71 or the stress relief groove 7 can also be used for stress relief and warpage reduction under other similar packaging conditions.
使用所述的一种降低扇出型封装翘曲的方法制造的结构，A structure fabricated using the described method of reducing warpage in a fan-out package,
所述注塑材料6一侧位置设有应力释放孔71或者应力释放槽7。One side of the injection molding material 6 is provided with a stress relief hole 71 or a stress relief groove 7 .
优选的，所述应力释放孔71或者应力释放槽7的位置设置在芯片或模块的间隔处，即后续的切割位置。Preferably, the position of the stress relief hole 71 or the stress relief groove 7 is set at the interval between chips or modules, that is, the subsequent cutting position.
优选的，所述应力释放孔71为是通孔或者盲孔。Preferably, the stress relief hole 71 is a through hole or a blind hole.
优选的，所述应力释放槽7为通槽或者浅槽。Preferably, the stress relief groove 7 is a through groove or a shallow groove.
优选的，所述应力释放孔71或者应力释放槽7通过高能量密度激光加工或共聚焦原理激光加工而成，共聚焦激光加工适用于对封装体内部进行精准定位打孔，激光对单个应力释放孔71或应力释放槽7的打孔的方式包括一次打孔或者多次打孔。Preferably, the stress relief hole 71 or the stress relief groove 7 is formed by high-energy-density laser processing or confocal laser processing. Confocal laser processing is suitable for precisely positioning and drilling the inside of the package, and the laser releases a single stress. The way of punching the hole 71 or the stress relief groove 7 includes one punching or multiple punching.
所述应力释放孔71或者应力释放槽7通过高能量密度激光加工制成。The stress relief holes 71 or stress relief grooves 7 are made by high energy density laser processing.
优选的，所述扇出型封装的范围是板级或者晶圆级扇出封装。Preferably, the scope of the fan-out packaging is board-level or wafer-level fan-out packaging.
优选的，所述应力释放槽7是直槽或者带有弧度的弯槽。Preferably, the stress relief groove 7 is a straight groove or a curved groove with a radian.
优选的，所述应力释放孔71或者应力释放槽7的分布是对称的阵列式、发散式或者非对称式的图案Preferably, the distribution of the stress relief holes 71 or the stress relief grooves 7 is a symmetrical array, divergent or asymmetric pattern
优选的，所述应力释放孔71或者应力释放槽7的深度范围是在0至100％封装厚度内进行调整的。Preferably, the depth range of the stress relief hole 71 or the stress relief groove 7 is adjusted within 0 to 100% of the package thickness.
优选的，打出应力释放孔71或者应力释放槽7阵列时是分别在封装体注塑材料一侧和再布线层的一侧进行两面同时打孔或者打槽；Preferably, when punching the array of stress relief holes 71 or stress relief grooves 7, holes or grooves are simultaneously punched on both sides of the package injection molding material side and the rewiring layer side respectively;
封装体注塑材料的一侧和再布线层的一侧是不同的图案。The side of the package injection molding material and the side of the redistribution layer have different patterns.
应力释放孔71和应力释放槽7的形状、深度、疏密度和图案分布可以自定义；The shape, depth, density and pattern distribution of the stress relief hole 71 and the stress relief groove 7 can be customized;
应力释放孔71和应力释放槽7的密度与排布可以根据具体封装要求进行设计，可以是选择不同疏密和图案分布。The density and arrangement of stress relief holes 71 and stress relief grooves 7 can be designed according to specific packaging requirements, and different density and pattern distribution can be selected.
实施例一Embodiment one
考虑一个面积为320×320mm2的大板级扇出型封装过程，其中单个芯片5的面积为5×5mm2，单个芯片5包含扇出区域的面积为8×8mm2的封装实例。在扇出型封装的注塑工艺后，在注塑材料6固化之前，(此时的结构从下到上依次为载板1、热释放层2、介电层3、再布线层4、芯片5、熔融注塑材料6)，使用激光器在每个芯片5间隔处的注塑材料6背面打出应力释放槽7阵列，其深度穿透注塑材料6层，单个槽长度为6mm，宽度为100微米。在注塑材料6固化后，进行载板1分离(debonding)、沉积凸块下金属层(UBM deposition)、刻蚀(etching)、嵌入球栅网格阵列(BGA mount)等一系列后续封装工艺，形成最终的扇出型封装结构。Consider a large board-level fan-out packaging process with an area of 320×320mm2, in which a single chip 5 has an area of 5×5mm2, and a single chip 5 includes a package example with a fan-out area of 8×8mm2. After the injection molding process of fan-out packaging, before the injection molding material 6 is solidified, (the structure at this time is the carrier board 1, the heat release layer 2, the dielectric layer 3, the rewiring layer 4, the chip 5, Melt the injection molding material 6), use a laser to punch an array of stress relief grooves 7 on the back of the injection molding material 6 at the interval of each chip 5, the depth of which penetrates the 6 layers of injection molding material, the length of a single groove is 6 mm, and the width is 100 microns. After the injection molding material 6 is cured, a series of subsequent packaging processes such as debonding of the substrate 1, UBM deposition, etching, and BGA mount are carried out. Form the final fan-out packaging structure.
实施例二Embodiment two
考虑一个使用die first方法(再布线在注塑过程之后)的面积为120×120mm2的大板级扇出型封装过程，其中单个芯片5的面积为5×5mm2，单个芯片5包含扇出区域的面积为8×8mm2的封装实例。在扇出型封装的注塑工艺后，在注塑材料6固化之前，(此时的结构从下到上依次为载板1、热释放层2、芯片5、熔融注塑材料6)，使用激光器在每3个芯片5的间隔处的注塑材料6背面打出应力释放槽7阵列，其深度穿透注塑材料6层，单个槽长度为20mm，宽度为100微米。在注塑材料6固化后，进行后续的研磨(grinding)、载板1分离(debonding)、图案化钝化(Patterned passivation)、再布线(RDL)、沉积凸块下金属层(UBM deposition)、刻蚀(etching)、嵌入球栅网格阵列(BGA mount)等一系列后续封装工艺，形成最终的扇出型封装结构。Consider a large board-level fan-out packaging process using the die first method (rewiring after the injection molding process) with an area of 120×120mm2, where the area of a single chip 5 is 5×5mm2, and the area of a single chip 5 including the fan-out area It is an example of package of 8×8mm2. After the injection molding process of the fan-out package, before the injection molding material 6 solidifies, (the structure at this time is the carrier plate 1, the heat release layer 2, the chip 5, and the molten injection molding material 6 from bottom to top), use a laser in each An array of stress relief grooves 7 is drilled on the back of the injection molding material 6 at the intervals between the three chips 5 , and its depth penetrates through the 6 layers of injection molding material. The length of a single groove is 20mm and the width is 100 microns. After the injection molding material 6 is solidified, subsequent grinding (grinding), carrier board 1 separation (debonding), patterned passivation (Patterned passivation), rewiring (RDL), deposition of the under bump metal layer (UBM deposition), engraving A series of subsequent packaging processes such as etching, BGA mount, etc., form the final fan-out packaging structure.
实施例三Embodiment Three
考虑一个使用die first方法(再布线在注塑过程之后)的面积为120×120mm2的大板级扇出型封装过程，其中单个芯片5的面积为5×5mm2，单个芯片5包含扇出区域的面积为8×8mm2的封装实例。在扇出型封装的注塑工艺后，在注塑材料6固化之前，(此时的结构从下到上依次为载板1、热释放层2、芯片5、熔融注塑材料6)，使用激光器在每个芯片5的间隔处的注塑材料6背面打出应力释放圆孔槽阵列，其深度穿透注塑材料6层，单个圆孔槽直径为2毫米。在注塑材料6固化后，进行后续的研磨(grinding)、载板1分离(debonding)、图案化钝化(Patterned passivation)、再布线层4(RDL)、沉积凸块下金属层(UBMdeposition)、刻蚀(etching)、嵌入球栅网格阵列(BGA mount)等一系列后续封装工艺，形成最终的扇出型封装结构。Consider a large board-level fan-out packaging process using the die first method (rewiring after the injection molding process) with an area of 120×120mm2, where the area of a single chip 5 is 5×5mm2, and the area of a single chip 5 including the fan-out area It is an example of package of 8×8mm2. After the injection molding process of fan-out packaging, before the injection molding material 6 is solidified, (the structure at this time is the carrier plate 1, the heat release layer 2, the chip 5, and the molten injection molding material 6 from bottom to top), use a laser in each On the back side of the injection molding material 6 at the intervals of each chip 5, an array of stress-releasing round holes is punched out, the depth of which penetrates through 6 layers of injection molding material, and the diameter of a single round hole is 2 mm. After the injection molding material 6 is solidified, subsequent grinding (grinding), substrate 1 separation (debonding), patterned passivation (Patterned passivation), rewiring layer 4 (RDL), deposition of the under bump metal layer (UBMdeposition), A series of subsequent packaging processes such as etching and BGA mount form the final fan-out packaging structure.
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明的保护范围之内。The above describes the technical principles of the present invention in conjunction with specific embodiments. These descriptions are only for explaining the principles of the present invention, and cannot be construed as limiting the protection scope of the present invention in any way. Based on the explanations herein, those skilled in the art can think of other specific implementation modes of the present invention without creative efforts, and these modes will all fall within the protection scope of the present invention.
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明的保护范围之内。The above describes the technical principles of the present invention in conjunction with specific embodiments. These descriptions are only for explaining the principles of the present invention, and cannot be construed as limiting the protection scope of the present invention in any way. Based on the explanations herein, those skilled in the art can think of other specific implementation modes of the present invention without creative efforts, and these modes will all fall within the protection scope of the present invention.
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