CN105140211A - FAN-OUT packaging structure and packaging method thereof - Google Patents
FAN-OUT packaging structure and packaging method thereof Download PDFInfo
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- CN105140211A CN105140211A CN201510413400.XA CN201510413400A CN105140211A CN 105140211 A CN105140211 A CN 105140211A CN 201510413400 A CN201510413400 A CN 201510413400A CN 105140211 A CN105140211 A CN 105140211A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004033 plastic Substances 0.000 claims abstract description 12
- 229920003023 plastic Polymers 0.000 claims abstract description 12
- 239000003292 glue Substances 0.000 claims description 58
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 29
- 238000012856 packing Methods 0.000 claims description 22
- 238000005520 cutting process Methods 0.000 claims description 20
- 239000011521 glass Substances 0.000 claims description 18
- 239000011265 semifinished product Substances 0.000 claims description 18
- 230000002378 acidificating effect Effects 0.000 claims description 15
- 239000005011 phenolic resin Substances 0.000 claims description 15
- 229920001568 phenolic resin Polymers 0.000 claims description 15
- 239000000741 silica gel Substances 0.000 claims description 15
- 229910002027 silica gel Inorganic materials 0.000 claims description 15
- 238000005538 encapsulation Methods 0.000 claims description 12
- 239000003822 epoxy resin Substances 0.000 claims description 12
- 229920000647 polyepoxide Polymers 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000007493 shaping process Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 239000011135 tin Substances 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 238000001746 injection moulding Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 229910010293 ceramic material Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 229910052809 inorganic oxide Inorganic materials 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 3
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 238000012360 testing method Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 238000003466 welding Methods 0.000 description 4
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000000246 remedial effect Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a FAN-OUT packaging structure and a packaging method thereof. The packaging structure is characterized in that the upper surface of a dielectric layer is provided with a medium layer, the upper surface of the medium layer is provided with a plastic-sealed body, the medium layer is internally provided with arranged wires, upper end parts of the arranged wires are provided with protruding points, the plastic-sealed body is internally provided with inverted chips, the chips are connected with the protruding points, lower end parts of the arranged wires are connected with welded balls, and the lower end parts of the welded balls are exposed from the dielectric layer. According to the invention, complex TSV and wafer thinning processes are omitted, and a low-cost high-density multi-chip integration scheme is provided; the x/y/z packaging size is reduced; and a wafer level electric test is performed after chip mounting before plastic packaging, and once the mounting process is discovered to be a failure, the operation can be repeated, so that the yield rate of the final products is improved.
Description
Technical field
The invention discloses the encapsulating structure of a kind of FAN-OUT, the invention also discloses the method for packing of the encapsulating structure of a kind of FAN-OUT, the invention belongs to technical field of semiconductor encapsulation.
Background technology
2.5D is integrated, and can to realize overall dimension little, at a high speed and low-power consumption multi-chip SiP.But current technique often needs to be TSV on silicon, RDL wiring and fine pith salient point, then spill TSV at wafer rear and complete salient point, by flip chip bonding in 2.5D keyset front the integrated multi-chip with high I/O density, at the 2.5D keyset back side and substrate interconnect, realize finally by SMT and PCB interconnection.TSV and wafer reduction process are complicated and expensive.Si keyset can increase Z-direction thickness simultaneously, is unfavorable for requirement more and more thinner at present.
Summary of the invention
An object of the present invention overcomes the deficiencies in the prior art, provide a kind of thickness little, can carry out fitting with the chip of other functions and obtain the encapsulating structure of the FAN-OUT of three-dimensional POP stacked structure.
Another object of the present invention is to provide a kind of problem that the integrated Z-direction of 2.5D multi-chip thickeies and multi-chip integrated x/y direction on substrate of can solving and increases and the method for packing of encapsulating structure by a kind of FAN-OUT of the problem of substrate wiring density restriction.
According to technical scheme provided by the invention, the encapsulating structure of described a kind of FAN-OUT, dielectric layer is provided with at the upper surface of dielectric layer, be provided with plastic-sealed body at dielectric layer upper surface, in dielectric layer, be provided with wiring, be provided with salient point in the upper end of wiring, the chip of upside-down mounting is provided with in plastic-sealed body, chip is connected with salient point, and be connected with soldered ball in the bottom of wiring, described dielectric layer is exposed in the bottom of soldered ball.
The method for packing of the encapsulating structure of a kind of FAN-OUT of the present invention comprises the following steps:
A, get substrate, make last layer bonding glue at the upper surface of substrate;
B, make one deck dielectric layer at the upper surface of bonding glue, in dielectric layer, make wiring, deposit salient point in the upper end of wiring;
C, on salient point chip on flip chip bonding, obtain packaging semi-finished product;
D, output cutting groove at the upper surface of packaging semi-finished product, the bottom land of cutting groove is positioned at the upper surface of bonding glue or the medium position of bonding glue;
E, to carry out plastic packaging at the upper surface of packaging semi-finished product shaping, obtains plastic-sealed body, complete the protection to chip by plastic-sealed body;
F, to be irradiated by laser or infrared heating makes bonding glue lose efficacy, substrate is removed, cleans remaining bonding glue, make dielectric layer at the lower surface of dielectric layer and make soldered ball, obtain encapsulation overall;
G, by encapsulation entirety cut along cutting groove position, obtain single FAN-OUT chip, method for packing terminates.
Described substrate is naked Silicon Wafer, polymethyl methacrylate, unorganic glass thin slice, resin flake, wafer from semiconducting material, oxide crystal thin slice, ceramic sheet, sheet metal, organic plastics thin slice, inorganic oxide platelets or ceramic material thin slice, and the thickness of substrate is 50um ~ 500um.
Described bonding glue is epoxy resin, organic silica gel, acidic glass glue or phenolic resins, and gluing mode is coating, spraying, pad pasting or injection moulding, and the thickness of bonding glue is 10nm ~ 100um.
The material of described dielectric layer is silica, silicon nitride, silicon oxynitride, organic silica gel, acidic glass glue or phenolic resins, and the thickness of dielectric layer is 50nm ~ 10um.
The material of described salient point is gold, copper, nickel, tin or palladium.
Described cutting groove is inverted trapezoidal.
The material of described plastic-sealed body is epoxy resin, organic silica gel, acidic glass glue or phenolic resins, and the thickness of plastic-sealed body is 100um ~ 1000um.
The material of described dielectric layer is epoxy resin, organic silica gel, acidic glass glue, phenolic resins, silicon nitride, silica or silicon oxynitride, and the thickness of dielectric layer is 1nm ~ 10um.
The present invention has the following advantages:
1) this encapsulating structure eliminates TSV and the wafer reduction process of complex process, provides a kind of low cost middle-high density multi-chip Integrated Solution;
2) x/y/z package dimension is reduced;
3) before plastic packaging, carry out the testing electrical property of wafer level after paster, once find that attaching process lost efficacy, can heavy industry operation be carried out, improve the yield of final products.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below.Apparently, the accompanying drawing in the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of substrate in the present invention.
Fig. 2 is the structural representation of the packaging body that in the present invention, step a obtains.
Fig. 3 is the structural representation of the packaging body that in the present invention, step b obtains.
Fig. 4 is the structural representation of the packaging body that in the present invention, step c obtains.
Fig. 5 is the structural representation of the packaging body that in the present invention, steps d obtains.
Fig. 6 is the structural representation of the packaging body that in the present invention, step e obtains.
Fig. 7 is the structural representation of the packaging body that in the present invention, step f obtains.
Fig. 8 is the structural representation of the packaging body that in the present invention, step g obtains.
Embodiment
Below in conjunction with specific embodiment, the invention will be further described.
Describe the present invention below with reference to embodiment shown in the drawings.But these execution modes do not limit the present invention, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection scope of the present invention.
In addition, label or the sign of repetition may be used in various embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.
The label had about step mentioned in the embodiments of the present invention, is only used to the convenience described, and does not have the contact of sequencing in fact.Different step in each embodiment, can carry out the combination of different sequencing, realize goal of the invention of the present invention.
Embodiment 1
The method for packing of the encapsulating structure of a kind of FAN-OUT of the present invention comprises the following steps:
A, get substrate 1, made the bonding glue 2 of last layer epoxy resin material by coating method at the upper surface of substrate 1, as shown in Figure 2;
B, make the dielectric layer 3 of one deck silica material at the upper surface of bonding glue 2, the thickness of dielectric layer 3 is 50nm, makes wiring 4 in dielectric layer 3, deposits the salient point 5 that material is gold, as shown in Figure 3 in the upper end of wiring 4;
C, on salient point 5 chip 6 on flip chip bonding, obtain packaging semi-finished product, as shown in Figure 4;
D, output the cutting groove 7 of inverted trapezoidal at the upper surface of packaging semi-finished product, the bottom land of cutting groove 7 is positioned at the upper surface of bonding glue 2 or the medium position of bonding glue 2, as shown in Figure 5;
E, to use epoxy resin to carry out plastic packaging at the upper surface of packaging semi-finished product shaping, and obtain plastic-sealed body 8, the thickness of plastic-sealed body 8 is 100um, completes the protection to chip 6, as shown in Figure 6 by plastic-sealed body 8;
F, by infrared heating, bonding glue 2 was lost efficacy, substrate 1 is removed, clean remaining bonding glue 2, make at the lower surface of dielectric layer 3 dielectric layer 9 that thickness is the epoxy resin material of 1nm and make soldered ball 10, obtaining encapsulation overall, as shown in Figure 7;
G, by encapsulation entirety cut along cutting groove 7 position, obtain single FAN-OUT chip, method for packing terminates, as shown in Figure 8.
Embodiment 2
The method for packing of the encapsulating structure of a kind of FAN-OUT of the present invention comprises the following steps:
A, get substrate 1, made the bonding glue 2 of last layer organic silica gel material by spraying method at the upper surface of substrate 1, as shown in Figure 2;
B, make the dielectric layer 3 of one deck silicon nitride material at the upper surface of bonding glue 2, the thickness of dielectric layer 3 is 10um, makes wiring 4 in dielectric layer 3, and depositing material in the upper end of wiring 4 is copper bump 5, as shown in Figure 3;
C, on salient point 5 chip 6 on flip chip bonding, obtain packaging semi-finished product, as shown in Figure 4;
D, output the cutting groove 7 of inverted trapezoidal at the upper surface of packaging semi-finished product, the bottom land of cutting groove 7 is positioned at the upper surface of bonding glue 2 or the medium position of bonding glue 2, as shown in Figure 5;
E, to use organic silica gel to carry out plastic packaging at the upper surface of packaging semi-finished product shaping, and obtain plastic-sealed body 8, the thickness of plastic-sealed body 8 is 1000um, completes the protection to chip 6, as shown in Figure 6 by plastic-sealed body 8;
F, by infrared heating, bonding glue 2 was lost efficacy, substrate 1 is removed, clean remaining bonding glue 2, make at the lower surface of dielectric layer 3 dielectric layer 9 that thickness is the organic silica gel material of 10um and make soldered ball 10, obtaining encapsulation overall, as shown in Figure 7;
G, by encapsulation entirety cut along cutting groove 7 position, obtain single FAN-OUT chip, method for packing terminates, as shown in Figure 8.
Embodiment 3
The method for packing of the encapsulating structure of a kind of FAN-OUT of the present invention comprises the following steps:
A, get substrate 1, made the bonding glue 2 of last layer acidic glass glue material by pad pasting mode at the upper surface of substrate 1, as shown in Figure 2;
B, make the dielectric layer 3 of one deck acidic glass glue material at the upper surface of bonding glue 2, the thickness of dielectric layer 3 is 500nm, makes wiring 4 in dielectric layer 3, deposits the salient point 5 that material is nickel, as shown in Figure 3 in the upper end of wiring 4;
C, on salient point 5 chip 6 on flip chip bonding, obtain packaging semi-finished product, as shown in Figure 4;
D, output the cutting groove 7 of inverted trapezoidal at the upper surface of packaging semi-finished product, the bottom land of cutting groove 7 is positioned at the upper surface of bonding glue 2 or the medium position of bonding glue 2, as shown in Figure 5;
E, to use acidic glass glue to carry out plastic packaging at the upper surface of packaging semi-finished product shaping, and obtain plastic-sealed body 8, the thickness of plastic-sealed body 8 is 400um, completes the protection to chip 6, as shown in Figure 6 by plastic-sealed body 8;
F, to be irradiated by laser bonding glue 2 was lost efficacy, substrate 1 is removed, cleans remaining bonding glue 2, make at the lower surface of dielectric layer 3 dielectric layer 9 that thickness is the silicon nitride material of 100nm and make soldered ball 10, obtaining encapsulation overall, as shown in Figure 7;
G, by encapsulation entirety cut along cutting groove 7 position, obtain single FAN-OUT chip, method for packing terminates, as shown in Figure 8.
Embodiment 4
The method for packing of the encapsulating structure of a kind of FAN-OUT of the present invention comprises the following steps:
A, get substrate 1, made the bonding glue 2 of last layer phenolic resins material by injection molding manner at the upper surface of substrate 1, as shown in Figure 2;
B, make the dielectric layer 3 of one deck phenolic resins material at the upper surface of bonding glue 2, the thickness of dielectric layer 3 is 5um, makes wiring 4 in dielectric layer 3, deposits the salient point 5 that material is tin, as shown in Figure 3 in the upper end of wiring 4;
C, on salient point 5 chip 6 on flip chip bonding, obtain packaging semi-finished product, as shown in Figure 4;
D, output the cutting groove 7 of inverted trapezoidal at the upper surface of packaging semi-finished product, the bottom land of cutting groove 7 is positioned at the upper surface of bonding glue 2 or the medium position of bonding glue 2, as shown in Figure 5;
E, to use phenolic resins to carry out plastic packaging at the upper surface of packaging semi-finished product shaping, and obtain plastic-sealed body 8, the thickness of plastic-sealed body 8 is 700um, completes the protection to chip 6, as shown in Figure 6 by plastic-sealed body 8;
F, to be irradiated by laser bonding glue 2 was lost efficacy, substrate 1 is removed, cleans remaining bonding glue 2, make at the lower surface of dielectric layer 3 dielectric layer 9 that thickness is the silicon oxynitride material of 1um and make soldered ball 10, obtaining encapsulation overall, as shown in Figure 7;
G, by encapsulation entirety cut along cutting groove 7 position, obtain single FAN-OUT chip, method for packing terminates, as shown in Figure 8.
The encapsulating structure of a kind of FAN-OUT of the present invention, dielectric layer 3 is provided with at the upper surface of dielectric layer 9, plastic-sealed body 8 is provided with at dielectric layer 3 upper surface, wiring 4 is provided with in dielectric layer 3, be provided with salient point 5 in the upper end of wiring 4, in plastic-sealed body 8, be provided with the chip 6 of upside-down mounting, chip 6 is connected with salient point 5, be connected with soldered ball 10 in the bottom of wiring 4, described dielectric layer 9 is exposed in the bottom of soldered ball 10.
In the present invention, substrate 1 can be naked Silicon Wafer, polymethyl methacrylate thin slice, unorganic glass thin slice, resin flake, wafer from semiconducting material, oxide crystal thin slice, ceramic sheet, sheet metal, organic plastics thin slice, inorganic oxide platelets or ceramic material thin slice etc.; Can be transparent also can be opaque, can be the thin slice of one deck one matter composition, also can be the thin slice of multilayer same substance or different material composition; And the thickness of described substrate 1 is 50um ~ 500um.
Described bonding glue 2 is epoxy resin, organic silica gel, acidic glass glue or phenolic resins, and gluing mode is coating, spraying, pad pasting or injection moulding, and can carry out viscosity operation by laser or infrared heating after this adhesive curing, and the thickness of described bonding glue 2 is 10nm ~ 100um.
The material of described dielectric layer 3 is silica, silicon nitride, silicon oxynitride, organic silica gel, acidic glass glue or phenolic resins; The thickness of described dielectric layer 3 is 50nm ~ 10um.
The material of described salient point 5 is gold, copper, nickel, tin or palladium.
The material of described plastic-sealed body 8 is epoxy resin, organic silica gel, acidic glass glue or phenolic resins, and the thickness of plastic-sealed body 8 is 100um ~ 1000um.
Described dielectric layer 9 is epoxy resin, organic silica gel, acidic glass glue, phenolic resins, silicon nitride, silica or silicon oxynitride, and the thickness of dielectric layer is 20 ~ 100 μm.
In step c, this chip 6 can be identical also can be different; Wafer scale testing electrical property is carried out to the wafer welding chip, the wafer four welding chip is with can test electrical PAD or tin ball exposes, can be used for connecting power supply and judge welding quality, and the chip structure that butt welding connects carries out functional test, it is qualified to judge whether; If judgement weld failure, then answer heavy industry Flip Chip Bond Technique, or carry out other remedial measures.
In order to ensure the planarization in plastic packaging face, grinding technics can also be carried out for the upper surface of the plastic-sealed body 8 after solidification, or depositing the good material of other mobility, making its surfacing.
In step f, to be irradiated by laser or the technique such as infrared heating makes substrate 1 lose efficacy with the bonding glue 2 in the middle of dielectric layer 2, make both be separated.
Those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, can realize the present invention in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (9)
1. the encapsulating structure of a FAN-OUT, it is characterized in that: be provided with dielectric layer (3) at the upper surface of dielectric layer (9), plastic-sealed body (8) is provided with at dielectric layer (3) upper surface, wiring (4) is provided with in dielectric layer (3), salient point (5) is provided with in the upper end of wiring (4), the chip (6) of upside-down mounting is provided with in plastic-sealed body (8), chip (6) is connected with salient point (5), be connected with soldered ball (10) in the bottom of wiring (4), described dielectric layer (9) is exposed in the bottom of soldered ball (10).
2. a method for packing for the encapsulating structure of FAN-OUT, is characterized in that the method comprises the following steps:
A, get substrate (1), make last layer bonding glue (2) at the upper surface of substrate (1);
B, make one deck dielectric layer (3) at the upper surface of bonding glue (2), in dielectric layer (3), make wiring (4), deposit salient point (5) in the upper end of wiring (4);
C, on the upper flip chip bonding of salient point (5) chip (6), obtain packaging semi-finished product;
D, output cutting groove (7) at the upper surface of packaging semi-finished product, the bottom land of cutting groove (7) is positioned at the upper surface of bonding glue (2) or the medium position of bonding glue (2);
E, to carry out plastic packaging at the upper surface of packaging semi-finished product shaping, obtains plastic-sealed body (8), complete the protection to chip (6) by plastic-sealed body (8);
F, to be irradiated by laser or infrared heating makes bonding glue (2) lose efficacy, substrate (1) is removed, cleans remaining bonding glue (2), make dielectric layer (9) at the lower surface of dielectric layer (3) and make soldered ball (10), obtain encapsulation overall;
G, will encapsulate and overall to cut along cutting groove (7) position, obtain single FAN-OUT chip, method for packing terminates.
3. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, it is characterized in that: described substrate (1) is naked Silicon Wafer, polymethyl methacrylate, unorganic glass thin slice, resin flake, wafer from semiconducting material, oxide crystal thin slice, ceramic sheet, sheet metal, organic plastics thin slice, inorganic oxide platelets or ceramic material thin slice, and the thickness of substrate (1) is 50um ~ 500um.
4. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, it is characterized in that: described bonding glue (2) is epoxy resin, organic silica gel, acidic glass glue or phenolic resins, and gluing mode is coating, spraying, pad pasting or injection moulding, and the thickness of bonding glue (2) is 10nm ~ 100um.
5. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, it is characterized in that: the material of described dielectric layer (3) is silica, silicon nitride, silicon oxynitride, organic silica gel, acidic glass glue or phenolic resins, and the thickness of dielectric layer (3) is 50nm ~ 10um.
6. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, is characterized in that: the material of described salient point (5) is gold, copper, nickel, tin or palladium.
7. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, is characterized in that: described cutting groove (7) is inverted trapezoidal.
8. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, it is characterized in that: the material of described plastic-sealed body (8) is epoxy resin, organic silica gel, acidic glass glue or phenolic resins, and the thickness of plastic-sealed body (8) is 100um ~ 1000um.
9. the method for packing of the encapsulating structure of a kind of FAN-OUT according to claim 2, it is characterized in that: the material of described dielectric layer (9) is epoxy resin, organic silica gel, acidic glass glue, phenolic resins, silicon nitride, silica or silicon oxynitride, and the thickness of dielectric layer (9) is 1nm ~ 10um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510413400.XA CN105140211A (en) | 2015-07-14 | 2015-07-14 | FAN-OUT packaging structure and packaging method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510413400.XA CN105140211A (en) | 2015-07-14 | 2015-07-14 | FAN-OUT packaging structure and packaging method thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129037A (en) * | 2016-08-10 | 2016-11-16 | 武汉寻泉科技有限公司 | Multi-project wafer fast packing plate and preparation method thereof, method for packing |
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