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CN102075208B - Radio frequency front-end with low power consumption - Google Patents

Radio frequency front-end with low power consumption Download PDF

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Publication number
CN102075208B
CN102075208B CN201010620294XA CN201010620294A CN102075208B CN 102075208 B CN102075208 B CN 102075208B CN 201010620294X A CN201010620294X A CN 201010620294XA CN 201010620294 A CN201010620294 A CN 201010620294A CN 102075208 B CN102075208 B CN 102075208B
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transistor
inductance
transistorized
connects
drain
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CN102075208A (en
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吴建辉
江平
陈超
李红
张萌
赵亮
孙杰
时龙兴
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Southeast University Wuxi Branch
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Southeast University
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Abstract

The invention discloses a radio-frequency front-end with low power consumption which comprises a phase-locked loop (PLL), a low-noise amplifier and a power amplifier, wherein the PLL comprises a voltage-controlled oscillator and further comprises a mode-switching controller, the two output ends of the mode-switching controller are respectively connected with the input ends of the power amplifier and the low-noise amplifier; the low-noise amplifier and the power amplifier are respectively connected with the voltage-controlled oscillator through a first loading network and a second loading network; and both the mode-switching controller and the voltage-controlled oscillator are connected with the power source end. By using current-reuse techniques in the radio front-end provided by the invention, a total power consumption of the three modules comprising the low-noise amplifier, the voltage-controlled oscillator and the power amplifier is significantly reduced, and meanwhile electric current used by each module is not reduced, so that circuit performance has no obvious degeneration. Unused modules can be shut off after the mode-switching controller is introduced, so as to further reduce the power consumption of the system.

Description

A kind of low-power consumption radio-frequency front-end
Technical field
What the present invention relates to is a kind of radio-frequency front-end, and what be specifically related to is a kind of low-power consumption radio-frequency front-end.
Background technology
In wireless sense network, ZigBee and GPS, low-power consumption receive-transmit system (module) design is main target.One of method that realizes low power dissipation design is that metal-oxide-semiconductor is biased in sub-threshold region.But there are some problems in the method, and is generally all very big such as the transistorized size in sub-threshold region work, limited transistorized maximum operating frequency, that is to say that the operating rate of circuit is lower, and common this method is not suitable for using in RF application.Another method is the size that reduces each tree transistors, makes to obtain less operating current, and this will cause bigger mismatch and flicker noise.More than discussion shows, in RF application, makes transistor work in sub-threshold region, obtains less operating current or reduces transistor size, obtains less operating current and all has certain problem.
Summary of the invention
At the deficiency that exists on the prior art, the present invention seeks to be to provide a kind of radio-frequency front-end of low-power consumption, multiplexing one road electric current uses for a plurality of modules, enough guarantee its performance for each blocks current, and under the prerequisite of not serious degrade performance, realized low-power consumption for a plurality of modules.
To achieve these goals, the present invention realizes by the following technical solutions:
The present invention includes phase-locked loop, low noise amplifier and power amplifier, phase-locked loop comprises voltage controlled oscillator, the present invention also comprises mode switching controller, two outputs of mode switching controller connect the input of power amplifier and low noise amplifier respectively, low noise amplifier and power amplifier are connected with voltage controlled oscillator with second laod network by first laod network respectively, and mode switching controller and voltage controlled oscillator all connect power end; Mode switching controller comprises transistor, and wherein, the 17 transistorized grid connects the tenth transistorized grid, its public termination control logic input signal, and source electrode connects power end, and drain electrode connects the tenth transistor drain; The tenth transistorized source ground, drain electrode connects the 18 transistorized grid and the 11 transistorized grid; The 18 transistorized source electrode connects power end, and drain electrode connects the 11 transistor drain, and grid connects the 14 transistorized grid and the 15 transistorized grid; The 11 transistor drain connects the 13 transistorized grid and the 16 transistorized grid, source ground; The 14 transistor drain connects an end of zero resistance and an end of first resistance, source ground, the other end of the other end of zero resistance and first resistance respectively with low noise amplifier in the 4th transistorized grid be connected with the 5th transistorized grid; The 13 transistorized source electrode connects the 14 transistor drain, and drain electrode connects the grid of the tenth two-transistor; The drain electrode of the tenth two-transistor connects reference current, grid and drain electrode short circuit, source ground; The 16 transistorized source ground, drain electrode connects an end of second resistance and an end of the 3rd resistance, the other end of the other end of second resistance and the 3rd resistance respectively with power amplifier in the 6th transistorized grid be connected with the 7th transistorized grid; The 15 transistorized source electrode connects the 16 transistor drain, and drain electrode connects the drain electrode of the tenth two-transistor.These three modules of voltage controlled oscillator of the present invention, power amplifier and low noise amplifier share one road electric current, greatly reduce the total power consumption of circuit.
Above-mentioned low noise amplifier also comprises the 3rd inductance, the 4th inductance, first electric capacity, the 5th inductance of connecting with first electric capacity, one end, second electric capacity, the 6th inductance, transistor seconds and the 3rd transistor of connecting with second electric capacity, one end; The other end of the 5th inductance and the 6th inductance connects the 4th transistor and the 5th transistorized grid respectively, the 4th transistor and the 5th transistorized source electrode connect an end of the 3rd inductance and the 4th inductance respectively, the equal ground connection of the other end of the 3rd inductance and the 4th inductance, the 4th transistor and the 5th transistor drain connect transistor seconds and the 3rd transistorized source electrode respectively, transistor seconds and the 3rd transistorized grid all connect first bias voltage, transistor seconds and the 3rd transistor drain connect an end of first inductance in first laod network and an end of second inductance in second laod network respectively, and the other end of the other end of first inductance and second inductance connects the source electrode of the 0th transistor and the first transistor in the voltage controlled oscillator respectively.
Above-mentioned power amplifier also comprises the 3rd electric capacity, the 4th electric capacity, the 8th transistor and the 9th transistor; One end of the 3rd electric capacity and an end of the 4th electric capacity connect the 6th transistor and the 7th transistorized grid respectively, the 6th transistor and the 7th transistorized source grounding, the 6th transistor and the 7th transistor drain connect the 8th transistor and the 9th transistorized source electrode respectively, the 8th transistor and the 9th transistorized grid all connect second bias voltage, and the 8th transistor and the 9th transistor drain connect an end of first inductance in first laod network and an end of second inductance in second laod network respectively.
Above-mentioned voltage controlled oscillator also comprises resonant network; Resonant network comprises zero inductance, zero capacitance and variable capacitance, and the three is parallel with one another, and zero inductance has three ports, and except two ports in parallel with zero capacitance, the 3rd port connects power end; The 0th transistorized grid connects the drain electrode of the first transistor, a pole plate of its public termination variable capacitance; The grid of the first transistor connects the 0th transistor drain, another pole plate of its public termination variable capacitance.
The source electrode of the above-mentioned the 0th transistorized source electrode and the first transistor links to each other by the 7th electric capacity, the source electrode of the 0th transistorized source electrode and the first transistor also is connected with an end of the 5th electric capacity and an end of the 6th electric capacity respectively, the equal ground connection of the other end of the other end of the 5th electric capacity and the 6th electric capacity.
Above-mentioned first laod network also comprises first capacitor array that is connected with first inductance; Second laod network (2b) also comprises second capacitor array that is connected with second inductance; First capacitor array and second capacitor array include binary weights capacitor C [1], C[2] ... C[n], one termination, the first control word transistor drain of capacitor C [1], the transistorized drain terminal of one termination, second control word of capacitor C [2], by that analogy, one termination n control word transistor drain of capacitor C [n], the transistorized grid of all control words meets control word K[1 respectively], K[2] ... K[n], the transistorized source grounding of all control words; Capacitor C in first capacitor array [1], C[2] ... C[n] the other end all be connected with an end of first inductance, connect the drain electrode of transistor seconds simultaneously; Capacitor C in second capacitor array [1], C[2] ... C[n] the other end all be connected with an end of second inductance, connect the 3rd transistor drain simultaneously.Adopt first capacitor array and second capacitor array, make under reception and emission mode, all can realize the digital control of load, can revise the difference of the parasitic capacitance that different annexations cause under the different working modes, simultaneously also can compensate for process, the capacitance deviation that causes of temperature, voltage.
The invention enables the total power consumption of these three modules of low noise amplifier, voltage controlled oscillator and power amplifier to reduce greatly, and the electric current that each module is used does not reduce, so the performance of circuit does not have tangible deterioration; The module shuts down that does not need to use further can be reduced system power dissipation after introducing mode switching controller; Use capacitor array to make the load of low noise amplifier and power amplifier to adjust by numerically controlled method, can revise the difference of the parasitic capacitance that different annexations cause under the different working modes, simultaneously also can compensate for process, the capacitance deviation that causes of temperature, voltage; Introduce electric capacity the 5th electric capacity and the 6th electric capacity at voltage controlled oscillator cross-couplings pipe source electrode, can suppress the variation of output common mode level effectively, it is remained within the suitable scope.
Description of drawings
Describe the present invention in detail below in conjunction with the drawings and specific embodiments:
Fig. 1 is system diagram of the present invention;
Fig. 2 is core circuit block diagram of the present invention;
Fig. 3 is core circuit schematic diagram of the present invention;
Relevant output waveform figure when Fig. 4 works in receiving mode for the present invention (A is low noise amplifier input waveform among the figure, and B is the voltage controlled oscillator output waveform, and C is the low noise amplifier output waveform).
Each sequence number is represented respectively among the figure:
The 1-voltage controlled oscillator; 2a-first laod network; 2b-second laod network; The 3-power amplifier; The 4-low noise amplifier; The 5-mode switching controller; Mod-control logic input signal; The BiasL-first control logic output signal; The BiasP-second control logic output signal; The Ibias-reference current; First difference output end of vco1-voltage controlled oscillator; Second difference output end of vco2-voltage controlled oscillator; First differential input end of LNAin1-low noise amplifier; Second differential input end of LNAin2-low noise amplifier; First differential input end of PAin1-power amplifier; Second differential input end of PAin2-power amplifier; The out1-first public difference output end; The out2-second public difference output end; Fout-intermediate frequency output signal; Fin-intermediate frequency input signal; V1-first bias voltage; V2-second bias voltage; The M1-the first transistor; The M2-transistor seconds; M3-the 3rd transistor; M4-the 4th transistor; M5-the 5th transistor; M6-the 6th transistor; M7-the 7th transistor; M8-the 8th transistor; M9-the 9th transistor; M10-the tenth transistor; M11-the 11 transistor; M12-the tenth two-transistor; M13-the 13 transistor; M14-the 14 transistor; M15-the 15 transistor; M16-the 16 transistor; P0-the 17 transistor; P1-the 18 transistor; The R0-zero resistance; R1-first resistance; R2-second resistance; R3-the 3rd resistance; The L0-zero inductance; L1-first inductance; L2-second inductance; L3-the 3rd inductance; L4-the 4th inductance; L5-the 5th inductance; L6-the 6th inductance; The C0-zero capacitance; C1-first electric capacity; C2-second electric capacity; C3-the 3rd electric capacity; C4-the 4th electric capacity; C5-the 5th electric capacity; C6-the 6th electric capacity; The Cv-variable capacitance; Cc-the 7th electric capacity; CO1-the 8th electric capacity; CO2-the 9th electric capacity; K[1], K[2] ... K[n]-control word; C[1], C[2] ... C[n]-binary weights electric capacity.
Embodiment
For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with embodiment, further set forth the present invention.
Referring to Fig. 1 and Fig. 2, the present invention includes phase-locked loop 6, low noise amplifier 4, power amplifier 3 and mode switching controller 5, phase-locked loop 6 comprises voltage controlled oscillator 1.The electric current of this voltage controlled oscillator 1 is multiplexing with low noise amplifier 4 and power amplifier 3.Down-conversion mixer 7b input produces intermediate frequency output signal fout from the local oscillation signal that output radiofrequency signal and the phase-locked loop 6 of low noise amplifier 4 provides; Upper frequency mixer 7a input comes from the local oscillation signal that intermediate frequency input signal fin and phase-locked loop 6 provide, and output is as the input signal of power amplifier 3.
Two outputs of mode switching controller 5 connect power amplifier 3 and low noise amplifier 4 respectively, power amplifier 3 and low noise amplifier 4 are connected with voltage controlled oscillator 1 with the second laod network 2b by the first laod network 2a respectively, and mode switching controller 5 and voltage controlled oscillator 1 all connect power end.Power end is voltage controlled oscillator 1 and mode switching controller 5 power supplies, and power amplifier 3 and low noise amplifier 4 be the electric current of shared voltage controlled oscillator 1 then.
The present invention adopts the stacked current multiplexing technology of multimode, be controlled to be the voltage controlled oscillator 1 of stacked connection and low noise amplifier 4 or voltage controlled oscillator 1 and power amplifier 3 by mode switching controller 5 bias current is provided, make power amplifier 3 and low noise amplifier 4 selectivity work.When being operated in emission mode, voltage controlled oscillator 1 and 3 stacked connections of power amplifier, power amplifier 3 shares the tail current of voltage controlled oscillator 1, and low noise amplifier 4 is not worked; And when working in receiving mode, mode switching controller 5 will cut off the stacked vias of voltage controlled oscillator 1 and power amplifier 3, the stacked vias of the voltage controlled oscillator 1 of conducting simultaneously and low noise amplifier 4, low noise amplifier 4 shares the tail current of voltage controlled oscillators 1, and power amplifier 3 is not worked.Voltage controlled oscillator 1 of the present invention, power amplifier 3 and low noise amplifier 4 these three modules share one road electric current, greatly reduce the total power consumption of circuit.
Low noise amplifier 4 and power amplifier 3 share the first laod network 2a and the second laod network 2b respectively.The first laod network 2a comprises first inductance L 1 and first capacitor array; The second laod network 2b comprises second inductance L 2 and second capacitor array.First capacitor array and second capacitor array are by binary weights capacitor C [1], C[2] ... C[n] and the switch composition, switch drain meets binary weights capacitor C [1], C[2 respectively] ... C[n] bottom crown, grid meets control word K[1 respectively], K[2] ... K[n], the equal ground connection of switch source.
The first laod network 2a and the second laod network 2b are respectively by changing the control word K[1 of first capacitor array and second capacitor array], K[2] ... K[n], can the different electric capacity of gating, with first inductance L 1 and second inductance L, 2 resonance.Adopt the benefit of first capacitor array and second capacitor array to be: under reception and emission mode, all can realize the digital control of load, can revise the difference of the parasitic capacitance that different annexations cause under the different working modes, simultaneously also can compensate for process, the capacitance deviation that causes of temperature, voltage.
Referring to Fig. 3, mode switching controller 5 of the present invention comprises transistor, wherein, the grid of the 17 transistor M17 connects the grid of the tenth transistor M10, its public termination control logic input signal Mod, source electrode connects power end, and drain electrode connects the drain electrode of the tenth transistor M10; The source ground of the tenth transistor M10, drain electrode connects the grid of the 18 transistor M18 and the grid of the 11 transistor M11; The source electrode of the 18 transistor M18 connects power end, and drain electrode connects the drain electrode of the 11 transistor M11, and grid connects the grid of the 14 transistor M14 and the grid of the 15 transistor M15; The drain electrode of the 11 transistor M11 connects the grid of the 13 transistor M13 and the grid of the 16 transistor M16, source ground; The drain electrode of the 14 transistor M14 connects low noise amplifier 4 by zero resistance R0 and first resistance R 1, source ground; The source electrode of the 13 transistor M13 connects the drain electrode of the 14 transistor M14, and drain electrode connects the grid of the tenth two-transistor M12; The drain electrode of the tenth two-transistor M12 meets reference current Ibias, grid and drain electrode short circuit, source ground; The source ground of the 16 transistor M16, drain electrode connects power amplifier 3 by second resistance R 2 and the 3rd resistance R 3; The source electrode of the 15 transistor M15 connects the drain electrode of the 16 transistor M16, and drain electrode connects the drain electrode of the tenth two-transistor M12.
Wherein, the 13 transistor M13 and the 14 transistor M14 form first switch, and the 15 transistor M15 and the 16 transistor M16 form second switch; The 17 transistor M17 and the tenth transistor M10 constitute first inverter, the 18 transistor M18 and the 11 transistor M11 form second inverter, and first inverter and second inverter produce homophase and the inversion signal of control logic input signal Mod and control first switch and second switch.
Low noise amplifier 4 comprises the 3rd inductance L 3, the 4th inductance L 4, first capacitor C 1, the 5th inductance L 5 that is connected with first capacitor C, 1 bottom crown, second capacitor C 2, the 6th inductance L 6, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4 and the 5th transistor M5 that are connected with second capacitor C, 2 bottom crowns.The first differential input end LNAin1 of low noise amplifier and the second differential input end LNAin2 of low noise amplifier connect the top crown of first capacitor C 1 and the top crown of second capacitor C 2 respectively; The other end of the 5th inductance L 5 and the 6th inductance L 6 connects the grid of the 4th transistor M4 and the grid of the 5th transistor M5 respectively, the source electrode of the 4th transistor M4 and the 5th transistor M5 connects an end of the 3rd inductance L 3 and the 4th inductance L 4 respectively, the equal ground connection of the other end of the 3rd inductance L 3 and the 4th inductance L 4, the drain electrode of the 4th transistor M4 and the 5th transistor M5 connects the source electrode of transistor seconds M2 and the 3rd transistor M3 respectively, the grid of transistor seconds M2 and the 3rd transistor M3 all meets the first bias voltage V1, the first bias voltage V1 is made of reference voltage source and buffer, the drain electrode of transistor seconds M2 connects first inductance L, 1 lower end, the 9th capacitor C O2 top crown of first capacitor array and low capacity, the drain electrode of the 3rd transistor M3 connects second inductance L, 2 lower ends, the top crown of second capacitor array and the 8th capacitor C O1.The grid of the grid of the 4th transistor M4 and the 5th transistor M5 is connected with zero resistance R0 and first resistance R 1 respectively.The bottom crown of the bottom crown of the 8th capacitor C O1 and the 9th capacitor C O2 meets the first public difference output end out1 and the second public difference output end out2 respectively.
Transistor seconds M2, the 4th transistor M4 and the 3rd transistor M3, the 5th transistor M5 constitute cascodes respectively, amplifier tube as low noise amplifier 4, certain gain is provided, reduces the influence of the first public difference output end out1 and the amplifier tube of the second public difference output end out2 simultaneously.The 3rd inductance L 3, the 4th inductance L 4, the 5th inductance L 5 and the 6th inductance L 6 are used for the input impedance coupling of low noise amplifier 4, first capacitor C 1 and second capacitor C 2 are used for the isolated DC signal, and the second differential input end LNAin2 of the first differential input end LNAin1 of low noise amplifier and low noise amplifier are coupled to the input pipe of low noise amplifier 4.
Power amplifier 3 comprises the 3rd capacitor C 3, the 4th capacitor C 4, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8 and the 9th transistor M9; The first differential input end PAin1 of power amplifier and the second differential input end PAin2 of power amplifier connect the top crown of the 3rd capacitor C 3 and the top crown of the 4th capacitor C 4 respectively, the bottom crown of the bottom crown of the 3rd capacitor C 3 and the 4th capacitor C 4 connects the grid of the 6th transistor M6 and the grid of the 7th transistor M7 respectively, the source grounding of the source electrode of the 6th transistor M6 and the 7th transistor M7, the drain electrode of the drain electrode of the 6th transistor M6 and the 7th transistor M7 connects the source electrode of the 8th transistor M8 and the source electrode of the 9th transistor M9 respectively, the grid of the grid of the 8th transistor M8 and the 9th transistor M9 all meets the second bias voltage V2, the second bias voltage V2 is made of reference voltage source and buffer, the drain electrode of the 8th transistor M8 connects first inductance L, 1 lower end, the top crown of first capacitor array and the 9th capacitor C O2, the drain electrode of the 9th transistor M9 connect second inductance L, 2 lower ends, the top crown of second capacitor array and the 8th capacitor C O1; The bottom crown of the bottom crown of the 8th capacitor C O1 and the 9th capacitor C O2 meets the first public difference output end out1 and the second public difference output end out2 respectively.The grid of the grid of the 6th transistor M6 and the 7th transistor M7 is connected with second resistance R 2 and the 3rd resistance R 3 respectively.The public output that the first public difference output end out1 and the second public difference output end out2 are low noise amplifier 4 and power amplifier 3.
The 6th transistor M6, the 8th transistor M8 and the 7th transistor M7, the 9th transistor M9 constitute cascodes respectively, as the amplifier tube of power amplifier 3, provide higher power gain; The 3rd capacitor C 3 and the 4th capacitor C 4 are used for the isolated DC signal, and the second differential input end PAin2 of the first differential input end PAin1 of power amplifier and power amplifier are coupled to the input pipe of power amplifier 3.
Voltage controlled oscillator 1 comprises resonant network, the 0th transistor and the first transistor M1, and vco1 is first difference output end of voltage controlled oscillator, and vco2 is second difference output end of voltage controlled oscillator.Resonant network comprises zero inductance L0, zero capacitance C0 and variable capacitance Cv, and the three is parallel with one another, and zero inductance L0 connects power end; The 0th transistorized grid connects the drain electrode of the first transistor M1, the pole plate of its public termination variable capacitance Cv, and the grid of the first transistor M1 connects the 0th transistor drain, another pole plate of its public termination variable capacitance Cv.The first transistor M1 and the 0th transistor constitute negative resistance, the energy of keeping vibration are provided for voltage controlled oscillator 1.
The source electrode of the 0th transistorized source electrode and the first transistor M1 links to each other by jumbo the 7th capacitor C c, connects by the 7th capacitor C c, and to the radio frequency signal shorts, Low Medium Frequency signal open circuit keeps voltage controlled oscillator 1 tail current constant; The source electrode of the 0th transistorized source electrode and the first transistor M1 connects the top crown of the 5th capacitor C 5 and the top crown of the 6th capacitor C 6 respectively simultaneously, the equal ground connection of the bottom crown of the bottom crown of the 5th capacitor C 5 and the 6th capacitor C 6, the 5th capacitor C 5 and the 6th capacitor C 6 can suppress the variation of output common mode level effectively, and it is remained within the suitable scope.Simultaneously, the source electrode of the 0th transistor and the first transistor M1 is connected with the upper end of first inductance L 1 and second inductance L 2 respectively.
Below be the course of work of the present invention:
When control logic input signal Mod is high level, the 13 transistor M13 and the 16 transistor M16 conducting, the 14 transistor M14, the 15 transistor M15 turn-offs, so the second control logic output signal BiasP level pulled down to earth potential, power amplifier 3 is cut off, and the first control logic output signal BiasL level is identical with the tenth two-transistor M12 grid leak electrode potential, at this moment, the tenth two-transistor M12, the 4th transistor M4 and the 5th transistor M5 constitute first current mirror, for two branch roads of low noise amplifier 4 and voltage controlled oscillator 1 stepped construction provide electric current.
Otherwise, when control logic input signal Mod is low level, the 14 transistor M14, the 15 transistor M15 conducting, the 13 transistor M13 and the 16 transistor M16 turn-off, low noise amplifier 4 is cut off, voltage controlled oscillator 1 and power amplifier 3 constitute stepped construction, and second current mirror that is made of the tenth two-transistor M12, the 6th transistor M6 and the 7th transistor M7 provides electric current for it.
When control logic input signal Mod is high level, be receiving mode; When control logic input signal Mod is low level, be emission mode; Two kinds of mode of operations are switched by mode switching controller 5.
Referring to Fig. 4, though the present invention has adopted lamination techniques, but the work of low noise amplifier 4 does not influence the starting of oscillation of voltage controlled oscillator 1, after voltage controlled oscillator 1 starting of oscillation, can be not influential to the work of low noise amplifier 4 yet, so the work that the stepped construction of voltage controlled oscillator 1 and low noise amplifier 4 can be independent of each other.Same, voltage controlled oscillator 1 also can operate as normal with the stepped construction of power amplifier 3.
More than show and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in above-described embodiment and the specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.

Claims (6)

1. low-power consumption radio-frequency front-end, comprise phase-locked loop (6), low noise amplifier (4) and power amplifier (3), described phase-locked loop (6) comprises voltage controlled oscillator (1), it is characterized in that, also comprise mode switching controller (5), two outputs of described mode switching controller (5) connect the input of power amplifier (3) and low noise amplifier (4) respectively, described low noise amplifier (4) and power amplifier (3) are connected with voltage controlled oscillator (1) with second laod network (2b) by first laod network (2a) respectively, and described mode switching controller (5) and voltage controlled oscillator (1) all connect power end;
Described mode switching controller (5) comprises transistor, and wherein, the 17 transistorized grid connects the tenth transistorized grid, its public termination control logic input signal, and source electrode connects power end, and drain electrode connects the tenth transistor drain; The tenth transistorized source ground, drain electrode connects the 18 transistorized grid and the 11 transistorized grid; The 18 transistorized source electrode connects power end, and drain electrode connects the 11 transistor drain, and grid connects the 14 transistorized grid and the 15 transistorized grid; The 11 transistor drain connects the 13 transistorized grid and the 16 transistorized grid, source ground; The 14 transistor drain connects an end of zero resistance and an end of first resistance, source ground, the other end of the other end of zero resistance and first resistance respectively with low noise amplifier (4) in the 4th transistorized grid be connected with the 5th transistorized grid; The 13 transistorized source electrode connects the 14 transistor drain, and drain electrode connects the grid of the tenth two-transistor; The drain electrode of the tenth two-transistor connects reference current, grid and drain electrode short circuit, source ground; The 16 transistorized source ground, drain electrode connects an end of second resistance and an end of the 3rd resistance, the other end of the other end of second resistance and the 3rd resistance respectively with power amplifier (3) in the 6th transistorized grid be connected with the 7th transistorized grid; The 15 transistorized source electrode connects the 16 transistor drain, and drain electrode connects the drain electrode of the tenth two-transistor.
2. low-power consumption radio-frequency front-end according to claim 1, it is characterized in that described low noise amplifier (4) also comprises the 3rd inductance, the 4th inductance, first electric capacity, the 5th inductance of connecting with first electric capacity, one end, second electric capacity, the 6th inductance, transistor seconds and the 3rd transistor of connecting with second electric capacity, one end; The other end of described the 5th inductance and the 6th inductance connects the 4th transistor and the 5th transistorized grid respectively, the 4th transistor and the 5th transistorized source electrode connect an end of the 3rd inductance and the 4th inductance respectively, the equal ground connection of the other end of described the 3rd inductance and the 4th inductance, described the 4th transistor and the 5th transistor drain connect transistor seconds and the 3rd transistorized source electrode respectively, transistor seconds and the 3rd transistorized grid all connect first bias voltage, transistor seconds and the 3rd transistor drain connect an end of first inductance in first laod network (2a) and an end of second inductance in second laod network (2b) respectively, and the other end of the other end of described first inductance and second inductance connects the source electrode of the 0th transistor and the first transistor in the voltage controlled oscillator (1) respectively.
3. low-power consumption radio-frequency front-end according to claim 1 is characterized in that, described power amplifier (3) also comprises the 3rd electric capacity, the 4th electric capacity, the 8th transistor and the 9th transistor; One end of described the 3rd electric capacity and an end of the 4th electric capacity connect the 6th transistor and the 7th transistorized grid respectively, the 6th transistor and the 7th transistorized source grounding, the 6th transistor and the 7th transistor drain connect the 8th transistor and the 9th transistorized source electrode respectively, the 8th transistor and the 9th transistorized grid all connect second bias voltage, and the 8th transistor and the 9th transistor drain connect an end of first inductance in first laod network (2a) and an end of second inductance in second laod network (2b) respectively.
4. low-power consumption radio-frequency front-end according to claim 1 is characterized in that, described voltage controlled oscillator (1) also comprises resonant network; Described resonant network comprises zero inductance, zero capacitance and variable capacitance, and the three is parallel with one another, and described zero inductance has three ports, and except two ports in parallel with zero capacitance, the 3rd port connects power end; The 0th transistorized grid connects the drain electrode of the first transistor, a pole plate of its public termination variable capacitance; The grid of the first transistor connects the 0th transistor drain, another pole plate of its public termination variable capacitance.
5. low-power consumption radio-frequency front-end according to claim 4, it is characterized in that, the source electrode of the described the 0th transistorized source electrode and the first transistor links to each other by the 7th electric capacity, the source electrode of the described the 0th transistorized source electrode and the first transistor also is connected with an end of the 5th electric capacity and an end of the 6th electric capacity respectively, the equal ground connection of the other end of the other end of described the 5th electric capacity and the 6th electric capacity.
6. according to any described low-power consumption radio-frequency front-end of claim 1 to 4, it is characterized in that,
Described first laod network (2a) also comprises first capacitor array that is connected with first inductance;
Described second laod network (2b) also comprises second capacitor array that is connected with second inductance;
Described first capacitor array and second capacitor array include binary weights capacitor C [1], C[2] ... C[n], one termination, the first control word transistor drain of described capacitor C [1], the transistorized drain terminal of one termination, second control word of described capacitor C [2], by that analogy, one termination n control word transistor drain of described capacitor C [n], the transistorized grid of all control words meets control word K[1 respectively], K[2] ... K[n], the transistorized source grounding of all control words;
Capacitor C [1] in described first capacitor array, C[2] ... C[n] the other end all be connected with an end of first inductance, connect the drain electrode of transistor seconds simultaneously;
Capacitor C [1] in described second capacitor array, C[2] ... C[n] the other end all be connected with an end of second inductance, connect the 3rd transistor drain simultaneously.
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