CN102075208A - Radio frequency front-end with low power consumption - Google Patents

Abstract

The present invention proposes a low-power radio frequency front end, including a phase-locked loop, a low-noise amplifier, and a power amplifier. The phase-locked loop includes a voltage-controlled oscillator, and a mode switching controller. The two modes of the mode switching controller The output ends are respectively connected to the input ends of the power amplifier and the low noise amplifier, the low noise amplifier and the power amplifier are respectively connected to the voltage-controlled oscillator through the first load network and the second load network, and the mode switching controller and the voltage control The oscillators are all connected to the power supply. The present invention utilizes the current multiplexing technology, so that the total power consumption of the three modules of the low-noise amplifier, the voltage-controlled oscillator and the power amplifier is greatly reduced, and the current used by each module is not reduced, so the performance of the circuit will not be reduced. Obvious deterioration; after the introduction of the mode switching controller, the unused modules can be turned off, further reducing the system power consumption.

Description

A low-power RF front-end

technical field

The invention relates to a radio frequency front end, in particular to a low power consumption radio frequency front end.

Background technique

In wireless sensor networks, ZigBee and GPS, low power consumption transceiver system (module) design is the main goal. One of the methods to achieve low power consumption design is to bias the MOS tube in the sub-threshold region. However, there are some problems with this method. For example, the size of transistors operating in the subthreshold region is generally large, which limits the maximum operating frequency of the transistor, which means that the operating speed of the circuit is relatively low. Usually, this method is not suitable for use in the radio frequency field. application. Another method is to reduce the size of each branch transistor to obtain a smaller operating current, which will lead to larger mismatch and flicker noise. The above discussion shows that in the radio frequency field, there are certain problems in making the transistor work in the sub-threshold region to obtain a smaller working current or reducing the size of the transistor to obtain a smaller working current.

Contents of the invention

Aiming at the deficiencies in the prior art, the purpose of the present invention is to provide a low-power RF front-end, which multiplexes one current for use by multiple modules, and the current for each module is sufficient to ensure its performance, while for multiple The module achieves low power consumption without seriously degrading performance.

In order to achieve the above object, the present invention is achieved through the following technical solutions:

The present invention includes a phase-locked loop, a low-noise amplifier and a power amplifier. The phase-locked loop includes a voltage-controlled oscillator and a mode switching controller. The two output ends of the mode switching controller are respectively connected to the input ends of the power amplifier and the low-noise amplifier. The low noise amplifier and the power amplifier are respectively connected to the voltage-controlled oscillator through the first load network and the second load network, and both the mode switching controller and the voltage-controlled oscillator are connected to the power supply terminal. The voltage-controlled oscillator, the power amplifier and the low-noise amplifier of the present invention share one current, which greatly reduces the total power consumption of the circuit.

The above-mentioned mode switching controller includes a transistor, wherein the gate of the seventeenth transistor is connected to the gate of the tenth transistor, its common terminal is connected to the control logic input signal, its source is connected to the power supply terminal, and its drain is connected to the drain of the tenth transistor; The source of the tenth transistor is grounded, and the drain is connected to the gate of the eighteenth transistor and the gate of the eleventh transistor; the source of the eighteenth transistor is connected to the power supply terminal, and the drain is connected to the drain of the eleventh transistor, and the gate The pole is connected to the gate of the fourteenth transistor and the gate of the fifteenth transistor; the drain of the eleventh transistor is connected to the gate of the thirteenth transistor and the gate of the sixteenth transistor, and the source is grounded; the fourteenth transistor The drain of the thirteenth transistor is connected to the low-noise amplifier, and the source is grounded; the source of the thirteenth transistor is connected to the drain of the fourteenth transistor, and the drain is connected to the gate of the twelfth transistor; the drain of the twelfth transistor is connected to the reference current, The gate and the drain are short-circuited, and the source is grounded; the source of the sixteenth transistor is grounded, and the drain is connected to the power amplifier; the source of the fifteenth transistor is connected to the drain of the sixteenth transistor, and the drain is connected to the twelfth transistor the drain.

The above-mentioned low noise amplifier comprises a third inductor, a fourth inductor, a first capacitor, a fifth inductor connected in series with one end of the first capacitor, a second capacitor, a sixth inductor connected in series with one end of the second capacitor, a second transistor, and a third transistor , the fourth transistor and the fifth transistor; the other section of the fifth inductance and the sixth inductance are respectively connected to the gate of the fourth transistor and the gate of the fifth transistor, and the sources of the fourth transistor and the fifth transistor are respectively connected to the first One end of the third inductance and the fourth inductance, the other end of the third inductance and the fourth inductance are grounded, the drains of the fourth transistor and the fifth transistor are respectively connected to the sources of the second transistor and the third transistor, and The gates of the second transistor and the third transistor are both connected to the first bias voltage, and the drains of the second transistor and the third transistor are respectively connected to the first load network and the second load network.

The power amplifier includes a third capacitor, a fourth capacitor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; the third capacitor and the fourth capacitor are respectively connected to the gate of the sixth transistor and the gate of the seventh transistor. The grid, the source of the sixth transistor and the source of the seventh transistor are all grounded, the drain of the sixth transistor and the drain of the seventh transistor are respectively connected to the source of the eighth transistor and the source of the ninth transistor, and the eighth transistor is connected to the source of the ninth transistor. The gates of the transistor and the ninth transistor are both connected to the second bias voltage, and the drains of the eighth transistor and the ninth transistor are respectively connected to the first load network and the second load network.

The voltage-controlled oscillator includes a resonant network, a zeroth transistor, and a first transistor; the resonant network includes a zeroth inductance, a zeroth capacitor, and a variable capacitor, and the three are connected in parallel with each other, and the zeroth inductance is connected to the power supply terminal; the zeroth transistor The gate of the first transistor is connected to the drain of the first transistor, and its common terminal is connected to a plate of the variable capacitor; the gate of the first transistor is connected to the drain of the zeroth transistor, and its common terminal is connected to the other plate of the variable capacitor; The first load network and the second load network are respectively connected to the sources of the zeroth transistor and the first transistor.

The source of the above-mentioned zeroth transistor is connected to the source of the first transistor through the seventh large-capacity capacitor, which is short-circuited to the radio frequency signal and opened to the low-intermediate frequency signal, so as to keep the tail current of the voltage-controlled oscillator constant; the source of the zeroth transistor The fifth capacitor and the sixth capacitor are respectively connected to the source of the first transistor, and the fifth capacitor and the sixth capacitor can effectively suppress the change of the output common mode level and keep it within an appropriate range.

The first load network includes a first inductor and a first capacitor array connected to the first inductor; the second load network includes a second inductor and a second capacitor array connected to the second inductor. Using the first capacitor array and the second capacitor array, the digital control of the load can be realized in both the receiving and transmitting modes, and the difference in parasitic capacitance caused by different connection relationships in different working modes can be corrected, and the process and temperature can also be compensated. , Capacitance deviation caused by voltage.

The present invention greatly reduces the total power consumption of the three modules of the low-noise amplifier, the voltage-controlled oscillator and the power amplifier, while the current used by each module is not reduced, so the performance of the circuit will not be significantly deteriorated; the introduction of mode switching After the controller, the unnecessary modules can be turned off to further reduce the power consumption of the system; the load of the low-noise amplifier and the power amplifier can be adjusted through digital control by using the capacitor array, and different connection relationships under different working modes can be corrected The difference in parasitic capacitance caused by this can also compensate for the capacitance deviation caused by the process, temperature, and voltage; the fifth capacitor and the sixth capacitor are introduced into the source of the voltage-controlled oscillator cross-coupling tube, which can effectively suppress the output common-mode level changes to keep it within an appropriate range.

Description of drawings

Describe the present invention in detail below in conjunction with accompanying drawing and specific embodiment:

Fig. 1 is a system diagram of the present invention;

Fig. 2 is a core circuit block diagram of the present invention;

Fig. 3 is a schematic diagram of the core circuit of the present invention;

Fig. 4 is the relevant output waveform diagram when the present invention works in receiving mode (A among the figures is the input waveform of the low noise amplifier, B is the output waveform of the voltage controlled oscillator, and C is the output waveform of the low noise amplifier).

The serial numbers in the figure represent:

1-voltage controlled oscillator; 2a-first load network; 2b-second load network; 3-power amplifier; 4-low noise amplifier; 5-mode switching controller; Mod-control logic input signal; BiasL-first Control logic output signal; BiasP-second control logic output signal; Ibias-reference current; vco1-the first differential output of the voltage-controlled oscillator; vco2-the second differential output of the voltage-controlled oscillator; LNAin1-low noise amplifier The first differential input terminal of LNAin2-the second differential input terminal of the low noise amplifier; PAin1-the first differential input terminal of the power amplifier; PAin2-the second differential input terminal of the power amplifier; out1-the first common differential output terminal; out2-second common differential output terminal; fout-IF output signal; fin-IF input signal; V1-first bias voltage; V2-second bias voltage; M1-first transistor; M2-second transistor; M3 - third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M10-tenth transistor; M11-th Eleventh transistor; M12-twelfth transistor; M13-thirteenth transistor; M14-fourteenth transistor; M15-fifteenth transistor; M16-sixteenth transistor; P0-seventeenth transistor; P1-tenth Eight transistors; R0-the zeroth resistance; R1-the first resistance; R2-the second resistance; R3-the third resistance; L0-the zeroth inductance; L1-the first inductance; L2-the second inductance; L3-the third inductance ; L4-fourth inductance; L5-fifth inductance; L6-sixth inductance; C0-zero capacitance; C1-first capacitance; C2-second capacitance; C3-third capacitance; C4-fourth capacitance; C5 -Fifth capacitor; C6-sixth capacitor; Cv-variable capacitor; Cc-seventh capacitor; CO1-eighth capacitor; CO2-ninth capacitor; K[1], K[2]...K[n ] - control word; C[1], C[2]...C[n] - binary weight capacitors.

Detailed ways

In order to make the technical means, creative features, goals and effects achieved by the present invention easy to understand, the present invention will be further described below in conjunction with specific embodiments.

Referring to FIG. 1 and FIG. 2 , the present invention includes a phase-locked loop 6 , a low-noise amplifier 4 , a power amplifier 3 and a mode switching controller 5 , and the phase-locked loop 6 includes a voltage-controlled oscillator 1 . The current of the voltage controlled oscillator 1 is multiplexed with the low noise amplifier 4 and the power amplifier 3 . The lower mixer 7b inputs the output radio frequency signal from the low noise amplifier 4 and the local oscillator signal provided by the phase-locked loop 6 to generate the intermediate frequency output signal fout; the upper mixer 7a input comes from the intermediate frequency input signal fin and the phase-locked loop 6 provides The local oscillator signal is output as the input signal of the power amplifier 3.

The two output terminals of the mode switching controller 5 are respectively connected to the power amplifier 3 and the low noise amplifier 4, and the power amplifier 3 and the low noise amplifier 4 are respectively connected to the voltage controlled oscillator 1 through the first load network 2a and the second load network 2b, Both the mode switching controller 5 and the voltage-controlled oscillator 1 are connected to the power supply terminal. The power supply terminal supplies power to the voltage-controlled oscillator 1 and the mode switching controller 5 , while the power amplifier 3 and the low-noise amplifier 4 share the current of the voltage-controlled oscillator 1 .

The present invention adopts multi-module lamination current multiplexing technology, and provides bias current for the voltage-controlled oscillator 1 and low-noise amplifier 4 or the voltage-controlled oscillator 1 and power amplifier 3 connected in lamination through the control of the mode switching controller 5, so that the power amplifier 3 and low noise amplifier 4 work selectively. When working in the transmitting mode, the voltage-controlled oscillator 1 and the power amplifier 3 are cascaded and connected, the power amplifier 3 shares the tail current of the voltage-controlled oscillator 1, and the low-noise amplifier 4 does not work; while working in the receiving mode, the mode switching controller 5 The stacking path between the voltage-controlled oscillator 1 and the power amplifier 3 will be cut off, and the stacking path between the voltage-controlled oscillator 1 and the low-noise amplifier 4 will be turned on at the same time. The low-noise amplifier 4 shares the tail current of the voltage-controlled oscillator 1, and the power amplifier 3 will not Work. The voltage-controlled oscillator 1, the power amplifier 3 and the low-noise amplifier 4 of the present invention share one current, which greatly reduces the total power consumption of the circuit.

The low noise amplifier 4 and the power amplifier 3 share the first load network 2a and the second load network 2b respectively. The first load network 2a includes a first inductor L1 and a first capacitor array; the second load network 2b includes a second inductor L2 and a second capacitor array. Both the first capacitor array and the second capacitor array are composed of binary weight capacitors C[1], C[2]...C[n] and switches, and the switch drains are respectively connected to binary weight capacitors C[1], C[2 ]...C[n] lower plates, the gates are respectively connected to the control words K[1], K[2]...K[n], and the switch sources are all grounded.

The first load network 2a and the second load network 2b can select different capacitors by changing the control words K[1], K[2]...K[n] of the first capacitor array and the second capacitor array respectively, It resonates with the first inductor L1 and the second inductor L2. The advantage of using the first capacitor array and the second capacitor array is that the digital control of the load can be realized in both the receiving and transmitting modes, and the difference in parasitic capacitance caused by different connection relationships in different working modes can be corrected. At the same time, it can also compensate for the process, Capacitance deviation caused by temperature and voltage.

Referring to FIG. 3 , the mode switching controller 5 of the present invention includes transistors, wherein the gate of the seventeenth transistor M17 is connected to the gate of the tenth transistor M10, its common terminal is connected to the control logic input signal Mod, and its source is connected to the power supply terminal. The drain is connected to the drain of the tenth transistor M10; the source of the tenth transistor M10 is grounded, and the drain is connected to the gate of the eighteenth transistor M18 and the gate of the eleventh transistor M11; the source of the eighteenth transistor M18 is connected to Power supply terminal, the drain is connected to the drain of the eleventh transistor M11, the gate is connected to the gate of the fourteenth transistor M14 and the gate of the fifteenth transistor M15; the drain of the eleventh transistor M11 is connected to the thirteenth transistor M13 The gate of the gate and the gate of the sixteenth transistor M16, the source is grounded; the drain of the fourteenth transistor M14 is connected to the low noise amplifier 4 through the zero resistance R0 and the first resistance R1, and the source is grounded; the thirteenth transistor M13 The source is connected to the drain of the fourteenth transistor M14, and the drain is connected to the gate of the twelfth transistor M12; the drain of the twelfth transistor M12 is connected to the reference current Ibias, the gate and the drain are short-circuited, and the source is grounded; The source of the sixteenth transistor M16 is grounded, and the drain is connected to the power amplifier 3 through the second resistor R2 and the third resistor R3; the source of the fifteenth transistor M15 is connected to the drain of the sixteenth transistor M16, and the drain is connected to the tenth The drain of the second transistor M12.

Among them, the thirteenth transistor M13 and the fourteenth transistor M14 form the first switch, the fifteenth transistor M15 and the sixteenth transistor M16 form the second switch; the seventeenth transistor M17 and the tenth transistor M10 form the first inverter , the eighteenth transistor M18 and the eleventh transistor M11 form the second inverter, and the first inverter and the second inverter generate the in-phase and inversion signals of the control logic input signal Mod to control the first switch and the second switch.

The low-noise amplifier 4 includes a third inductor L3, a fourth inductor L4, a first capacitor C1, a fifth inductor L5 connected to the lower plate of the first capacitor C1, a second capacitor C2, and a phase electrode connected to the lower plate of the second capacitor C2. The connected sixth inductor L6, the second transistor M2, the third transistor M3, the fourth transistor M4 and the fifth transistor M5. The first differential input terminal LNAin1 of the low noise amplifier and the second differential input terminal LNAin2 of the low noise amplifier are respectively connected to the upper plate of the first capacitor C1 and the upper plate of the second capacitor C2; the fifth inductance L5 and the sixth inductance L6 The other end of the gate of the fourth transistor M4 and the gate of the fifth transistor M5 are respectively connected, and the sources of the fourth transistor M4 and the fifth transistor M5 are respectively connected to one end of the third inductance L3 and the fourth inductance L4, and the third inductance The other ends of L3 and the fourth inductance L4 are both grounded, the drains of the fourth transistor M4 and the fifth transistor M5 are respectively connected to the sources of the second transistor M2 and the third transistor M3, and the gates of the second transistor M2 and the third transistor M3 Both poles are connected to the first bias voltage V1, the first bias voltage V1 is composed of a reference voltage source and a buffer, the drain of the second transistor M2 is connected to the lower end of the first inductor L1, the first capacitor array and the ninth capacitor with a small capacity The upper plate of CO2, the drain of the third transistor M3 is connected to the lower end of the second inductor L2, the second capacitor array and the upper plate of the eighth capacitor CO1. The gate of the fourth transistor M4 and the gate of the fifth transistor M5 are connected to the zero resistor R0 and the first resistor R1 respectively. The lower plate of the eighth capacitor CO1 and the lower plate of the ninth capacitor CO2 are connected to the first common differential output terminal out1 and the second common differential output terminal out2 respectively.

The second transistor M2, the fourth transistor M4, the third transistor M3, and the fifth transistor M5 respectively form a cascode structure, which serves as the amplifier tube of the low-noise amplifier 4, provides a certain gain, and reduces the first common differential output terminal at the same time The influence of out1 and the second common differential output terminal out2 on the amplifier tube. The third inductance L3, the fourth inductance L4, the fifth inductance L5 and the sixth inductance L6 are used for the input impedance matching of the low-noise amplifier 4, and the first capacitor C1 and the second capacitor C2 are used for isolating DC signals and connecting the low-noise amplifier The first differential input terminal LNAin1 of the low noise amplifier and the second differential input terminal LNAin2 of the low noise amplifier are coupled to the input transistor of the low noise amplifier 4 .

The power amplifier 3 includes a third capacitor C3, a fourth capacitor C4, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9; the first differential input terminal PAin1 of the power amplifier and the second differential input terminal of the power amplifier The input terminal PAin2 is respectively connected to the upper plate of the third capacitor C3 and the upper plate of the fourth capacitor C4, and the lower plate of the third capacitor C3 and the lower plate of the fourth capacitor C4 are respectively connected to the gate and gate of the sixth transistor M6. The gate of the seventh transistor M7, the source of the sixth transistor M6 and the source of the seventh transistor M7 are all grounded, and the drain of the sixth transistor M6 and the drain of the seventh transistor M7 are respectively connected to the source of the eighth transistor M8 and the source of the ninth transistor M9, the gate of the eighth transistor M8 and the gate of the ninth transistor M9 are connected to the second bias voltage V2, the second bias voltage V2 is composed of a reference voltage source and a buffer, the eighth transistor M8 The drain of the transistor M8 is connected to the lower end of the first inductor L1, the first capacitor array and the upper plate of the ninth capacitor CO2, and the drain of the ninth transistor M9 is connected to the lower end of the second inductor L2, the second capacitor array and the eighth capacitor CO1 The upper plate; the lower plate of the eighth capacitor CO1 and the lower plate of the ninth capacitor CO2 are respectively connected to the first common differential output terminal out1 and the second common differential output terminal out2. The gate of the sixth transistor M6 and the gate of the seventh transistor M7 are connected to the second resistor R2 and the third resistor R3 respectively. The first common differential output terminal out1 and the second common differential output terminal out2 are common output terminals of the low noise amplifier 4 and the power amplifier 3 .

The sixth transistor M6, the eighth transistor M8, the seventh transistor M7, and the ninth transistor M9 respectively form a cascode structure, which serves as an amplifying tube of the power amplifier 3 and provides higher power gain; the third capacitor C3 and the fourth capacitor C4 is used to isolate the DC signal, and couple the first differential input terminal PAin1 of the power amplifier and the second differential input terminal PAin2 of the power amplifier to the input transistor of the power amplifier 3 .

The voltage controlled oscillator 1 includes a resonant network, a zeroth transistor and a first transistor M1, vco1 is the first differential output terminal of the voltage controlled oscillator, and vco2 is the second differential output terminal of the voltage controlled oscillator. The resonant network includes the zeroth inductance L0, the zeroth capacitance C0 and the variable capacitance Cv, the three are connected in parallel, and the zeroth inductance L0 is connected to the power supply terminal; the gate of the zeroth transistor is connected to the drain of the first transistor M1, and its common terminal It is connected to one plate of the variable capacitor Cv, the gate of the first transistor M1 is connected to the drain of the zeroth transistor, and its common terminal is connected to the other plate of the variable capacitor Cv. The first transistor M1 and the zeroth transistor form a negative resistance to provide the voltage-controlled oscillator 1 with energy to maintain oscillation.

The source of the zeroth transistor and the source of the first transistor M1 are connected through the seventh large-capacity capacitor Cc, connected through the seventh capacitor Cc, the radio frequency signal is short-circuited, the low-intermediate frequency signal is open-circuited, and the tail current of the voltage-controlled oscillator 1 is kept constant. ; Simultaneously, the source of the zeroth transistor and the source of the first transistor M1 are respectively connected to the upper plate of the fifth capacitor C5 and the upper plate of the sixth capacitor C6, and the lower plate of the fifth capacitor C5 and the sixth capacitor C6 Both the lower plates are grounded, and the fifth capacitor C5 and the sixth capacitor C6 can effectively suppress the change of the output common mode level and keep it within an appropriate range. Meanwhile, the sources of the zeroth transistor and the first transistor M1 are connected to the upper ends of the first inductor L1 and the second inductor L2 respectively.

Following is the working process of the present invention:

When the control logic input signal Mod is at a high level, the thirteenth transistor M13 and the sixteenth transistor M16 are turned on, and the fourteenth transistor M14 and the fifteenth transistor M15 are turned off, so the level of the second control logic output signal BiasP is controlled by Pull down to the ground potential, the power amplifier 3 is cut off, and the level of the first control logic output signal BiasL is the same as the gate-drain potential of the twelfth transistor M12, at this time, the twelfth transistor M12, the fourth transistor M4 and the fifth transistor M5 constitutes a first current mirror, which provides current for the two branches of the stacked structure of the low noise amplifier 4 and the voltage-controlled oscillator 1 .

Conversely, when the control logic input signal Mod is at a low level, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the thirteenth transistor M13 and the sixteenth transistor M16 are turned off, the low noise amplifier 4 is cut off, and the voltage control The oscillator 1 and the power amplifier 3 form a stack structure, and the second current mirror formed by the twelfth transistor M12 , the sixth transistor M6 and the seventh transistor M7 supplies current thereto.

When the control logic input signal Mod is high level, it is the receiving mode; when the control logic input signal Mod is low level, it is the transmission mode; the two working modes are switched by the mode switching controller 5 .

Referring to Fig. 4, although the present invention adopts the lamination technology, the work of the low noise amplifier 4 does not affect the start-up of the voltage-controlled oscillator 1, and after the start-up of the voltage-controlled oscillator 1, it will not affect the work of the low-noise amplifier 4 Therefore, the stacked structure of the voltage-controlled oscillator 1 and the low-noise amplifier 4 can work independently of each other. Similarly, the stacked structure of the voltage-controlled oscillator 1 and the power amplifier 3 can also work normally.

The basic principles and main features of the present invention and the advantages of the present invention have been shown and described above. Those skilled in the industry should understand that the present invention is not limited by the above-mentioned embodiments. What are described in the above-mentioned embodiments and the description only illustrate the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will also have Variations and improvements are possible, which fall within the scope of the claimed invention. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (7)

1. a kind of low-power radio frequency front-end, comprises phase-locked loop (6), low-noise amplifier (4) and power amplifier (3), and described phase-locked loop (6) comprises voltage-controlled oscillator (1), its feature In that, it also includes a mode switching controller (5), the two output terminals of the mode switching controller (5) are respectively connected to the input terminals of the power amplifier (3) and the low noise amplifier (4), and the low noise amplifier (4) ) and the power amplifier (3) are respectively connected to the voltage-controlled oscillator (1) through the first load network (2a) and the second load network (2b), and the mode switching controller (5) and the voltage-controlled oscillator ( 1) Both are connected to the power supply terminal. 2. The low-power radio frequency front-end according to claim 1, wherein the mode switching controller (5) includes a transistor, wherein the gate of the seventeenth transistor is connected to the gate of the tenth transistor, and its common The terminal is connected to the control logic input signal, the source is connected to the power supply terminal, and the drain is connected to the drain of the tenth transistor; the source of the tenth transistor is grounded, and the drain is connected to the gate of the eighteenth transistor and the gate of the eleventh transistor; The source of the eighteenth transistor is connected to the power terminal, the drain is connected to the drain of the eleventh transistor, and the grid is connected to the grid of the fourteenth transistor and the grid of the fifteenth transistor; the drain of the eleventh transistor is connected to the grid of the eleventh transistor The gate of the thirteenth transistor and the gate of the sixteenth transistor, the source is grounded; the drain of the fourteenth transistor is connected to the low noise amplifier (4), and the source is grounded; the source of the thirteenth transistor is connected to the fourteenth transistor The drain of the twelfth transistor is connected to the gate of the twelfth transistor; the drain of the twelfth transistor is connected to the reference current, the gate and the drain are shorted, and the source is grounded; the source of the sixteenth transistor is grounded, and the drain is connected to Power amplifier (3); the source of the fifteenth transistor is connected to the drain of the sixteenth transistor, and the drain is connected to the drain of the twelfth transistor. 3. The low-power radio frequency front-end according to claim 1, wherein the low-noise amplifier (4) includes a third inductor, a fourth inductor, a first capacitor, and a fifth inductor connected in series with one end of the first capacitor , the second capacitance, the sixth inductance connected in series with one end of the second capacitance, the second transistor, the third transistor, the fourth transistor and the fifth transistor; the other section of the fifth inductance and the sixth inductance are connected to the fourth transistor and the sixth inductance respectively The gate of the fifth transistor, the sources of the fourth transistor and the fifth transistor are respectively connected to one end of the third inductance and the fourth inductance, and the other ends of the third inductance and the fourth inductance are both grounded, and the fourth transistor and the fifth transistor are connected to one end of the fourth inductance. The drains of the fifth transistor are respectively connected to the sources of the second transistor and the third transistor, the gates of the second transistor and the third transistor are both connected to the first bias voltage, and the drains of the second transistor and the third transistor are respectively connected to the first bias voltage. A load network (2a) and a second load network (2b). 4. The low-power radio frequency front end according to claim 1, wherein the power amplifier (3) includes a third capacitor, a fourth capacitor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor ; The third capacitor and the fourth capacitor are respectively connected to the gates of the sixth transistor and the seventh transistor, the sources of the sixth transistor and the seventh transistor are all grounded, and the drains of the sixth transistor and the seventh transistor are connected to the eighth transistor respectively. The sources of the transistor and the ninth transistor, the gates of the eighth transistor and the ninth transistor are all connected to the second bias voltage, and the drains of the eighth transistor and the ninth transistor are respectively connected to the first load network (2a) and the second load Network (2b). 5. The low-power radio frequency front-end according to claim 1, wherein the voltage-controlled oscillator (1) includes a resonant network, a zeroth transistor, and a first transistor; the resonant network includes a zeroth inductance, a first Zero capacitance and variable capacitance, the three are connected in parallel with each other, and the zeroth inductance is connected to the power supply terminal; the gate of the zeroth transistor is connected to the drain of the first transistor, and its common terminal is connected to a plate of the variable capacitance; The gate is connected to the drain of the zeroth transistor, and its common terminal is connected to the other plate of the variable capacitor; the first load network (2a) and the second load network (2b) are respectively connected to the zeroth transistor and the first transistor source. 6. The low-power radio frequency front-end according to claim 5, wherein the source of the zeroth transistor is connected to the source of the first transistor through a large-capacity seventh capacitor, and the source of the zeroth transistor The pole and the source of the first transistor are respectively connected to a fifth capacitor and a sixth capacitor. 7. The low-power radio frequency front-end according to any one of claims 1 to 5, wherein the first load network (2a) includes a first inductor and a first capacitor array connected to the first inductor; The second load network (2b) includes a second inductance and a second capacitor array connected to the second inductance.

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