CN102034531A - Static random access memory for reducing reading interference - Google Patents
Static random access memory for reducing reading interference Download PDFInfo
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- CN102034531A CN102034531A CN2010101873755A CN201010187375A CN102034531A CN 102034531 A CN102034531 A CN 102034531A CN 2010101873755 A CN2010101873755 A CN 2010101873755A CN 201010187375 A CN201010187375 A CN 201010187375A CN 102034531 A CN102034531 A CN 102034531A
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Abstract
The invention provides a static random access memory for reducing the reading interference, comprising a first NMOS (N-channel metal oxide semiconductor) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS (P-channel Metal Oxide Semiconductor) transistor and a second PMOS transistor, wherein the first PMOS transistor and the first NMOS as well as the second PMOS transistor and the second NMOS transistor form two COMS (Complementary Metal Oxide Semiconductor) phase inverters which are crossly coupled to form a bistable flip-flop; the source electrode of the third NMOS transistor is connected with the drain electrode of the first PMOS transistor and the source electrode of the first NMOS transistor; and the source electrode of the fourth NMOS transistor is connected with the drain electrode of the second PMOS transistor and the source electrode of the second NMOS transistor. The static random access memory also comprises a fifth NMOS transistor, wherein the source electrode of the fifth NMOS transistor is connected with the drain electrode of the first NMOS transistor and the drain electrode of the fifth NMOS transistor is connected with a low level. In the invention, the fifth NMOS transistor is added in the static random access memory and closed during the execution of a reading task, thereby preventing the reading interference phenomenon and improving the stability of the reading state of the static random access memory.
Description
Technical field
The present invention relates to a kind of semiconductor devices, relate in particular to the static RAM that interference is read in a kind of minimizing.
Background technology
Component density within the integrated circuit can be utilized integrated circuit (IC) design (the reducedgeometry integrated circuit designs) principle in reduction space, increases the performance of integrated circuit and reduces its real cost.The modern integrated circuits memory device that comprises Flash, SRAM (static RAM), OUM, EEPROM, FRAM, MRAM etc. all is the obvious example that utilizes the principle of this poke unit (memory cell).Density in the integrated circuit memory devices increases just constantly, and what follow with it is the corresponding reduction of the unit carrying cost of this class device.The increase of density is to utilize to make small construction in device, and utilization reduces between the element or the compartment between the structure of composed component is finished.Usually, the design criteria of this class reduced size (design rules) can be attended by layout, and the correction of design and structure is when using the design criteria of this class reduced size, these are revised and change and will could realize by the size of reduction element, but also will keep device performance.As a kind of example, the reduction of its operating voltage among multiple existing integrated circuits is because such as the reduction gate oxide thicknesses, and promotes that error in little shadow programmed control just may finish.On the other hand, the design criteria of size reduction also make to reduce operating voltage and becomes necessity, so that if small-sized component is limited the hot carrier (hot carriers) that generation is understood by institute during with existing higher operation voltage operation.First generation SRAM module adopts large scale DIP encapsulation, and this encapsulation has certain height, because battery and RAM chip are stacked among the DIP encapsulation.The advantage of DIP encapsulation is that device can insert the DIP socket, the convenient replacement and storage, or transfer to another from a printed board.Though these advantages are still very useful so far, by contrast, more be necessary to develop surface mounting technology, and operating voltage is become 3.3V by 5V.Second generation SRAM module adopts two-piece type scheme---PowerCap module (PCM), promptly is made up of the pedestal that is welded direct to printed panel (comprising SRAM) and PowerCap (lithium battery just) two parts.Compare with the DIP module, this class device has two major advantages: they adopt surface mount, and have the standard pin configuration.In other words, the SRAM of much capacity no matter, its encapsulation is identical with number of pins.Therefore, the designer can strengthen system memory size, and need not worry to need to change the PCB layout.Battery altering gets up and also is easy to.The SRAM module that the third generation is just up-to-date, it has not only solved the existing problem of previous product, has increased greater functionality simultaneously.This class novel sram is a monolithic BGA module, built-in chargeable lithium cell.The same with PCM, all SRAM that adopt this packing forms are its amount of capacity no matter, and package dimension all is identical with pin configuration.This generic module adopts surface mount, and is monolithic device.Therefore design is firmer reliable, can bear stronger mechanical shock than the previous generation device.Because battery is chargeable, so the notion of data holding time has had other one deck implication.Describe more appropriately with equivalence speech in serviceable life one, the equivalence of this class device serviceable life can be up to 200 years.In addition, this module can bear+230 ℃ Reflow Soldering temperature, and the Lead-free in Electronic Packaging device that provides can bear+and 260 ℃ temperature.
Cellar area and cell stability are two importances of SRAM design.Cellar area has determined the size of memory chip to a great extent; Cell stability has determined the data reliability of storer, and stability described here comprises and reads stability and write stability.The main flow cellular construction of SRAM comprises 6 MOS transistor, and its formation can be the whole CMOS planar structure, also can be the laminated type three-dimensional structure.Please refer to Fig. 1, Fig. 1 is the structural representation of six transistorized SRAM in the prior art, among the figure, described SRAM is made of six transistors, in described six transistors, comprise that four NMOS pipe N1, N2, N3, N4 and two PMOS manage P1 and P2, wherein a PMOS pipe P1, NMOS pipe N1 and the 2nd PMOS pipe P2, the 2nd NMOS manage two COMS phase inverters of N2 composition, and cross-couplings forms trigger flip-flop; Gate tube the 3rd NMOS pipe N3, the 4th NMOS pipe N4 provides the approach and the control of data input and output; BL among the figure,
Be the bit line control signal, WL is the word line of this unit, in read operation, when V1 voltage increases, just may cause the change of current lock-out state.And after the CMOS technology enters sub-micro; the bad stability of D S RAM; especially the bad stability of reading state; its main cause is that 2 PMOS load pipes are to be made by non-aligned back of the body grid technique technology; when the stored data of the same block in the storer is repeatedly read; the reading times between 100,000 to 1,000,000 times for example; probably the data that can take place to be read is wrong, even this data that is repeatedly read in the block to be stored can take place unusual or loses.And this type of phenomenon has with field of the present invention and knows that usually the knowledgeable is used to be called " reading interference " (read-disturb), also because of there being such phenomenon to exist, order about each tame manufacturer invariably and must develop the technology that to prevent to read interference, so as to suppressing to read the interference odds effectively.Please refer to Fig. 2, Fig. 2 is the structural representation of improved static RAM in the prior art, SRAM among Fig. 2 has increased by two NMOS pipe N6 and N7 than SRAM among Fig. 1, in the time will reading to the data that the block in the storage period is stored, will use two NMOS pipes of extra increase, thereby avoid in process of reading, producing and read interference, the accuracy that assurance is read, yet the shortcoming of SRAM is that integrated level is low originally, and power consumption is bigger, identical content volume is bigger, increase by two NMOS pipes, will certainly increase the volume of SRAM to a great extent, be unfavorable for improving the service efficiency of SRAM.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of static RAM, solves static RAM and read the problem of interference easily when reading.
To achieve these goals, the present invention proposes the static RAM that interference is read in a kind of minimizing, comprising: a CMOS phase inverter, form by NMOS pipe and the 2nd PMOS pipe; The 2nd CMOS phase inverter is made up of the 2nd NMOS pipe and the 2nd PMOS pipe, and a described CMOS phase inverter and described the 2nd CMOS phase inverter cross-couplings form trigger flip-flop; The 3rd NMOS pipe, the drain electrode of the source electrode of described the 3rd NMOS pipe and a described PMOS pipe, the source electrode of a described NMOS pipe all link to each other; The 4th NMOS pipe, the drain electrode of the source electrode of described the 4th NMOS pipe and described the 2nd PMOS pipe, the source electrode of described the 2nd NMOS pipe all link to each other; Described static RAM also comprises the 5th NMOS pipe, and the source electrode of described the 5th NMOS pipe links to each other with the drain electrode of a described NMOS pipe, and the drain electrode of described the 5th NMOS pipe connects low level.
Optionally, the source electrode of a described PMOS pipe links to each other with the source electrode of described the 2nd PMOS pipe.
Optionally, the source electrode of the source electrode of a described PMOS pipe and described the 2nd PMOS pipe all is connected high level.
Optionally, the source electrode of described the 3rd metal-oxide-semiconductor links to each other with the grid of described the 2nd PMOS pipe.
Optionally, the source electrode of described the 3rd metal-oxide-semiconductor links to each other with the grid of described the 2nd NMOS pipe.
Optionally, the drain electrode of described the 2nd PMOS pipe links to each other with the source electrode of described the 2nd NMOS pipe.
Optionally, the drain electrode of described the 2nd NMOS pipe connects low level.
The useful technique effect that the static RAM of interference is read in a kind of minimizing of the present invention is: the present invention adds the 5th NMOS pipe in static RAM, when task is read in execution, the 5th NMOS pipe is closed, thereby avoided reading the generation of interference phenomenon, improved the stability of static RAM reading state.
Description of drawings
Fig. 1 is the structural representation of prior art static RAM.
Fig. 2 is the structural representation of improved static RAM in the prior art.
Fig. 3 is the structural representation that the static RAM of interference is read in a kind of minimizing of the present invention.
Fig. 4 is the operation form that the static RAM of interference is read in a kind of minimizing of the present invention.
Fig. 5 is the first embodiment analysis diagram of a kind of minimizing of the present invention static RAM of reading interference.
Fig. 6 is the second embodiment analysis diagram of a kind of minimizing of the present invention static RAM of reading interference.
Embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Please refer to Fig. 3, Fig. 3 is that the static RAM of interference is read in a kind of minimizing of the present invention, this static RAM is to have increased a NMOS pipe on the basis of existing six transistorized static RAM, existing SRAM is made of six transistors, in described six transistors, comprise four NMOS pipe N1, N2, N3, N4 and two PMOS manage P1 and P2, wherein a PMOS manages P1, the one NMOS pipe N1 and the 2nd PMOS pipe P2, the 2nd NMOS pipe N2 forms two COMS phase inverters, cross-couplings forms trigger flip-flop, the one CMOS phase inverter is made up of NMOS pipe and the 2nd PMOS pipe; The 2nd CMOS phase inverter is made up of the 2nd NMOS pipe and the 2nd PMOS pipe; Gate tube the 3rd NMOS pipe N3, the 4th NMOS pipe N4 provides the approach and the control of data input and output, the drain electrode of the source electrode of described the 3rd NMOS pipe and a described PMOS pipe, the source electrode of a described NMOS pipe all link to each other, and the drain electrode of the source electrode of described the 4th NMOS pipe and described the 2nd PMOS pipe, the source electrode of described the 2nd NMOS pipe all link to each other; BL among Fig. 3,
Be the bit line control signal, WL is the word line of this unit, and described static RAM also comprises the 5th NMOS pipe, and the source electrode of described the 5th NMOS pipe links to each other with the drain electrode of a described NMOS pipe, and the drain electrode of described the 5th NMOS pipe connects low level.
The principle of work of SRAM storage unit of the present invention is: when word line control signal WL was high level, gate tube the 3rd NMOS managed M
N3, the 4th NMOS manages M
N4Conducting is by PMOS pipe M
P1, a NMOS manages M
N1With the 2nd PMOS pipe M
P2, the 2nd NMOS manages M
N2The cross coupled flip-flop of forming can from bit line BL,
Output or input signal when using the 2nd NMOS pipe and the 4th NMOS pipe to carry out read operation, are closed the 5th NMOS pipe, block the electric current of this circuit, thereby have avoided reading the generation of interference, have improved the stability of static RAM reading state.The source electrode of the source electrode of described the 5th NMOS pipe and a described PMOS pipe or drain electrode link to each other, and about being connected of source electrode and drain electrode, during actual the use, also can exchange use.
The signal read is exported through behind the sense amplifier, and the amplifier that transistor constitutes will be accomplished without distortion signal voltage to be amplified, and just must guarantee that transistorized emitter junction positively biased, collector junction are anti-inclined to one side, and its working point promptly should be set.So-called working point is exactly that setting by external circuit makes transistorized base stage, emitter and collector be in desired current potential (can obtain according to calculating).These external circuits just are called biasing circuit (can be regarded as, the positive and negative inclined to one side circuit of PN junction is set), and biasing circuit just is called bias current to the electric current that transistor provides.Go ahead with total radio amplifier commonly used, main flow is the IC from the emitter to the collector, and bias current is exactly the IB from the emitter to the base stage, and relative and main circuit is exactly so-called biasing circuit for base stage provides the circuit of electric current.
Then, please refer to Fig. 4, Fig. 4 is the operation form that the static RAM of interference is read in a kind of minimizing of the present invention, when carrying out read operation, the signal among Fig. 3 on the RWL is " 1 ", and RBL is continued precharge, signal on the WL is " 0 ", the last nothing operation of BL, and the signal on the WLx is " 0 "; When carrying out write operation, the signal among Fig. 3 on the RWL is " 1 ", and the signal on the RBL is " 0 " or " 1 ", and the signal on the WL is " 1 ", and the signal on the BL is " 0 " or " 1 ", and the signal on the WLx is " 1 "; When storer carried out the state maintenance, the signal among Fig. 3 on the RWL was " 0 ", and the signal on the RBL is " 1 ", and the signal on the WL is " 0 ", and the signal on the BL is " 1 ", and the signal on the WLx is " 1 ".
Please refer to Fig. 5, Fig. 5 is the first embodiment analysis diagram of a kind of minimizing of the present invention static RAM of reading interference, among Fig. 5, starting condition is: the voltage (curve C among Fig. 5) that point 1 (referring to Fig. 3) locates is " 0V ", and promptly signal is " 0 ", and the voltage (curve D among Fig. 5) that point 2 (referring to Fig. 3) locate is " 1.2V ", be that signal is " 1 ", to between the general 4.4ns, the signal on the WLx (curve A among Fig. 5) is " 0 " at 1ns, and the signal on the RWL (curve B among the figure) is " 1 ".At last, please refer to Fig. 6, Fig. 6 is the second embodiment analysis diagram of a kind of minimizing of the present invention static RAM of reading interference, and among Fig. 6, starting condition is: the voltage (curve C among Fig. 6) that point 1 (referring to Fig. 3) locates is " 1.2V ", be that signal is " 1 ", the voltage (curve D among Fig. 6) that point 2 (referring to Fig. 3) locate is " 0V ", and promptly signal is " 0 ", between the extremely general 4.4ns of 1ns, signal on the WLx (curve A among Fig. 6) is " 0 ", and the signal on the RWL (curve B among Fig. 6) is " 1 ".Above-mentioned two kinds of situations all are to take place under the read operation situation, and the signal on the WLx is " 0 ", promptly in reading process, when using the 2nd NMOS pipe and the 4th NMOS pipe to carry out read operation, close the 5th NMOS pipe, block the electric current of this circuit, thereby avoided reading the generation of interference.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Have in the technical field of the present invention and know the knowledgeable usually, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (7)
1. the static RAM of interference is read in a minimizing, comprising:
The one CMOS phase inverter is made up of NMOS pipe and the 2nd PMOS pipe;
The 2nd CMOS phase inverter is made up of the 2nd NMOS pipe and the 2nd PMOS pipe, and a described CMOS phase inverter and described the 2nd CMOS phase inverter cross-couplings form trigger flip-flop;
The 3rd NMOS pipe, the drain electrode of the source electrode of described the 3rd NMOS pipe and a described PMOS pipe, the source electrode of a described NMOS pipe all link to each other;
The 4th NMOS pipe, the drain electrode of the source electrode of described the 4th NMOS pipe and described the 2nd PMOS pipe, the source electrode of described the 2nd NMOS pipe all link to each other;
It is characterized in that:
Described static RAM also comprises the 5th NMOS pipe, and the source electrode of described the 5th NMOS pipe links to each other with the drain electrode of a described NMOS pipe, and the drain electrode of described the 5th NMOS pipe connects low level.
2. the static RAM of interference is read in minimizing according to claim 1, it is characterized in that: the source electrode of a described PMOS pipe links to each other with the source electrode of described the 2nd PMOS pipe.
3. the static RAM of interference is read in minimizing according to claim 1 and 2, it is characterized in that: the source electrode of the source electrode of a described PMOS pipe and described the 2nd PMOS pipe all is connected high level.
4. the static RAM of interference is read in minimizing according to claim 1, it is characterized in that: the source electrode of described the 3rd metal-oxide-semiconductor links to each other with the grid of described the 2nd PMOS pipe.
5. the static RAM of interference is read in minimizing according to claim 1, it is characterized in that: the source electrode of described the 3rd metal-oxide-semiconductor links to each other with the grid of described the 2nd NMOS pipe.
6. the static RAM of interference is read in minimizing according to claim 1, it is characterized in that: the drain electrode of described the 2nd PMOS pipe links to each other with the source electrode of described the 2nd NMOS pipe.
7. the static RAM of interference is read in minimizing according to claim 1, it is characterized in that: the drain electrode of described the 2nd NMOS pipe connects low level.
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| CN2010101873755A CN102034531A (en) | 2010-05-28 | 2010-05-28 | Static random access memory for reducing reading interference |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117653A (en) * | 2011-03-15 | 2011-07-06 | 上海宏力半导体制造有限公司 | Static random-access memory |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
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| CN1408118A (en) * | 2000-03-03 | 2003-04-02 | 睦塞德技术公司 | Improved high density memory cell |
| WO2005041203A1 (en) * | 2003-10-27 | 2005-05-06 | Nec Corporation | Semiconductor storage device |
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2010
- 2010-05-28 CN CN2010101873755A patent/CN102034531A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1408118A (en) * | 2000-03-03 | 2003-04-02 | 睦塞德技术公司 | Improved high density memory cell |
| WO2005041203A1 (en) * | 2003-10-27 | 2005-05-06 | Nec Corporation | Semiconductor storage device |
Non-Patent Citations (1)
| Title |
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| HIEP TRAN: "Demonstration of 5T SRAM And 6T Dual-Port RAM Cell Arrays", 《IEEE1996 SYMPOSIUM ON VLSL CIRCUITS DIGEST OF TECHNICAL PAPERS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117653A (en) * | 2011-03-15 | 2011-07-06 | 上海宏力半导体制造有限公司 | Static random-access memory |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
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