CN109903796B - 10-tube storage unit adopting P-P-N and P-N-N mixed structure - Google Patents

Abstract

The invention discloses a 10-transistor storage unit adopting a P-P-N and P-N-N mixed structure, which comprises a bit line, a reverse phase line, a word line, a writing line, a P-N-N type phase inverter, a P-P-N type phase inverter and a read-write selection circuit, wherein the P-N-N type phase inverter comprises a first MOS transistor, a second MOS transistor and a third MOS transistor, the first MOS transistor is a P-type MOS transistor, the P-P-N type phase inverter comprises a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor, and the read-write selection circuit comprises a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor and a tenth MOS transistor; the method has the advantages of high read-write noise tolerance, low noise interference during read-write process and high stability.

Description

10-tube storage unit adopting P-P-N and P-N-N mixed structure

Technical Field

The invention relates to a storage unit, in particular to a 10-tube storage unit adopting a P-P-N and P-N-N mixed structure.

Background

In modern chip design, low power consumption has become a design goal of equal importance to area and performance. Reducing the operating voltage of the chip is the most direct and effective method for reducing the power consumption of the chip, but too low operating voltage not only affects the performance of the chip, but also reduces the stability of the chip. Memory, as one of the important components of a chip, usually dominates the power consumption of the whole chip, and its operating voltage has become a bottleneck to reduce the operating voltage of the chip.

6T-SRAMAs the most common memory technology, it has been working for many years for the entire integrated circuit industry. The 6T-SRAM adopts a classical 6-tube storage unit structure, so that the whole SRAM has a very small area and a very fast data access speed. Therefore, it is not a choice for storage in portable low-power electronic products such as high-speed Buffer inside the processor, Buffer of hard disk connection interface, mobile phone chip, network communication equipment, and portable computer. However, due to the read and write mutual constraint problem of the circuit, the read-destroy phenomenon is easy to occur, and the circuit is difficult to operate under the voltage lower than 0.7V. Therefore, when designing low voltage SRAM, designers prefer to use other memory cells with new structures to implement SRAM design. For example, in 2007, L.Chang published in the article "A5.3 GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS" in the conference "Symposium on VLSI: Technology Paper", which proposes a single-ended 8-transistor memory cell, and a 32kbits 8T-SRAM manufactured by 65nm Technology using the single-ended 8-transistor memory cell can operate at a voltage of 0.41V at the lowest and has an operating frequency of 295 MHz; in 2011, the article "A Large σ V" was published by the author J.J.Wu in the Journal of Solid-State Circuits_THThe article provides a differential 8-tube storage unit, a 32kbits differential 8T-SRAM manufactured by adopting a 65nm process, and the minimum working voltage of the differential 8T-SRAM can be as low as 430 mV; in 2012, the author J.P.Kulkarni published an article "ultra-low-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design" in the journal "IEEE Transactions on Green Large Scale Integration (VLSI) Systems", which proposes a Schmidt-structured differential 10-transistor memory cell, a 2kbits Schmidt 10T-SRAM fabricated by 130nm technology, the minimum operating Voltage of which is 320 mV.

Although the novel memory cells can work under the subthreshold voltage, the lowest working voltage of the novel memory cells is about 0.4V, a read/write auxiliary circuit is needed to assist, and once the read/write auxiliary circuit is lost, the novel memory cells are easily interfered by noise, so that read/write failure is caused.

Disclosure of Invention

The invention aims to solve the technical problem of providing a 10-tube storage unit which has higher read-write noise tolerance, is not easily interfered by noise in the read-write process and has higher stability and a P-P-N and P-N-N mixed structure.

The technical scheme adopted by the invention for solving the technical problems is as follows: a10-transistor memory cell adopting a P-P-N and P-N-N mixed structure comprises a bit line, a phase inversion line, a word line, a write word line, a P-N-N type inverter, a P-P-N type inverter and a read-write selection circuit; the P-N-N type phase inverter comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the first MOS tube is a P-type MOS tube, the second MOS tube and the third MOS tube are both N-type MOS tubes, the source electrode of the first MOS tube is connected with a power supply, the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the connecting end of the first MOS tube is the output end of the P-N-N type phase inverter, the output end of the P-N-N type phase inverter is a first storage node of the 10-tube storage unit, the grid electrode of the first MOS tube is connected with the grid electrode of the third MOS tube, the connecting end of the first MOS tube is the input end of the P-N-N type phase inverter, the grid electrode of the second MOS tube is the isolating end of the P-N-N type phase inverter, the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube, and the connecting end of the second MOS tube is the P-N-N type phase inverter The source electrode of the third MOS tube is grounded; the P-P-N type phase inverter comprises a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, wherein the fourth MOS tube and the fifth MOS tube are both P-type MOS tubes, the sixth MOS tube is an N-type MOS tube, a source electrode of the fourth MOS tube is connected with a power supply, a grid electrode of the fourth MOS tube is connected with a grid electrode of the sixth MOS tube, a connecting end of the grid electrode is an input end of the P-P-N type phase inverter, a grid electrode of the fifth MOS tube is an isolating end of the P-P-N type phase inverter, a drain electrode of the fourth MOS tube is connected with a source electrode of the fifth MOS tube, a connecting end of the drain electrode is a stacking node of the P-P-N type phase inverter, a drain electrode of the fifth MOS tube is connected with a drain electrode of the sixth MOS tube, and a connecting end of the drain electrode is an output end of the P-P-N type phase inverter, the output end of the P-P-N type phase inverter is a second storage node of the 10-transistor storage unit, and the source electrode of the sixth MOS transistor is grounded; the input end of the P-P-N type phase inverter is connected with a first storage node of the 10-tube storage unit, the input end of the P-N-N type phase inverter is connected with a second storage node of the 10-tube storage unit, the isolation end of the P-N type phase inverter is connected with the stacking node of the P-P-N type phase inverter, and the isolation end of the P-P-N type phase inverter is connected with the stacking node of the P-N-N type phase inverter; the read-write selection circuit comprises a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube, wherein the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are all N-type MOS tubes, a grid electrode of the seventh MOS tube and a grid electrode of the eighth MOS tube are all connected with the write word line, a source electrode of the seventh MOS tube and a source electrode of the ninth MOS tube are respectively connected with the bit line, a drain electrode of the seventh MOS tube is connected with the first storage node of the 10-tube storage unit, a drain electrode of the ninth MOS tube is connected with the stacking node of the P-N-N inverter, a grid electrode of the ninth MOS tube and a grid electrode of the tenth MOS tube are both connected with the word line, and a source electrode of the eighth MOS tube and a source electrode of the tenth MOS tube are both connected with the anti-phase line, the drain electrode of the eighth MOS tube is connected with the stacking node of the P-P-N type phase inverter, and the drain electrode of the tenth MOS tube is connected with the second storage node of the 10-tube storage unit.

Compared with the prior art, the invention has the advantages that a 10-transistor storage unit is formed by a bit line, a phase inversion line, a word line, a write word line, a P-N type inverter, a P-P-N type inverter and a read-write selection circuit, a pull-up network of the P-N type inverter consists of a P type MOS transistor (a first MOS transistor), a pull-down network consists of two stacked N type MOS transistors (a second MOS transistor and a third MOS transistor), a pull-up network of the P-P-N type inverter consists of two stacked P type MOS transistors (a fourth MOS transistor and a fifth MOS transistor), a pull-down network consists of an N type MOS transistor (a sixth MOS transistor), the P-N type inverter and the P-P-N type inverter are mutually cross-coupled to form a storage core of the storage unit, the output end of the P-N type inverter is a first storage node of the storage unit, the input end of the P-P-N type phase inverter is connected with a first storage node of the storage unit, the output end of the P-P-N type phase inverter is a second storage node of the storage unit, the input end of the P-N type phase inverter is connected with the second storage node of the storage unit, the isolation end of the P-N type phase inverter is connected with the stacking node of the P-P-N type phase inverter, the isolation end of the P-P-N type phase inverter is connected with the stacking node of the P-N-N type phase inverter, the read-write selection circuit consists of four N type MOS (a seventh MOS, an eighth MOS, a ninth MOS and a tenth MOS), the grid electrode of the seventh MOS is connected with the grid electrode of the eighth MOS by a write word line, the source electrode of the seventh MOS is connected with the source electrode of the ninth MOS by a bit line, the drain electrode of the seventh MOS tube is connected with the first storage node of the 10-tube storage unit, the drain electrode of the ninth MOS tube is connected with the stacking node of the P-N-N type phase inverter, the grid electrode of the ninth MOS tube and the grid electrode of the tenth MOS tube are both connected with the word line, the source electrode of the eighth MOS tube and the source electrode of the tenth MOS tube are both connected with the anti-phase line, the drain electrode of the eighth MOS tube is connected with the stacking node of the P-P-N type phase inverter, the drain electrode of the tenth MOS tube is connected with the second storage node of the 10-tube storage unit, the seventh MOS tube and the eighth MOS tube provide a read path for the 10-tube storage unit, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube together provide a write path for the 10-tube storage unit, when the 10-tube storage unit is in a non-working state, the write word line WWL and the word line WL are both turned off, and the first storage node and the second storage node are mutually, the stacked node of the P-N inverter and the stacked node of the P-N inverter are also interlocked with each other, thereby ensuring that a positive feedback loop normally operates, thereby achieving the retention of stored data, when the memory cell is in a write operation state, the write word line WWL and the word line WL are all turned on (set to "1"), the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are all in an on state, when a write "0" operation is performed, the bit line BL is "0", and the inverted BLB is "1", the first memory node of the 10-transistor memory cell and the stacked node of the P-N inverter are pulled down to "0", then the second memory node of the 10-transistor memory cell and the stacked node of the P-N inverter are precharged to "1" through the positive feedback loop, when a write "1" operation is performed, bit line BL is "1" and inverted BLB is "0", the second storage node of 10-T memory cell and the stacked node of P-P-N inverter are pulled down to "0", then the first storage node of 10-T memory cell and the stacked node of P-N-N inverter are precharged to "1" through positive feedback loop, the write "0" and the write "1" operation of 10-T memory cell are completely mirror symmetric, the double differential write operation mode greatly improves the write noise tolerance of 10-T memory cell, when the memory cell is in read operation state, word line WL is turned on, write word line WWL is turned off, ninth MOS transistor and tenth MOS transistor are in open state, bit line BL and inverted phase line BLB are precharged to "1" and float, when 10-T memory cell performs read "0" operation, inverted phase line BLB keeps the original "1" level, the bit line BL is pulled down to a low level through the ninth MOS transistor and the third MOS transistor, so that a voltage difference is formed between the bit line BL and the inverted phase line BLB, when the 10-transistor memory cell executes a read 1 operation, the bit line BL keeps the original 1 level, the inverted phase line BLB is pulled down to a low level through the tenth MOS transistor and the sixth MOS transistor, and a voltage difference is formed between the bit line BL and the inverted phase line BLB, because a read current path is isolated from a first memory node of the memory cell and a stacked node of the P-N-N inverter in the whole read operation process, the read damage can not occur, namely, the circuit eliminates the read damage and has a high read noise tolerance, therefore, the invention uses a double-differential write operation mode and a single-differential read operation mode, has a very high read-write noise tolerance and is not easily interfered by noise in the read-write process, the stability is higher, can work at lower subthreshold voltage.

Drawings

FIG. 1 is a circuit diagram of a 10-transistor memory cell of the present invention;

FIG. 2 is a schematic circuit diagram of a 10-transistor memory cell according to the present invention during a write operation;

FIG. 3 is a circuit diagram of a 10-transistor memory cell according to the present invention during a read operation.

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.

Example (b): as shown in FIG. 1, a 10-transistor memory cell with a P-P-N and P-N-N mixed structure comprises a bit line BL, a bit bar line BLB, a word line WL, a write word line WWL, a P-N-N inverter 1, a P-P-N inverter 2 and a read-write selection circuit; the P-N-N type inverter 1 comprises a first MOS tube M1, a second MOS tube M2 and a third MOS tube M3, wherein the first MOS tube M1 is a P-type MOS tube, the second MOS tube M2 and the third MOS tube M3 are both N-type MOS tubes, the source electrode of the first MOS tube M1 is connected with a power supply, the drain electrode of the first MOS tube M1 is connected with the drain electrode of the second MOS tube M2, the connection end of the first MOS tube M2 is the output end of the P-N-N type inverter 1, the output end of the P-N-N type inverter 1 is a first storage node T1 of a 10-tube storage unit, the grid electrode of the first MOS tube M1 is connected with the grid electrode of the third MOS tube M3, the connection end of the first MOS tube M3 is the input end of the P-N-N type inverter 1, the grid electrode of the second MOS tube M2 is the isolation end of the P-N-N type inverter 1, the source electrode of the second MOS tube M2 and the drain electrode of the third MOS tube M3 are connected with the P-N type inverter 2, the source electrode of the third MOS tube M3 is grounded; the P-P-N type inverter 2 comprises a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube, wherein the fourth MOS tube M4 and the fifth MOS tube M5 are both P type MOS tubes, the sixth MOS tube M4834 is an N type MOS tube, the source of the fourth MOS tube M4 is connected with a power supply, the grid of the fourth MOS tube M4 is connected with the grid of the sixth MOS tube M6, the connection end of the fourth MOS tube M5 is the input end of the P-P-N type inverter 2, the grid of the fifth MOS tube M5 is the isolation end of the P-P-N type inverter 2, the drain of the fourth MOS tube M4 is connected with the source of the fifth MOS tube M5, the connection end of the fifth MOS tube M3 is the stacked node of the P-P-N type inverter 2, the drain of the fifth MOS tube M5 is connected with the drain of the sixth MOS tube M6, the connection end of the stacked node T3 is the output end of the P-P-N type inverter 2, the output end of the P-N type inverter 2 is the second storage node T84, the source electrode of the sixth MOS transistor M6 is grounded; the input end of the P-P-N type inverter 2 is connected with a first storage node T1 of the 10-transistor storage unit, the input end of the P-N-N type inverter 1 is connected with a second storage node T4 of the 10-transistor storage unit, the isolation end of the P-N type inverter 1 is connected with a stacking node T3 of the P-P-N type inverter 2, and the isolation end of the P-P-N type inverter 2 is connected with a stacking node T2 of the P-N-N type inverter 1; the read-write selection circuit comprises a seventh MOS transistor, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, a seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10 are all N-type MOS transistors, the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8 are all connected to a word line WWL, the source of the seventh MOS transistor M7 and the source of the ninth MOS transistor M9 are respectively connected to a bit line BL, the drain of the seventh MOS transistor M7 and the first storage node T1 of the 10-transistor memory cell are connected, the drain of the ninth MOS transistor M9 and the stacking node T2 of the P-N inverter 1 are connected, the gate of the ninth MOS transistor M9 and the gate of the tenth MOS transistor M10 are all connected to a word line WL, the source of the eighth MOS transistor M8 and the source of the tenth MOS transistor M10 are all connected to an inverted phase line BLB, the drain of the eighth MOS transistor M8 and the drain of the tenth MOS transistor M10 are connected to the stacking node T3 of the P-N inverter 2, and the drain of the tenth MOS transistor M10 and the second storage node T4 are connected.

The read-write working principle of the 10-tube storage unit adopting the P-P-N and P-N mixed structure is as follows:

as shown in fig. 2, when the memory cell performs a write operation, the write word line WWL and the word line WL are all turned on (set to "1"), the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10 are all in an open state, when the write "0" operation is performed, the bit line BL is "0" and the inverted BLB is "1", the first storage node T1 of the 10-transistor memory cell and the stacked node T2 of the P-N inverter are pulled down to "0", then the second storage node T4 of the 10-transistor memory cell and the stacked node T3 of the P-N inverter are precharged to "1" through a positive feedback loop, when the write "1" operation is performed, the bit line BL is "1" and the inverted BLB is "0", the second storage node T4 of the 10-transistor memory cell and the stacked node T3 of the P-N inverter are pulled down to "0", then the first storage node T1 of the 10-tube storage unit and the stacked node T2 of the P-N-N type inverter are precharged to '1' through a positive feedback loop, the writing '0' and the writing '1' of the 10-tube storage unit are completely mirror-symmetrical, and the double-differential writing operation mode greatly improves the writing noise tolerance of the 10-tube storage unit.

As shown in fig. 3, when the memory cell performs a read operation, the word line WL is turned on, the write word line WWL is turned off, the ninth MOS transistor M9 and the tenth MOS transistor M10 are in an open state, the bit line BL and the bit bar line BLB are precharged to "1" and floated, when the 10-transistor memory cell performs a read "0" operation, the bit bar line BLB maintains the original "1" level, and the bit line BL is pulled down to a low level through the ninth MOS transistor M9 and the third MOS transistor M3, resulting in a voltage difference between the bit line BL and the bit bar line BLB, when the 10-transistor memory cell performs a read "1" operation, the bit line BL maintains the original "1" level, and the bit bar line BLB is pulled down to a low level through the tenth MOS transistor M10 and the sixth MOS transistor M6, resulting in a voltage difference between the bit line BL and the bit bar line BLB, since the read current path is isolated from the stacked node of the first memory node and the P-N inverter of the memory cell during the entire read operation, therefore, the read corruption can not occur, the read corruption is eliminated, and the read noise tolerance is higher.

Claims (1)

1. A10-transistor memory cell adopting a P-P-N and P-N-N mixed structure is characterized by comprising a bit line, a reverse phase line, a word line, a write word line, a P-N-type inverter, a P-P-N-type inverter and a read-write selection circuit;

the P-N-N type phase inverter comprises a first MOS tube, a second MOS tube and a third MOS tube, wherein the first MOS tube is a P-type MOS tube, the second MOS tube and the third MOS tube are both N-type MOS tubes, the source electrode of the first MOS tube is connected with a power supply, the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the connecting end of the first MOS tube is the output end of the P-N-N type phase inverter, the output end of the P-N-N type phase inverter is a first storage node of the 10-tube storage unit, the grid electrode of the first MOS tube is connected with the grid electrode of the third MOS tube, the connecting end of the first MOS tube is the input end of the P-N-N type phase inverter, the grid electrode of the second MOS tube is the isolating end of the P-N-N type phase inverter, the source electrode of the second MOS tube is connected with the drain electrode of the third MOS tube, and the connecting end of the second MOS tube is the P-N-N type phase inverter The source electrode of the third MOS tube is grounded;

the P-P-N type phase inverter comprises a fourth MOS tube, a fifth MOS tube and a sixth MOS tube, wherein the fourth MOS tube and the fifth MOS tube are both P-type MOS tubes, the sixth MOS tube is an N-type MOS tube, a source electrode of the fourth MOS tube is connected with a power supply, a grid electrode of the fourth MOS tube is connected with a grid electrode of the sixth MOS tube, a connecting end of the grid electrode is an input end of the P-P-N type phase inverter, a grid electrode of the fifth MOS tube is an isolating end of the P-P-N type phase inverter, a drain electrode of the fourth MOS tube is connected with a source electrode of the fifth MOS tube, a connecting end of the drain electrode is a stacking node of the P-P-N type phase inverter, a drain electrode of the fifth MOS tube is connected with a drain electrode of the sixth MOS tube, and a connecting end of the drain electrode is an output end of the P-P-N type phase inverter, the output end of the P-P-N type phase inverter is a second storage node of the 10-transistor storage unit, and the source electrode of the sixth MOS transistor is grounded;

the input end of the P-P-N type phase inverter is connected with a first storage node of the 10-tube storage unit, the input end of the P-N-N type phase inverter is connected with a second storage node of the 10-tube storage unit, the isolation end of the P-N type phase inverter is connected with the stacking node of the P-P-N type phase inverter, and the isolation end of the P-P-N type phase inverter is connected with the stacking node of the P-N-N type phase inverter;

the read-write selection circuit comprises a seventh MOS tube, an eighth MOS tube, a ninth MOS tube and a tenth MOS tube, wherein the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are all N-type MOS tubes, a grid electrode of the seventh MOS tube and a grid electrode of the eighth MOS tube are all connected with the write word line, a source electrode of the seventh MOS tube and a source electrode of the ninth MOS tube are respectively connected with the bit line, a drain electrode of the seventh MOS tube is connected with the first storage node of the 10-tube storage unit, a drain electrode of the ninth MOS tube is connected with the stacking node of the P-N-N inverter, a grid electrode of the ninth MOS tube and a grid electrode of the tenth MOS tube are both connected with the word line, and a source electrode of the eighth MOS tube and a source electrode of the tenth MOS tube are both connected with the anti-phase line, the drain electrode of the eighth MOS tube is connected with the stacking node of the P-P-N type phase inverter, and the drain electrode of the tenth MOS tube is connected with the second storage node of the 10-tube storage unit.

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