CN102023811B - Method and system for issuing programmatic instructions to flash memory - Google Patents

Abstract

The embodiment of the invention provides a method, a controller and a storage system for issuing a programming command to a flash memory. The method includes receiving a plurality of host write commands and write data corresponding to the host write commands from a host system using a Native Command Queuing (NCQ) protocol, and issuing a cache program Command to the flash memory chip to write the write data into the flash memory chip. Therefore, the time for executing the host write command can be effectively shortened by only using the cache program command and the native instruction sorting protocol to execute the data write.

Description

Method and system for issuing programmatic instructions to flash memory

technical field

The invention relates to a method for issuing programming instructions to a flash memory, a flash memory controller and a flash memory storage system using the method. the

Background technique

Because flash memory (Flash Memory) has the characteristics of data non-volatility, power saving, small size and no mechanical structure, it is most suitable for use in portable electronic products. For example, a solid state disk is a storage device using NAND flash memory as a storage medium, and has been widely deployed in notebook computers as a main storage device. the

FIG. 1 is a schematic block diagram illustrating a general flash storage device. In general, when the host system 110 is electrically connected to the flash storage device through the connector 122 and intends to store data in the flash storage device 120, the process of writing data to the flash memory module 126 of the flash storage device 120 can be divided into data transmission. (transfer) and data programming (program) two parts. Specifically, when the host system 110 intends to store data in the flash storage device 120, the flash controller 124 will transmit the data to the buffer 132 in the flash memory module 126 through the data input/output bus 128, and then the flash memory module 126 will The data in the buffer 132 is programmed to the memory (i.e., the storage area) 134 of the flash memory module 126, wherein the flash memory module 126 is in an actual busy (busy) state while the flash memory module 126 is programming data to the memory 134, And when the flash memory module 126 is actually in a busy state, the flash memory controller 124 cannot issue any instructions or transmit any data to it. That is to say, the flash memory controller 124 can respond to the host system 110 and process the next command of the host system 110 only after the flash memory module 126 is programmed. the

Specifically, when the flash memory controller 124 receives the host write command and write data from the host system 110 and needs to write the write data to the flash memory module 126, the flash memory controller 124 will issue a command via the data input/output bus 128. programming instructions, and the relevant information in the programming instructions will be temporarily stored in the buffer 132 . For example, the programmed command is composed of character strings such as "command W1", "physical address", "write data" and "command W2", wherein the flash memory controller 124 instructs the flash memory module 126 to prepare to execute The programming procedure indicates the address of the flash memory module 126 to be programmed by "physical address", the data to be programmed by the flash memory module 126 by "write data" and the flash memory module 126 to start programming by "command W2". Therefore, when the flash memory module 126 starts to write the data in the buffer 132 to the memory 134 according to the "command W2" in the programming instruction, the flash memory controller 124 needs to receive the confirmation from the flash memory module 126 that the programming is completed ( acknowl edgement) information, the host system 110 will be replied. Generally speaking, the time from when the host system issues an instruction to when the host system receives the acknowledgment information is called response time (response time). the

With the development of transmission technology, the transmission speed of connectors has been greatly improved. For example, Serial Advanced Technology Attachment (SATA) connectors can reach 1.5 billion bits per second (Gigabit, Gb), or even 30Gb per second. . However, the speed of the above-mentioned programmable flash memory is far lower than the speed of the connector, and the performance of the overall storage cannot be effectively improved. Therefore, how to shorten the time for executing the host write command is the goal of those skilled in the art. the

Contents of the invention

The invention provides a method for issuing programmed instructions, which can effectively shorten the time for executing the write instructions of the host. the

The present invention provides a flash memory controller, which can effectively shorten the time for executing a host write command. the

The invention provides a flash memory storage system, which can effectively shorten the time for executing a host write command. the

Exemplary embodiments of the present invention provide a method for issuing programming instructions for writing data from a host system into a flash memory chip. The method for issuing programmed commands includes providing a flash controller, and the flash controller receives a plurality of host write commands from the host system using a native command queuing (Native Command Queuing, NCQ) protocol. The method for issuing programmed instructions also includes that the flash memory controller transmits an instruction sequence to the host system according to the host write instruction. The method for issuing programming commands also includes sequentially receiving the host write command and a plurality of write data corresponding to the host write command from the host system according to the command order, and issuing a cache programming command to the flash memory chip respectively. command to write the write data into the flash memory chip. the

Exemplary embodiments of the present invention provide a flash memory controller for writing data from a host system into a flash memory chip. The flash memory controller includes a microprocessor unit, a buffer memory, a flash memory interface unit, a host interface unit and a memory management unit. The flash memory interface unit is electrically connected to the microprocessor unit and used for connecting the flash memory chip. The buffer memory is electrically connected to the microprocessor unit. The host interface unit is electrically connected to the microprocessor unit and used to connect to the above-mentioned host system, wherein the host interface unit supports the NCQ protocol. The memory management unit is electrically connected to the micro-processing unit, and is used for receiving a plurality of host write commands from the host system through the host interface unit using the NCQ protocol. In addition, the memory management unit transmits a command sequence to the host system through the host interface unit according to the host write command. Furthermore, the memory management unit sequentially receives the host write command and a plurality of write data corresponding to the host write command from the host system through the host interface unit according to the command order, and issues cache programs to the flash memory chip respectively. Write instructions to write the write data into the flash memory chip. the

Exemplary embodiments of the present invention provide a flash storage system for storing data from a host system. The flash memory storage system includes a connector, a flash memory chip and a flash memory controller for electrically connecting the above-mentioned host system, wherein the connector supports the NCQ protocol. The flash memory controller is electrically connected to the connector and the flash memory chip, and used for receiving a plurality of host write commands from the host system through the connector using the NCQ protocol. In addition, the flash memory controller transmits a command sequence to the host system according to the host write command. Furthermore, the flash memory controller sequentially receives the host write command and a plurality of write data corresponding to the host write command from the host system through the connector according to the order of issuing the above commands, and issues a cache memory to the flash memory chip respectively. Program instructions to write write data into the flash memory chip. the

Based on the above, the method for issuing programming instructions, the flash memory controller and the flash memory storage system of the exemplary embodiments of the present invention can effectively shorten the execution time of the host write instruction, thereby improving the performance of data access. the

The present invention will be described in further detail below through specific embodiments and in conjunction with the accompanying drawings. the

Description of drawings

Figure 1 is a schematic block diagram illustrating a general flash memory storage system;

2A is a diagram illustrating a host system using a flash memory storage device according to an embodiment of the present invention;

2B is a schematic diagram of a computer, an input/output device, and a flash storage device according to an exemplary embodiment of the present invention;

2C is a schematic diagram of a host system and a flash storage device according to another exemplary embodiment of the present invention;

2D is a schematic block diagram of a flash memory storage device illustrated according to an exemplary embodiment of the present invention;

3 is a schematic block diagram of a flash memory die illustrated according to an exemplary embodiment of the present invention;

FIG. 4A is a schematic diagram of an example of a flash memory controller issuing cache programming instructions through a data input/output bus according to an exemplary embodiment of the present invention;

FIG. 4B is an operation timing diagram of the illustrated flash memory chip according to the instruction shown in FIG. 4A;

FIG. 5 is a flowchart illustrating issuing a programmatic instruction according to an exemplary embodiment of the present invention. the

Explanation of reference signs:

110: host system; 120: flash storage device;

122: connector; 124: flash memory controller;

126: Flash memory module; 128: Data input/output bus;

132: Buffer; 134: Memory;

200: flash storage device; 202: connector;

204: flash controller; 206: microprocessor unit;

208: memory management unit; 210: host interface unit;

212: Flash memory interface unit; 214: Buffer memory;

220: flash memory chip; 290: host system;

295: bus; 300: 0th flash memory module;

302: the 0th data input/output bus; 310: the 1st flash memory module;

312: the first data input/output bus; 320: the second flash memory module;

322: the second data input/output bus; 330: the third flash memory module;

332: the third data input/output bus; 340: the fourth flash memory module;

342: the 4th data input/output bus; 350: the 5th flash memory module;

352: the fifth data input/output bus; 360: the sixth flash memory module;

362: the sixth data input/output bus; 370: the seventh flash memory module;

372: the 7th data input/output bus; 400: the 0th flash memory die;

402: storage area; 404: first buffer zone;

406: the second buffer zone; 410: the first flash memory die;

420: the second flash memory die; 430: the third flash memory die;

440: the fourth flash memory die; 450: the fifth flash memory die;

460: the sixth flash memory die; 470: the seventh flash memory die;

480: the 8th flash memory die; 490: the 9th flash memory die;

500: the 10th flash memory die; 510: the 11th flash memory die;

520: the 12th flash memory die; 530: the 13th flash memory die;

540: the 14th flash memory grain; 550: the 15th flash memory grain;

1100: computer; 1102: microprocessor;

1104: random access memory; 1106: input/output device;

1108: system bus; 1110: data transmission interface;

1202: mouse; 1204: keyboard;

1206: monitor; 1208: printer;

1212: flash drive; 1214: memory card;

1216: SSD; 1310: Digital camera;

1310a: SD card; 1310b: MMC card;

1310c: CF card; 1310d: memory stick;

1310e: embedded storage device; W1, W2, W3: instructions;

D1, D2, D3: data; ADD1, ADD2, ADD3: entity address;

CM1, CM2, CM3, CM4, CM5, CM6, CM7, CM8, CM9: instructions;

T1, T2, T3: data transmission; B1, B2, B3: busy time;

S501, S503, S505, S507, S509, S511, S513, S515, S517: the step of issuing a programming instruction. the

Detailed ways

A flash memory storage device generally includes a flash memory chip and a controller (also referred to as a control circuit). Typically, a flash storage device is used with a host system so that the host system can write data to or read data from the flash storage device. In addition, there are also flash storage devices that include embedded flash memory and software executable on a host system that essentially acts as a controller for the embedded flash memory. the

FIG. 2A illustrates a host system using a flash storage device according to an embodiment of the present invention. the

Referring to FIG. 2A , the host system 290 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 2B. It must be understood that the device shown in FIG. 2B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices. the

In the embodiment of the present invention, the flash storage device 200 is electrically connected with other components of the host system 290 through the data transmission interface 1110 . Data can be written into or read from the flash storage device 200 through the processing of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the flash storage device 200 may be a flash drive 1212, a memory card 1214 or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 2B. the

In general, host system 290 can be virtually any system that can store data. Although in this exemplary embodiment, the host system 290 is illustrated as a computer system, however, in another exemplary embodiment of the present invention, the host system 290 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the flash storage device is an SD card 1310a, an MMC card 1310b, a CF card 1310c, a memory stick (memory stick) 1310d or an embedded storage device 1310e (such as Figure 2C). The embedded storage device 1310e includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system. the

FIG. 2D is a detailed block diagram illustrating the flash storage device 200 shown in FIG. 2A . the

Referring to FIG. 2D , the flash storage device 200 includes a connector 202 , a flash controller 204 and a flash chip 220 . the

The connector 202 is electrically connected to the flash memory controller 204 and used for connecting to the host system 290 through the bus 295 . In this exemplary embodiment, the connector 202 is a Serial Advanced Technology Attachment (SATA) connector. In particular, the connector 202 supports the native command queuing (Native Command Queuing, NCQ) protocol, and the write command is transmitted between the host system 290 and the flash memory controller 204 using the NCQ protocol. Specifically, when the host system 290 and the flash memory controller 204 transmit host write commands with the NCQ protocol, the host system 290 will first transmit the multiple host write commands to be sent to the flash controller 204 together, and the flash memory The controller 204 responds to the host system 290 in response to its expected command sequence. In particular, the host system 290 only transmits the command to be issued to the flash memory controller 204 but does not transmit the data to be written. Afterwards, the host system 290 transmits the host write command and data according to the response of the flash controller 204, and the flash controller 204 responds to the host system 290 with the execution status of each write command after completing all the host write commands. In particular, when a programming error (program fail) occurs, the host system 290 will retransmit the instructions and data corresponding to the programming error to the flash controller 204 according to the report information (ie, execution status) of the flash controller 204 . Or, in another exemplary embodiment of the present invention, when a program fail occurs, the host system 290 will retransmit all instructions and data to the flash memory controller 204. the

In addition, it must be understood that, in the exemplary embodiment of the present invention, the connector 202 is a SATA connector supporting NCQ, but the present invention is not limited thereto, and the connector 202 may also be other connectors supporting the NCQ protocol. the

The flash memory controller 204 executes a plurality of logic gates or control commands implemented in hardware or firmware, and writes, reads, and erases data in the flash memory chip 220 according to the instructions of the host system 290 . The flash memory controller 204 includes a microprocessor unit 206 , a memory management unit 208 , a host interface unit 210 , a flash memory interface unit 212 and a cache memory 214 . the

The microprocessor unit 206 is the main control unit of the flash memory controller 204 , and cooperates with the memory management unit 208 , the host interface unit 210 , the flash memory interface unit 212 , and the buffer memory 214 to perform various operations of the flash memory storage device 200 . the

The memory management unit 208 is electrically connected to the microprocessor unit 206 for executing the programmed instructions and the block management mechanism according to the present exemplary embodiment. The operation of the memory management unit 208 will be described in detail below with reference to the drawings. the

In this exemplary embodiment, the memory management unit 208 is implemented in the flash memory controller 204 in the form of a firmware. For example, burn the memory management unit 208 including a plurality of control instructions into a program memory (for example, read only memory (Read Only Memory, ROM)) and embed this program memory in the flash memory controller 204, when the flash memory stores When the device 200 is running, a plurality of control commands of the memory management unit 208 will be executed by the microprocessor unit 206 to implement the programmed command and block management mechanism according to the embodiment of the present invention. the

In another exemplary embodiment of the present invention, the control instructions of the memory management unit 208 may also be stored in a specific area of the flash memory chip 220 (for example, a system area dedicated to storing system data in the flash memory chip) in the form of program code. Likewise, when the flash storage device 200 is operating, a plurality of control commands of the memory management unit 208 will be executed by the microprocessor unit 206 . In addition, in another exemplary embodiment of the present invention, the memory management unit 208 may also be implemented in the flash memory controller 204 in a hardware form. the

The host interface unit 210 is electrically connected to the microprocessor unit 206 and used for receiving and identifying instructions and data transmitted by the host system 290 . That is to say, the instructions and data sent by the host system 290 are sent to the microprocessor unit 206 through the host interface unit 210 . In this exemplary embodiment, the host interface unit 210 corresponds to the SATA interface of the connector 202 . However, it must be understood that the present invention is not limited thereto, and the host interface unit 210 may also be other suitable data transmission interfaces. the

The flash interface unit 212 is electrically connected to the microprocessor unit 206 and used for accessing the flash chip 220 . That is to say, the data to be written into the flash memory chip 220 will be converted into a format acceptable to the flash memory chip 220 through the flash memory interface unit 212 . the

The buffer memory 214 is electrically connected to the microprocessor unit 206 and used for temporarily storing data and instructions from the host system 290 or data from the flash chip 220 . the

In addition, although not shown in this exemplary embodiment, the flash memory controller 204 also includes general functional modules such as an error correction unit and a power management unit. the

The flash chip 220 is electrically connected to the flash controller 204 and used for storing data. The flash memory chip 220 includes the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, the 6th flash memory module 360 and the 7th flash memory module 370. In this exemplary embodiment, the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, the 6th flash memory module 360 and the 7. The flash memory module 370 is a multi-level memory (Multi LevelCell, MLC) NAND flash memory module. However, the present invention is not limited thereto, the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, the 6th flash memory module 360 and The seventh flash memory module 370 may also be a single-level memory (Single Level Cell, SLC) NAND flash memory module. the

In this exemplary embodiment, the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, the 6th flash memory module 360 and the 7. The flash memory modules 370 are electrically connected to the flash memory controller 204 respectively. Specifically, the flash memory interface unit 212 of the flash memory controller 204 passes through the 0th data input/output bus (Data input/output bus) 302, the first data input/output bus 312, and the second data input/output bus 322 respectively. , the 3rd data input/output bus 332, the 4th data input/output bus 342, the 5th data input/output bus 352, the 6th data input/output bus 362 and the 7th data input/output bus 372 transmit data to the 0th The flash memory module 300 , the first flash memory module 310 , the second flash memory module 320 , the third flash memory module 330 , the fourth flash memory module 340 , the fifth flash memory module 350 , the sixth flash memory module 360 and the seventh flash memory module 370 . the

In this exemplary embodiment, the 0th flash memory module 300 includes a 0th flash memory die 400 and a first flash memory die 410, and the first flash memory module 310 includes a second flash memory die 420 and a third flash memory die 430, The 2nd flash memory module 320 includes the 4th flash memory die 440 and the 5th flash memory die 450, the 3rd flash memory module 330 includes the 6th flash memory die 460 and the 7th flash memory die 470, the 4th flash memory module 340 includes the 8th flash memory die 480 and the 9th flash memory die 490, the 5th flash memory module 350 includes the 10th flash memory die 500 and the 11th flash memory die 510, the sixth flash memory module 360 includes the 12th flash memory die 520 and the 13th flash memory die 530 and The seventh flash memory module 370 includes a fourteenth flash memory die 540 and a fifteenth flash memory die 550 . the

It is worth mentioning that, in the exemplary embodiment of the present invention, the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, The 0th data input/output bus 302, the first data input/output bus 312, the second data input/output bus 322, the third The data input/output bus 332, the 4th data input/output bus 342, the 5th data input/output bus 352, the 6th data input/output bus 362 and the 7th data input/output bus 372, so the memory management unit 208 will use Parallel mode transmits write data to corresponding flash memory modules through multiple data input/output buses at the same time, so as to improve access speed. In addition, each flash memory module includes two flash memory dies, so the memory management unit 208 uses an interleave mode to interleave write data to the two flash memory dies in the same flash memory module to further increase access performance. In more detail, as mentioned above, the process of writing data in the flash memory grain includes two parts: data transfer and data programming (program), and the interleave mode (interleave mode) is to use the same data input In the example of two flash dies that transfer data via the I/O bus, data is transferred to the other flash die while one of the flash dies is performing data programming. the

FIG. 3 is a schematic block diagram of a flash memory die illustrated according to an exemplary embodiment of the present invention. Here, the 0th flash memory die 400, the first flash memory die 410, the second flash memory die 420, the third flash memory die 430, the fourth flash memory die 440, the fifth flash memory die 450, and the sixth flash memory die 460, the seventh flash memory die 470, the eighth flash memory die 480, the ninth flash memory die 490, the tenth flash memory die 500, the eleventh flash memory die 510, the twelfth flash memory die 520, and the thirteenth flash memory die 530 The structure and operation of the 14th flash memory die 540 and the 15th flash memory die 550 are the same, and only the 0th flash memory die 400 will be described below. the

Referring to FIG. 3 , the 0th flash die 400 includes a storage area 402 , a first buffer 404 and a second buffer 406 . the

The storage area 402 includes a plurality of physical blocks and is used for storing data. A physical block is the smallest unit of erasure. That is, each physical block contains the minimum number of memories that are erased together. Each physical block has several pages. In this exemplary embodiment, a page is the smallest unit of programming. In other words, a page is the smallest unit for writing data or reading data. Each page generally includes a user data area and a redundant area. The user data area is used to store user data, and the redundant area is used to store system data (for example, Error Checking and Correcting Code (ECC Code). 

It is worth mentioning that the 0th flash memory grain 400, the 1st flash memory grain 410, the 2nd flash memory grain 420, the 3rd flash memory grain 430, the 4th flash memory grain 440, the 5th flash memory grain 450, the 6th flash memory grain Flash memory grain 460, seventh flash memory grain 470, eighth flash memory grain 480, ninth flash memory grain 490, tenth flash memory grain 500, eleventh flash memory grain 510, twelfth flash memory grain 520, thirteenth flash memory The physical blocks in the die 530 , the 14th flash memory die 540 and the 15th flash memory die 550 are grouped into a plurality of physical units by the memory management unit 208 for writing, reading and erasing data. In particular, each physical unit is composed of physical blocks in a plurality of flash memory dies, so the memory management unit 208 uses the above-mentioned parallel mode and interleaved mode to improve the access speed. the

Furthermore, since the memory of the flash memory can only be programmed from "1" to "0", the data in the physical block must be erased first when updating the data in the physical block. However, the flash memory is written in units of pages and erased in units of physical blocks, so the physical blocks in the storage area 402 store data in an alternate manner. Specifically, the memory management unit 208 logically groups the grouped entity units into system area, data area, spare area and replacement area, wherein the grouping is system area, data area, spare area, and replacement area. The physical units in the area are used to store relevant important information of the flash storage device, and the physical units grouped into the replacement area are used to replace the damaged physical units in the data area or spare area. Therefore, in the normal access state, the host system 290 is unable to access the physical units in the system area and the replacement area. The data written by the host write command is stored in the physical units grouped into the data area, and the physical units in the spare area are used to replace the physical units in the data area when the host write command is executed. For example, when the flash storage device 200 receives a host write command from the host system 290 and intends to update (or write) data to a certain page of a physical unit in the data area, the memory management unit 208 will extract the data from the spare area. a physical unit and write valid old data and new data to be written in the physical unit to be updated into the physical unit extracted from the spare area, and write valid old data and new data to the physical unit It is logically associated as a data area, and the physical units to be updated in the data area are erased and logically associated as a spare area. In order to enable the host system 290 to smoothly access the physical units that store data in a rotating manner, the flash storage device 200 provides a logical address to the host system 290 . That is to say, the flash storage device 200 will reflect the physical unit by recording and updating the mapping relationship between the logical address and the physical unit in the data area in the logical address-physical address mapping table. Alternately, the host system 290 only needs to write to the provided logical address and the flash storage device 200 reads or writes data to the physical address of the corresponding physical unit according to the logical address-physical address mapping table. the

The first buffer 404 and the second buffer 406 are used to temporarily store data transmitted by the flash memory controller 204 . As mentioned above, the process of writing data in the 0th flash memory die 400 includes two parts: data transmission and data programming. In the part of data transmission, the flash memory controller 204 transmits the data to be written to the first buffer 404 , and then, the data to be written is moved to the second buffer 406 . In the part of data programming, the data to be written is written from the second buffer 406 to the storage area 402 . Here, the first buffer 404 is also referred to as a data cache (data cache) area, and the second buffer 406 is also referred to as a cache buffer (cache buffer), wherein the first buffer 404 and the second buffer 406 A page of write data can be temporarily stored to correspond to a programming unit (ie, a page). the

Specifically, when the memory management unit 208 receives the host write command and write data from the host system 290 and needs to write the write data to the 0th flash memory die 400, the memory management unit 208 will pass the flash memory interface unit 212 A programming instruction is issued with the data input/output bus 302, and the data to be written in the programming instruction is transferred from the buffer memory 214 to the first buffer 404, and then the data to be written will be transferred from the first buffer 404 is moved to the second buffer 406 , and finally, the data is programmed from the second buffer 406 to the storage area 402 . In particular, in this exemplary embodiment, the memory management unit 208 only uses programming instructions composed of character strings such as "command W1", "physical address", "write data" and "command W3" to program Data, wherein the memory management unit 208 instructs the 0th flash memory die 400 to prepare to execute the programming program through the "command W1", indicates the physical address of the 0th flash memory die 400 to be programmed through the "physical address", and passes the "write data" Indicate the data to be programmed by the 0th flash memory die 400 and instruct the 0th flash memory die 400 to start executing the cache program through the "command W3". Here, when the "command W3" in the programming command is used, the flash memory controller 204 will receive the acknowledgment from the 0th flash die 400 when the data has been moved from the first buffer 404 to the second buffer 406 information, and the next command can be processed. the

For example, in the example where the flash controller 204 receives two consecutive host write commands from the host system 290 using the NCQ protocol and needs to perform programming on two pages of the 0th flash die 400, since the 0th flash die 400 has two buffers (i.e., the first buffer 404 and the second buffer 406), so when the 0th flash die 400 has moved the data of the first host write command from the first buffer 404 to the 0th After the second buffer 406, the first buffer 404 can be cleared and receive the data of the second host write command. In particular, during the 0th flash memory die 400 is programming the write data of the first host write command from the second buffer 406 to the storage area 402, the first buffer 404 can be responsible for receiving the next programming The write data of the command (that is, the data of the second master write command). That is to say, by using "command W3", the memory management unit 208 can continue to process the second host write command without waiting for the 0th flash die 400 to complete the programming of the first host write command. command, and transmit the write data of the second host write command to the first buffer 404 . Therefore, the 0th flash memory die 400 can simultaneously execute the data programming of the write data of the first host write command and the data transmission of the write data of the second host command, thereby shortening the time for executing the host write command. . the

FIG. 4A is an exemplary schematic diagram of a flash memory controller illustrating a cache programming command through a data input/output bus according to an exemplary embodiment of the present invention, and FIG. 4B is a diagram of a flash memory chip illustrated according to the command shown in FIG. 4A Operation sequence diagram. In the example shown in FIG. 4A and FIG. 4B , the memory management unit 208 receives three host write commands from the host system 290 using the NCQ protocol. Here, the logical addresses to be written by the three host write commands are three consecutive logical addresses, and the memory management unit 208 will generate the instruction order according to the order of these logical addresses, so that the host system 290 can use the memory The command sequence generated by the management unit 208 is to issue the three host write commands, wherein the first host write command includes the logical address to be written and the data D1 to be written, and the second host write command includes The logical address to be written and the data to be written D2, the third host write command includes the logical address to be written and the data to be written D3, and these three host write commands are to be written in the logic The address is mapped to the physical block of the 0th flash memory die 400 . the

Please refer to FIG. 4A and FIG. 4B, when the memory management unit 208 of the flash memory controller 204 receives the first host write command and the data to be written from the host system 290 according to the command order, the memory management unit 208 According to the logical address in the first host write command and the data D1 to be written, it will issue a string consisting of "command W1", "ADD1", "data D1" and "command W3" to the flash memory chip 220 cache programming instructions (command CM1 , command CM2 , transfer T1 and command CM3 shown in FIG. 4A ), wherein “ADD1” represents the physical address of the programming data. That is to say, the memory management unit 208 will transmit the physical address corresponding to the logical address in the host write instruction to the 0th flash memory die 400 (that is, the instruction CM2) according to the logical address-physical address mapping table, and The data D1 is transmitted to the first buffer 404 (ie, T1 is transmitted). Afterwards, the 0th flash memory die 400 will move the data D1 from the first buffer 404 to the second buffer 406 according to the cache programming instruction (ie, the instruction CM3 ), and after completing the transfer of the data D1 from the first buffer 404 After moving to the second buffer 406 , program the data D1 from the second buffer 406 to the storage area 402 . In particular, when the 0th flash memory die 400 starts to execute the command CM3, the 0th flash memory die 400 will be in a busy state, and will resume after completing the transfer of the data D1 from the first buffer 404 to the second buffer 406 It is a ready state (ie, busy time B1). When the 0th flash memory die 400 returns to the standby state, the memory management unit 208 will respond to the host system 290, receive the second host write command and data D2 from the host system 290, and issue a command to the 0th flash memory die 400 The cache programming instructions (command CM4, command CM5, transmission T2 and command CM6 shown in FIG. The data D2 of the second host write command is transmitted to the first buffer 404 (ie, transmission T2). At this time, the data programming of the data D1 and the data transmission of the data D2 are performed simultaneously. That is to say, since there are two buffers (i.e., the first buffer 404 and the second buffer 406) in the 0th flash memory die 400, the data to be written is read from After the first buffer 404 is moved to the second buffer 406 , the second buffer 406 is used to program data into the storage area 402 , and the first buffer 406 can continue to receive data from the buffer memory 214 . the

Next, after the data D2 is transmitted, when the 0th flash memory die 400 completes the data programming of the data D1, the 0th flash memory die 400 will move the data D2 from the first buffer 404 to the second buffer 406 according to the command CM6 , and after moving the data D2 from the first buffer 404 to the second buffer 406 , program the data D2 from the second buffer 406 to the storage area 402 . When the 0th flash memory grain 400 starts to execute the instruction CM6, the 0th flash memory grain 400 will be in a busy state, and will return to the standby state after completing the transfer of the data D2 from the first buffer 404 to the second buffer 406 ( That is, the busy time B2). Similarly, when the 0th flash memory grain 400 returns to the standby state, the memory management unit 208 will respond to the host system 290, receive the third host write command and data D3 from the host system 290, and write the 0th flash memory grain 400 issues a fast-fetching programming instruction composed of character strings such as "command W1", "ADD3", "data D3" and "command W3" (command CM7, command CM8, transmission T3 and command CM9 shown in FIG. 4A ) to transfer the data D3 of the third host write command to the first buffer 404 (ie, transfer T3). the

Next, after the data D3 is transmitted, when the 0th flash memory die 400 completes the data programming of the data D2, the 0th flash memory die 400 will move the data D3 from the first buffer 404 to the second buffer 406 according to the command CM9 , and after moving the data D3 from the first buffer 404 to the second buffer 406, program the data D3 from the second buffer 406 to the storage area 402. Similarly, when the 0th flash memory die 400 starts to execute the command CM9, the 0th flash memory die 400 will be in a busy state, and will return to Standby state (ie, busy time B3). the

It is worth mentioning that the memory management unit 208 will include the cache status bit and the actual busy status bit in the confirmation message that the memory management unit 208 receives from the 0th flash memory chip 400 to return to the standby status, wherein the cache status bit indicates that the 0th flash memory die 400 Whether the flash memory die 400 is ready to receive the next write data, and the actual busy status bit indicates whether the 0th flash memory die 400 is currently in the actual busy state. Thus, the flash memory controller 204 can correctly determine whether the 0th flash memory die 400 is programming data through the information in the confirmation information. In the example of FIG. 4A and FIG. 4B , after the busy time B3, although the 0th flash memory die 400 has returned to the standby state, the memory management unit 208 has written commands to all hosts received through the NCQ protocol this time. The action of issuing the programming instruction is completed, so the memory management unit 208 will continue to confirm that the 0th flash memory die 400 has completed the programming of all data (that is, the memory management unit 208 will confirm that the 0th flash memory die 400 has been in a non-actually busy state ) Afterwards, the execution status of each host write command is returned to the host system 290. the

FIG. 5 is a flowchart illustrating issuing a programmatic instruction according to an exemplary embodiment of the present invention. the

Please refer to FIG. 5 , first, in step S501 , the flash storage device 200 receives a host write command from the host system 290 . Specifically, in this exemplary embodiment, the host system 290 uses the NCQ protocol to transmit multiple host write commands (2 host write commands as described in FIG. 4A ). Therefore, in step S501, the flash storage device 200 will first receive a plurality of host write commands expected to be issued by the host system 290.

Next, in step S503 , the memory management unit 208 generates an instruction sequence according to the logical address corresponding to the received host write instruction. Specifically, in this embodiment, when the memory management unit 208 receives multiple host write commands from the host system 290 using the NCQ protocol, the memory management unit 208 will sort according to the logical addresses in the host write commands to Determines the expected order in which host write commands are executed. It is worth mentioning that, in another exemplary embodiment of this example, the memory management unit 208 may not rearrange the sequence of the received host write commands, but generate and issue commands in the order in which the host system 290 originally issued the host write commands. order of instructions. the

In step S505 , the memory management unit 208 transmits the generated command order to the host system. Afterwards, in step S507 , the memory management unit 208 receives the host write commands and the write data corresponding to the host write commands from the host system 290 one by one according to the command order. the

Afterwards, in step S509, the memory management unit 208 will issue a cache programming instruction to the flash memory chip 220 (for example, composed of character strings such as "command W1", "physical address", "write data" and "command W3") programmatic instructions). Afterwards, in step S511, the memory management unit 208 waits for and receives confirmation information from the flash memory chip 220, and in step S513 determines whether all host write commands to be issued by the host system 290 in step S501 have been completed. If it is determined in step S513 that all host write commands to be issued by the host system 290 in step S501 have not been completed, then step S507 is executed to continue receiving the next host write command. the

If it is determined in step S513 that all host write commands to be issued by the host system 290 in step S501 have been completed, then in step S515 it is determined whether the flash memory chip 220 is actually busy. If it is determined in step S515 that the flash memory chip 220 is not actually busy, then execute step S517 to respond to the host system 290 and end the process of FIG. 5 , otherwise, continue to execute step S511. the

Based on the above, in the example of using the NCQ protocol to receive a plurality of host write commands from the host system 290, the memory management unit 208 will write to the batch after all the host write commands issued according to the NCQ protocol are completed. The host system 290 reports the execution status of all host write commands (for example, whether there is a programming error). In particular, the memory management unit 208 waits for the flash memory chip 220 to return to the standby state from the actual busy state of executing the last host write command before reporting the execution status of all host write commands to the host system 290 . the

To sum up, the method for issuing a programming command according to the exemplary embodiment of the present invention only uses the cache programming command to program the flash memory chip, thereby greatly shortening the execution time of the host write command. In addition, the method for issuing programmed commands in the exemplary embodiment of the present invention further utilizes the NCQ protocol to transmit commands between the host system and the flash storage device, thereby preventing the host system from being unable to correctly determine the actual execution status of each host write command . Furthermore, in the above-mentioned exemplary embodiment, the NCQ protocol is used to rearrange the order of issuing the host write commands according to the logical addresses to be written by the host write commands, thereby shortening the time required for executing the host write commands. time. the

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention. the

Claims (12)

1. method of flash memory being assigned programmed instructions; The data that are used for coming from a host computer system write to a flash chip; Wherein said flash chip comprises one first buffer zone, one second buffer zone and a storage area, and the said method of assigning programmed instructions comprises:

One flash controller is provided;

Use a primary instruction ordering agreement from said host computer system, to receive a plurality of main frames by said flash controller and write instruction;

Write instruction transmission one by said flash controller according to said main frame and assign instruction sequences to said host computer system; And

From said host computer system, receive said main frame in order and write instruction and write a plurality of data that write of instruction according to the said instruction sequences of assigning with corresponding said main frame; And assign a fast program fetch instruction so that the said write data are write in the said flash chip to said flash chip respectively

Wherein from said host computer system, receive said main frame in order and write instruction and write the said write data of instruction, and assign said fast program fetch instruction to said flash chip respectively and comprise with the step that the said write data are write in the said flash chip with corresponding said main frame according to the said instruction sequences of assigning:

From said host computer system, receiving said main frame writes one first main frame among the instruction and writes among instruction and the said write data corresponding said first main frame and write one first of instruction and write data;

Assign said fast program fetch instruction by said flash controller to said flash chip and write data transmission to said first buffer zone with said first, wherein said first writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area;

From said host computer system, receiving said main frame writes one second main frame among the instruction and writes among instruction and the said write data corresponding said second main frame and write one second of instruction and write data; And

Assign said fast program fetch instruction to write data transmission to said first buffer zone by said flash controller to said flash chip with said second; Wherein said second writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area

Wherein write data and moved to said second buffer zone from said first buffer zone when said first, said second writes data is transferred in said first buffer zone.

2. according to claim 1 flash memory is assigned the method for programmed instructions, wherein writes instruction according to said main frame and transmit the said instruction sequences of assigning and comprise for the step of said host computer system by said flash controller:

Assign the order that said main frame writes instruction by said flash controller according to said host computer system and decide the said instruction sequences of assigning; And

The said instruction sequences of assigning is transmitted said host computer system.

3. according to claim 1 flash memory is assigned the method for programmed instructions, wherein writes instruction according to said main frame and transmit the said instruction sequences of assigning and comprise for the step of said host computer system by said flash controller:

Decide the said instruction sequences of assigning by said flash controller according to a plurality of logical addresses that the said main frame of correspondence writes instruction; And

The said instruction sequences of assigning is transmitted said host computer system.

4. according to claim 1 flash memory is assigned the method for programmed instructions, also comprises:

The executing state that the corresponding said main frame of transmission writes instruction after said flash controller is accomplished all said main frames to write instruction is to said host computer system.

5. the method for flash memory being assigned programmed instructions according to claim 4; When wherein among corresponding said main frame writes the executing state of instruction, comprising at least one sequencing mistake, then receive said main frame again from said host computer system and write that the main frame of corresponding said at least one sequencing mistake writes instruction and writes data among the instruction by said flash controller.

6. the method for flash memory being assigned programmed instructions according to claim 4; When wherein among corresponding said main frame writes the executing state of instruction, comprising at least one sequencing mistake, then receive all said main frames again from said host computer system and write instruction and said write data by said flash controller.

7. system of flash memory being assigned programmed instructions; The data that are used for coming from a host computer system write to a flash chip; Wherein said flash chip comprises one first buffer zone, one second buffer zone and a storage area, and the said system that flash memory is assigned programmed instructions comprises:

First module writes instruction in order to use a primary instruction ordering agreement from said host computer system, to receive a plurality of main frames;

Second module is assigned instruction sequences to said host computer system in order to write instruction transmission one according to said main frame; And

Three module; In order to from said host computer system, to receive said main frame in order and write instruction and write a plurality of data that write of instruction with corresponding said main frame according to the said instruction sequences of assigning; And assign a fast program fetch instruction so that the said write data are write in the said flash chip to said flash chip respectively

Wherein said three module receives said main frame and writes one first main frame among the instruction and write among instruction and the said write data corresponding said first main frame and write one first of instruction and write data from said host computer system; Assign said fast program fetch instruction to said flash chip and write data transmission to said first buffer zone with said first, wherein said first writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area;

Wherein said three module receives said main frame and writes one second main frame among the instruction and write among instruction and the said write data corresponding said second main frame and write one second of instruction and write data from said host computer system,

Wherein said three module is assigned said fast program fetch instruction to write data transmission to said first buffer zone with said second to said flash chip; Wherein said second writes data is moved to said second buffer zone and from said second buffer zone from said first buffer zone and is written into said storage area; And write data and moved to said second buffer zone from said first buffer zone when said first, said second writes data is transferred in said first buffer zone.

8. according to claim 7 flash memory is assigned the system of programmed instructions, wherein said second module is assigned order that said main frame writes instruction according to said host computer system and is decided and saidly assign instruction sequences and the said instruction sequences of assigning is transmitted said host computer system.

9. according to claim 7 flash memory is assigned the system of programmed instructions, a plurality of logical addresses that wherein said second module writes instruction according to the said main frame of correspondence decide saidly to be assigned instruction sequences and the said instruction sequences of assigning is transmitted said host computer system.

10. according to claim 7 flash memory is assigned the system of programmed instructions, also comprises:

Four module, the executing state that writes instruction in order to the corresponding said main frame of transmission after accomplishing all said main frames to write instruction is given said host computer system.

11. according to claim 10 flash memory is assigned the system of programmed instructions, also comprises:

The 5th module; When comprising at least one sequencing mistake among the executing state that writes instruction when corresponding said main frame, from said host computer system, receive said main frame again and write that the main frame of corresponding said at least one sequencing mistake writes instruction and writes data among the instruction.

12. according to claim 10 flash memory is assigned the system of programmed instructions, also comprises:

The 6th module when comprising at least one sequencing mistake among the executing state that writes instruction when corresponding said main frame, receives said main frame again and writes instruction and said write data from said host computer system.

Images