CN103914391A - Data reading method, memory controller and memory storage device - Google Patents

Abstract

The invention provides a data reading method, a memory controller and a memory storage device. The reading method is used for a rewritable nonvolatile memory module comprising a plurality of entity erasing units, and comprises the following steps: configuring a plurality of logical addresses to map to a portion of the physical erase units; receiving a plurality of reading instructions from a host system, wherein the reading instructions instruct to read a plurality of first logical addresses in the logical addresses; executing the reading instructions and judging whether the first logic addresses are continuous or not; and if the first logical addresses are continuous, pre-reading data belonging to a logical range from the entity erasing unit to the buffer memory. Thus, the speed of reading data can be improved.

Description

Data reading method, memory controller and memory storage device

technical field

The present invention relates to a data reading method, and in particular to a data reading method, a memory controller and a memory storage device for a rewritable non-volatile memory module.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable devices such as the above examples. in the multimedia device.

Generally, the erasable non-volatile memory module is controlled by a memory controller, and the memory controller receives a read command from a host system. The memory controller reads data from the erasable non-volatile memory module according to the received read command. The memory controller can create a command array in which read commands from the host system are stored. The memory controller is free to determine the execution order of the read commands in the command array. Also, the memory controller can pre-read some data from the erasable non-volatile memory module to a buffer memory, so that when the host system reads a plurality of consecutive addresses, the read data can be increased. speed. However, the read commands issued by the host system to the memory controller may not be sequential, which will cause the pre-read data to be cleared from the buffer memory. Therefore, how to increase the speed of reading data is a topic concerned by those skilled in the art.

Contents of the invention

An exemplary embodiment of the present invention proposes a data reading method, a memory controller and a memory storage device, which can increase the speed of reading data.

An exemplary embodiment of the invention provides a data reading method for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erasable units. The above data reading method includes: configuring a plurality of logical addresses to map to a part of the entity erasing unit; receiving a plurality of first read instructions from the host system, wherein the first read instruction indicates to read the A plurality of first logical addresses; execute the first read instruction, and judge whether the first logical addresses are continuous; and if the first logical addresses are continuous, pre-read data belonging to the first logical range from the entity erasing unit to buffer memory.

In an exemplary embodiment, the above data reading method further includes: receiving a second read instruction from the host system, wherein the second read instruction indicates to read a second logical address; judging the second logical address Whether it is within a predetermined range of the above-mentioned logical addresses, wherein the predetermined range includes the first logical range; if the second logical address is within the predetermined range, judging whether the second logical address is the initial logical address of the first logical range; and if If the second logical address is the initial logical address, the data belonging to the second logical address is sent to the host system.

In an exemplary embodiment, the above data reading method further includes: if the second logical address is the initial logical address, pre-reading data belonging to a second logical range from the physical erasing unit into the buffer memory, Wherein the second logical range follows the first logical range.

In an exemplary embodiment, the above data reading method further includes: if the second logical address is not the initial logical address, maintaining data belonging to the first logical range in the buffer memory and starting a timer; and if the timer If the recorded value is greater than a critical value, the data belonging to the first logical range in the buffer memory is cleared.

In an exemplary embodiment, the aforementioned threshold is proportional to the read time of the rewritable non-volatile memory module.

In an exemplary embodiment, the above data reading method further includes: receiving a third read instruction from the host system, wherein the third read instruction indicates to read a third logical address in the logical addresses; and if The third logical address is the initial logical address, the timer is reset and the data belonging to the third logical address is sent to the host system.

In an exemplary embodiment, the above data reading method further includes: if the second logical address is not within the predetermined range, clearing the data belonging to the first logical range in the buffer memory.

In an exemplary embodiment, the above data reading method further includes: receiving a second read instruction from the host system, wherein the second read instruction indicates to read a second logical address among the logical addresses; Whether the second logical address is within a predetermined range, wherein the predetermined range includes the first logical range; if the second logical address is within the predetermined range, judge whether the second logical address is within the first logical range; if the second logical address is within the first logical range Within range, data belonging to the second logical address is transmitted to the host system.

In an exemplary embodiment, the above data reading method further includes: if the second logical address is not within the first logical range, maintaining data belonging to the first logical range in the buffer memory and starting a timer; and if the timer The recorded value is greater than the critical value, and the data belonging to the first logical range in the buffer memory is cleared.

In an exemplary embodiment, the size of the above-mentioned first logical range is equal to the size of the memory space of the buffer memory.

From another perspective, an exemplary embodiment of the present invention provides a memory storage device, including a connector, a rewritable non-volatile memory module, and a memory controller. The connector is used to electrically connect to a host system. The rewritable non-volatile memory module includes multiple physical erasing units. The memory controller is electrically connected to the connector and the rewritable non-volatile memory module for configuring a plurality of logical addresses to map to a part of the physical erase unit, and receiving a plurality of first reads from the host system Fetch instructions. These first read instructions indicate to read a plurality of first logical addresses among the above logical addresses. The memory controller is also used to execute the first read commands and determine whether the first logical addresses are continuous. If the first logical address is continuous, the memory controller is used to pre-read data belonging to the first logical range in the above logical address from the physical erasing unit to a buffer memory.

In an exemplary embodiment, the above-mentioned memory controller is further configured to receive a second read command from the host system, wherein the second read command indicates to read a second logical address among the logical addresses. The memory controller is also used to determine whether the second logical address is within a predetermined range of logical addresses, wherein the predetermined range includes the first logical range. If the second logical address is within the predetermined range, the memory controller is also used to determine whether the second logical address is the initial logical address of the first logical range. If the second logical address is the initial logical address, the memory controller is further configured to transmit data belonging to the second logical address to the host system.

In an exemplary embodiment, if the second logical address is not the initial logical address, the memory controller is further configured to maintain data belonging to the first logical range in the buffer memory and start a timer. If the value recorded by the timer is greater than the critical value, the memory controller is also used to clear the data belonging to the first logical range in the buffer memory.

In an exemplary embodiment, the above-mentioned memory controller is further configured to receive a third read command from the host system, wherein the third read command indicates to read a third logical address among the logical addresses. If the third logical address is the initial logical address, the memory controller is also used to reset the timer and transmit the data belonging to the third logical address to the host system.

In an exemplary embodiment, the above-mentioned memory controller is further configured to receive a second read command from the host system, wherein the second read command indicates to read a second logical address among the logical addresses. The memory controller is also used to determine whether the second logical address is within a predetermined range of logical addresses. If the second logical address is within the predetermined range, the memory controller is also used to determine whether the second logical address is within the first logical range. If the second logical address is within the first logical range, the memory controller is further configured to transmit data belonging to the second logical address to the host system.

In an exemplary embodiment, if the second logical address is not within the first logical range, the memory controller is further configured to maintain data belonging to the first logical range in the buffer memory and start a timer. If the value recorded by the timer is greater than the critical value, the memory controller is also used to clear the data belonging to the first logical range in the buffer memory.

From another point of view, an exemplary embodiment of the present invention provides a memory controller for controlling a rewritable non-volatile memory module. The memory controller includes a host interface, a memory interface and a memory management circuit. The host interface is used to electrically connect to a host system. The memory interface is used to electrically connect to the rewritable nonvolatile memory module, and the rewritable nonvolatile memory module includes a plurality of physical erasing units. The memory management circuit is electrically connected to the host interface and the memory interface, and is used to configure a plurality of logical addresses to be mapped to part of the physical erasing units, and receive a plurality of first read commands from the host system. Wherein these first read instructions indicate to read multiple first logical addresses in the above logical addresses. The memory management circuit is also used for executing the first read command and judging whether the first logical addresses are consecutive. If the first logical address is continuous, the memory management circuit is used to pre-read data belonging to the first logical range in the above logical address from the physical erasing unit to a buffer memory.

In an exemplary embodiment, the above-mentioned memory management circuit is further configured to receive a second read command from the host system, wherein the second read command indicates to read a second logical address among the logical addresses. The memory management circuit is also used to determine whether the second logical address is within a predetermined range of logical addresses, wherein the predetermined range includes the first logical range. If the second logical address is within the predetermined range, the memory management circuit is also used to determine whether the second logical address is the initial logical address of the first logical range. If the second logical address is the initial logical address, the memory management circuit is also used to transmit data belonging to the second logical address to the host system.

In an exemplary embodiment, if the second logical address is the initial logical address, the memory management circuit is further used to pre-read data belonging to the second logical range from the physical erase unit into the buffer memory, wherein the second logical range is after the first logical range.

In an exemplary embodiment, if the second logical address is not the initial logical address, the memory management circuit is further configured to maintain data belonging to the first logical range in the buffer memory and start a timer. If the value recorded by the timer is greater than the critical value, the memory management circuit is also used to clear the data belonging to the first logic range in the buffer memory.

In an exemplary embodiment, the above memory management circuit is further configured to receive a third read command from the host system, wherein the third read command indicates to read a third logical address among the logical addresses. If the third logical address is the initial logical address, the memory management circuit is further used to reset the timer and transmit the data belonging to the third logical address to the host system.

In an exemplary embodiment, if the second logical address is not within the predetermined range, the memory management circuit is further configured to clear data belonging to the first logical range in the buffer memory.

In an exemplary embodiment, the above-mentioned memory management circuit is further configured to receive a second read command from the host system, wherein the second read command indicates to read a second logical address among the logical addresses. The memory management circuit is also used to determine whether the second logical address is within a predetermined range of logical addresses. If the second logical address is within the predetermined range, the memory management circuit is also used to determine whether the second logical address is within the first logical range. If the second logical address is within the first logical range, the memory management circuit is further configured to transmit data belonging to the second logical address to the host system.

In an exemplary embodiment, if the second logical address is not within the first logical range, the memory management circuit is further configured to maintain data belonging to the first logical range in the buffer memory and start a timer. If the value recorded by the timer is greater than the critical value, the memory management circuit is also used to clear the data belonging to the first logic range in the buffer memory.

Based on the above, the data reading method, the memory controller and the memory storage device proposed by the present invention judge whether to pre-read data according to whether the executed read command reads continuous logical addresses. Thus, the speed at which data is read can be increased.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment;

FIG. 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment;

FIG. 1C is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment;

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A;

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment;

Fig. 4 is an exemplary schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment;

Fig. 5 is an exemplary schematic diagram illustrating a log file according to an exemplary embodiment;

FIG. 6A is a schematic diagram illustrating prefetching data belonging to a logical range according to an exemplary embodiment;

FIG. 6B is a flow chart of the system after judging the pre-read data according to an exemplary embodiment;

FIG. 7 is a flowchart illustrating a data reading method according to an exemplary embodiment.

Explanation of reference signs:

1000: host system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212: U disk;

1214: memory card;

1216: SSD;

1310: digital camera;

1312: SD card;

1314: MMC card;

1316: memory card;

1318: CF card;

1320: embedded storage device;

100: memory storage device;

102: connector;

104: memory controller;

106: erasable non-volatile memory module;

304(0)～304(R): entity erasing unit;

202: memory management circuit;

204: host interface;

206: memory interface;

252: buffer memory;

254: power management circuit;

256: error checking and correction circuit;

410: data area;

420: idle area;

430: system area;

440: replacement area;

450(0)～450(E): logical address

510: record file;

511~515: read instruction;

610, 640: logical range;

620: logical address;

630: predetermined range;

S602, S604, S606, S608, S610, S612, S614: steps of the system flowchart;

S702, S704, S706, S708: steps of the data reading method.

Detailed ways

[First Exemplary Embodiment]

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1A is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . 1B is a schematic diagram of a computer, an input/output device and a memory storage device according to an exemplary embodiment. Referring to FIG. . It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into or read from the memory storage device 100 through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a USB flash drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B.

In general, host system 1000 is any system that can cooperate substantially with memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is described as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the rewritable non-volatile memory storage device is an SD card 1312, an MMC card 1314, a memory stick (memory stick) 1316, and a CF card 1318. Or an embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 is a schematic block diagram showing the memory storage device shown in FIG. 1A.

Please refer to FIG. 2 , the memory storage device 100 includes a connector 102 , a memory controller 104 and a rewritable non-volatile memory module 106 .

In this exemplary embodiment, the connector 102 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connector 102 may also be in accordance with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, high-speed Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (Universal Serial Bus, USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (UHS-I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, memory card (Memory Stick, MS) interface standard, multimedia memory card (Multi MediaCard, MMC) interface standard, plug-in multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (DE) standard or others suitable standard.

The memory controller 104 is used to execute a plurality of logic gates or control instructions implemented in hardware or solid form, and perform data writing, Read and erase operations.

The rewritable non-volatile memory module 106 is electrically connected to the memory controller 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical erasing units 304(0)˜304(R). For example, the physical erase units 304(0)˜304(R) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, and the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. For example, each physical erase unit is composed of 128 physical program units. However, it must be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

In more detail, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of units to be erased together. Entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. Each physical programming unit generally includes a data bit field and a redundant bit field. The data bit field contains a plurality of physical access addresses for storing user data, and the redundant bit field is used for storing system data (eg, control information and error correction code). In this exemplary embodiment, the data bit area of each physical programming unit includes 4 physical access addresses, and the size of one physical access address is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, the physical erasing unit is a physical block, and the physical programming unit is a physical page or a physical sector.

In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (MultiLevel Cell, MLC) NAND flash memory module, that is, at least 2 bits of data can be stored in one storage package. However, the present invention is not limited thereto, and the rewritable nonvolatile memory module 106 may also be a single-level cell (Single Level Cell, SLC) NAND flash memory module, a multi-level cell (Trinary Level Cell, TLC) NAND type Flash memory modules, other flash memory modules, or other memory modules with the same characteristics.

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment.

Referring to FIG. 3 , the memory controller 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .

The memory management circuit 202 is used to control the overall operation of the memory controller 104 . Specifically, the memory management circuit 202 has a plurality of control instructions, and when the memory storage device 100 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data.

In this exemplary embodiment, the control commands of the memory management circuit 202 are implemented in solid form. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 100 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 can also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program codes (for example, in the memory module dedicated to storing system data system area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has driver code, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driver code segment to store the data stored in the erasable non-volatile memory module 106. The control instructions are loaded into the random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit executes these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be implemented in a hardware form. For example, the memory management circuit 202 includes a microcontroller, a memory management unit, a memory writing unit, a memory reading unit, a memory erasing unit and a data processing unit. The memory management unit, the memory writing unit, the memory reading unit, the memory erasing unit and the data processing unit are electrically connected to the microcontroller. Wherein, the memory management unit is used to manage the physical block of the erasable nonvolatile memory module 106; the memory writing unit is used to issue a write command to the erasable nonvolatile memory module 106 to write data into the erasable nonvolatile memory module 106; the memory read unit is used to issue a read instruction to the erasable nonvolatile memory module 106 to read from the erasable nonvolatile memory module 106 Read data in; The memory erasing unit is used for erasing the erasable non-volatile memory module 106 to erase data from the erasable non-volatile memory module 106; and the data processing unit It is used for processing data to be written into the erasable non-volatile memory module 106 and data read from the erasable non-volatile memory module 106 .

The host interface 204 is electrically connected to the memory management circuit 202 and used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the erasable nonvolatile memory module 106 is converted into a format acceptable to the erasable nonvolatile memory module 106 via the memory interface 206 .

In an exemplary embodiment of the present invention, the memory controller 104 further includes a buffer memory 252 , a power management circuit 254 and an error checking and correction circuit 256 .

The buffer memory 252 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the erasable non-volatile memory module 106 .

The power management circuit 254 is electrically connected to the memory management circuit 202 and used to control the power of the memory storage device 100 .

The error checking and correcting circuit 256 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correction circuit 256 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code, ECC Code), and the memory management circuit 202 will write the data corresponding to the write command and the corresponding error checking and correction code into the rewritable non-volatile memory module 106. Afterwards, when the memory management circuit 202 reads data from the erasable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 256 will check the error code according to the error checking and correction code. and correction code to perform error checking and correction procedures on the read data.

FIG. 4 is an exemplary schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment.

It must be understood that when describing the operation of the physical blocks of the rewritable non-volatile memory module 106, words such as "extract", "exchange", "group", and "rotate" are used to operate the physical areas. Blocks are logical concepts. That is to say, the actual location of the physical block of the erasable nonvolatile memory module is not changed, but the physical block of the erasable nonvolatile memory module is logically operated.

Referring to FIG. 4, the memory controller 104 can logically group the physical blocks 304(0)-304(R) of the rewritable non-volatile memory module into multiple areas, such as a data area 410, a free area 420 , a system area 430 and a replacement area 440 . In another exemplary embodiment, the replacement area 440 may also share a physical block containing invalid data with the spare area 420 .

The physical blocks of the data area 410 and the spare area 420 are used to store data from the host system 1000 . Specifically, the data area 410 is a physical block for storing data, and the physical blocks of the idle area 420 are used to replace the physical blocks of the data area 410 . Therefore, the physical blocks of the spare area 420 are empty or usable physical blocks, in which no data is stored or invalid data marked as useless is stored. That is to say, the physical blocks in the spare area 420 have been erased, or the physical blocks extracted before the physical blocks in the spare area 420 are extracted for storing data will be erased first . Therefore, the physical blocks in the spare area 420 are usable physical blocks.

The physical blocks logically belonging to the system area 430 are used to record system data, wherein the system data includes the manufacturer and model of the memory chip, the number of physical blocks of the memory chip, the number of physical pages of each physical block, and the like.

Physical blocks logically belonging to the replacement area 440 are replacement physical blocks. For example, the rewritable non-volatile memory module will reserve 4% of the physical blocks for replacement when it leaves the factory. That is to say, when the physical blocks in the data area 410, the free area 420, and the system area 430 are damaged, the physical blocks reserved in the replacement area 440 are used to replace the damaged physical blocks (ie, bad physical blocks block (badblock)). Therefore, if a normal physical block still exists in the replacement area 440 and the physical block is damaged, the memory controller 104 will extract a normal physical block from the replacement area 440 to replace the damaged physical block. If there is no normal physical block in the replacement area 440 and the physical block is damaged, the memory controller 104 will declare the entire memory storage device 100 as a write-protected state, and data cannot be written any more.

In particular, the number of physical blocks in the data area 410 , the spare area 420 , the system area 430 and the replacement area 440 varies according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 100 , the grouping relationship of the physical blocks associated with the data area 410 , the idle area 420 , the system area 430 and the replacement area 440 will change dynamically. For example, when a physical block in the spare area is damaged and replaced by a physical block in the replacement area, the original physical block in the replacement area will be associated with the spare area.

In this exemplary embodiment, the memory controller 104 allocates logical addresses 450(0)˜450(E) to facilitate data access in physical blocks storing data. For example, when the memory storage device 100 is formatted by the operating system 1110 through the file system (for example, FAT 32), the logical addresses 450(0)-450(E) are respectively mapped to the physical block 304(0) of the data area 410 ~304(A). Here, the memory management circuit 202 (or the memory controller 104) will establish a logical address-physical erasing unit mapping table (logical address-physical erasing unit mapping table) to record the relationship between the logical block address and the physical erasing unit Mapping relations. In this exemplary embodiment, the size of each logical address 450(0)-450(E) is the same as the size of a physical erase unit, that is, the logical address can also be called a logical block address (logical block address, LBA). However, in other exemplary embodiments, the size of each logical address 450(0)-450(E) may also be the size of a physical programming unit, and the present invention does not limit the logical addresses 450(0)-450(E) )the size of.

The host system 1000 will issue a plurality of read commands to the memory management circuit 202 (or the memory controller 104), and these read commands are instructions to read one or more logical addresses 450(0)-450(E) address. The memory management circuit 202 (or the memory controller 104 ) puts these read commands into a command queue, and the memory management circuit 202 (or the memory controller 104 ) determines the order of executing the read commands. If the memory management circuit 202 (or the memory controller 104) is to execute a read instruction, the memory management circuit 202 (or the memory controller 104) will obtain the logical address to be read by the read instruction, and obtain the logical address of the logical address. A mapped physical erasing unit reads data from the physical erasing unit and transmits the data to the host system 1000 . However, before executing a read command, the memory management circuit 202 (or the memory controller 104) pre-reads some data from the physical erase units 304(0)-304(B) into the buffer memory in the memory controller 104 252; Next, if the data to be read by the read command is already in the buffer memory 252, the memory management circuit 202 (or the memory controller 104) can transmit the data in the buffer memory 252 to the host system 1000, thereby Increase the speed of reading data. In another exemplary embodiment, the data pre-read by the memory management circuit 202 (or the memory controller 104 ) may also be placed in a buffer memory other than the memory controller 104 , the invention is not limited thereto.

FIG. 5 is an exemplary diagram illustrating a log file according to an exemplary embodiment.

Please refer to FIG. 5, after the memory management circuit 202 (or memory controller 104) receives multiple read commands (also called first read commands) from the host system 1000 and executes these read commands, it will The read command is stored in log file 510 . For example, the read commands 511-515 that have been executed are recorded in the record file 510, which respectively indicate to read logical addresses 450(2), 450(4), 450(1), 450(0) and 450(3 ) (also called the first logical address). The memory management circuit 202 (or the memory controller 104) first receives the read command 511 from the host system 1000, and then sequentially receives the read commands 512-515; in other words, according to the order in which the read commands 511-515 are received Therefore, the memory management circuit 202 (or the memory controller 104 ) will not find that the host system 1000 wants to read consecutive logical addresses. However, in this exemplary embodiment, the memory management circuit 202 (or the memory controller 104 ) will determine whether the logical addresses to be read by the read commands 511 - 515 are consecutive after executing the read commands 511 - 515 . For example, after the memory management circuit 202 (or the memory controller 104 ) sorts the logical addresses to be read by the read instructions 511 - 515 , it will find that the logical addresses 450 ( 0 ) - 450 ( 4 ) are continuous. This means that although the host system 1000 is sequentially sending read commands 511-515 to the memory management circuit 202 (or the memory controller 104), the host system 1000 is reading consecutive logical addresses 450(0)-450(4) . Since the logical addresses 450(0)-450(4) are consecutive, the logical addresses to be read by the host system 1000 next may also be consecutive. Therefore, the memory management circuit 202 (or the memory controller 104) prefetches data belonging to a logical range.

In this exemplary embodiment, five read commands 511 - 515 are recorded in the log file 510 . However, in other exemplary embodiments, the record file 510 may also record a greater or lesser number of read commands. Moreover, the memory management circuit 202 (or the memory controller 104 ) starts to pre-read data after judging that n read commands in the record file 510 are continuous, wherein n is a positive integer. However, the present invention does not limit the value of n.

FIG. 6A is a schematic diagram illustrating prefetching data belonging to a logical range according to an exemplary embodiment.

Please refer to FIG. 6A, since the logical addresses 450(0)-450(4) read by the read command in the record file 510 are continuous, the memory management circuit 202 (or the memory controller 104) will pre-read the logic address The data of range 610 is sent to buffer memory 252 . The memory management circuit 202 (or the memory controller 104 ) also sets a predetermined range 630 , and the predetermined range 630 includes the logical range 610 . However, the present invention does not limit the size of the logical range 610 and the predetermined range 630 . Next, the memory management circuit 202 (or the memory controller 104 ) receives a read command (also called a second read command) from the host system 1000 . The second read command indicates to read the logical address 620 (also referred to as the second logical address). The memory management circuit 202 (or the memory controller 104 ) first determines whether the logical address 620 is within the predetermined range 630 . If the logical address 620 is within the predetermined range 630, the memory management circuit 202 (or the memory controller 104) also determines whether the logical address 620 is the initial logical address of the logical range 610 (ie, logical address 450(5)). If the logical address 620 is the logical address 450 (5), the memory management circuit 202 (or the memory controller 104 ) reads the data belonging to the logical address 620 from the buffer memory 252 and transmits the data to the host system 1000 .

On the other hand, if logical address 620 is within predetermined range 630 but not logical address 450(5), memory management circuit 202 (or memory controller 104) will maintain data belonging to logical range 610 in buffer memory 252 and start a timer. The present invention does not limit the implementation of the timer by software or hardware. Here, although the host system 1000 does not currently want to read the logical address 450(5), since the logical address 620 is still within the predetermined range 630, the host system 1000 may read the logical address again in the next period of time 450(5). Therefore, the memory management circuit 202 (or the memory controller 104 ) will not clear the data belonging to the logic range 610 in the buffer memory 252 after obtaining the second read command. However, if the value recorded by the timer is greater than a threshold value, the memory management circuit 202 (or the memory controller 104 ) will clear the data belonging to the logic range 610 in the buffer memory 252 . In addition, if the logical address 620 is not within the predetermined range 630 , the memory management circuit 202 (or the memory controller 104 ) will also clear the data belonging to the logical range 610 in the buffer memory 252 .

After the timer is started, if the memory management circuit 202 (or the memory controller 104) receives the next read command (also called the third read command) from the host system 1000, and the third read command indicates to read When the fetched logical address (also called the third logical address) is logical address 450(5), the memory management circuit 202 (or memory controller 104) will reset this timer, and will belong to logical address 450(5) The data is transferred to the host system 1000 .

In other words, the memory management circuit 202 (or the memory controller 104) will maintain the data belonging to the logical range 610 in the buffer memory 252 until the host system 1000 reads a logical address outside the predetermined range 630 or within a predetermined time None of the internal host system 1000 reads the logical address 450(5) (ie, the value recorded by the timer is greater than a threshold value). In an exemplary embodiment, the threshold is proportional to a read time of the erasable non-volatile memory module 106 . The read time represents the time required for the erasable non-volatile memory module 106 to execute a read command. If the read time is greater, the memory management circuit 202 (or the memory controller 104 ) will increase the threshold, thereby increasing the time for data belonging to the logical range 610 to be stored in the buffer memory 252 . For example, the memory management circuit 202 (or the memory controller 104 ) can set the threshold to be twice the read time, but the invention is not limited thereto.

In an exemplary embodiment, the memory management circuit 202 (or the memory controller 104 ) can also transmit data belonging to multiple logical addresses to the host system 1000 at one time. For example, the memory management circuit 202 (or the memory controller 104) first receives the read instruction to read the logical address 450(6) and then receives the read instruction to read the logical address 450(5), and reads the logical address The read command of 450(6) will be stored in the command array first. When it is determined that the host system 1000 is going to read the logical address 450(5), the memory management circuit 202 (or the memory controller 104) transmits the data belonging to the logical addresses 450(5), 450(6) to the host system 1000. In an exemplary embodiment, the step of transmitting the data belonging to the logical addresses 450(5), 450(6) to the host system 1000 may also be performed by another circuit (not shown), the invention is not limited thereto.

In this exemplary embodiment, the size of the logical range 610 is equal to the size of the memory space of the buffer memory 252 . However, in another exemplary embodiment, the size of the logical range 610 may also be smaller than the size of the memory space of the buffer memory 252 , the invention is not limited thereto. And, when the logical address 620 is the logical address 450(5), and the data belonging to the logical address 450(5) has been transferred to the host system 1000, the memory management circuit 202 (or the memory controller 104) can also be erased from the physical The data belonging to the logical range 640 (also referred to as the second logical range) in the units 304 ( 0 )˜304 (R) is pre-read to the buffer memory 252 . The logical range 640 follows the logical range 610 , but the present invention does not limit the size of the logical range 640 . For example, logical range 640 may include two logical addresses if memory management circuit 202 (or memory controller 104 ) transfers data belonging to logical addresses 450(5), 450(6) to host system 1000 at one time. However, in another exemplary embodiment, the memory management circuit 202 (or the memory controller 104) may also pre-read the memory belonging to the logical range 640 when the host system 1000 reads to the logical address 450(F) or other logical addresses. data, the present invention is not limited thereto.

In this exemplary embodiment, logical range 610 follows logical addresses 450(0)˜450(4). However, in other exemplary embodiments, the logical range 610 may also be before the logical addresses 450(0)˜450(4). For example, the host system 1000 reads consecutive logical addresses from large to small, so after executing multiple read instructions with consecutive logical addresses, the memory management circuit 202 (or memory controller 104) pre-reads The fetched logical range 610 will precede these consecutive logical addresses. Also, the logical range 640 will be before the logical range 610 .

FIG. 6B is a flow chart showing the system after judging the pre-read data according to an exemplary embodiment.

Referring to FIG. 6B , in step S602 , the memory management circuit 202 (or the memory controller 104 ) pre-reads data belonging to the logical range 610 into the buffer memory 252 .

In step S604 , the memory management circuit 202 (or the memory controller 104 ) receives a read command, and the read command indicates to read the logical address 620 .

In step S606 , the memory management circuit 202 (or the memory controller 104 ) determines whether the logical address 620 is within the predetermined range 630 .

If the result of step S606 is negative, in step S608 , the memory management circuit 202 (or the memory controller 104 ) clears the data belonging to the logical range 610 in the buffer memory 252 .

If the result of step S606 is yes, in step S610 , the memory management circuit 202 (or the memory controller 104 ) determines whether the logical address 620 is the initial logical address 450 ( 5 ) of the logical range 610 .

If the result of step S610 is negative, in step S612, the memory management circuit 202 (or the memory controller 104) waits for a period of time, and clears the data belonging to the logical range 610 in the buffer memory 252 if the time exceeds.

If the result of step S610 is yes, in step S614 , the memory management circuit 202 (or the memory controller 104 ) transmits the data belonging to the logical address 620 to the host system 1000 .

[Second Exemplary Embodiment]

The second exemplary embodiment is similar to the first exemplary embodiment, and only the differences are described here. Referring to FIG. 6A, in the first exemplary embodiment, the memory management circuit 202 (or the memory controller 104) transmits data to the host system when the logical address 620 is the logical address 450(5). But in the second exemplary embodiment, the memory management circuit 202 (or the memory controller 104 ) can transmit data to the host system 1000 when the logical address 620 is any logical address in the logical range 610 .

Specifically, after pre-reading the data belonging to the logical range 610 and receiving the read command to read the logical address 620, the memory management circuit 202 (or the memory controller 104) will determine whether the logical address 620 is within the predetermined range 630 Inside. If the logical address 620 is not within the predetermined range 630 , the memory management circuit 202 (or the memory controller 104 ) clears the data belonging to the logical range 610 in the buffer memory 252 . If the logical address 620 is within the logical range 630 , the memory management circuit 202 (or the memory controller 104 ) will further determine whether the logical address 620 is within the logical range 610 . If the logical address 620 is within the logical range 610 , the memory management circuit 202 (or the memory controller 104 ) will transmit the data belonging to the logical address 620 to the host system 1000 . If the logical address 620 is within the predetermined range 630 but not within the logical range 610, the memory management circuit 202 (or the memory controller 104) maintains the data belonging to the logical range 610 in the buffer memory 252 and starts a timer. If the value recorded by the timer is greater than the threshold value, the memory management circuit 202 (or the memory controller 104 ) clears the data belonging to the logic range 610 in the buffer memory 252 .

FIG. 7 is a flowchart illustrating a data reading method according to an exemplary embodiment. It should be noted that the flowchart shown in FIG. 7 can be implemented together with the first exemplary embodiment or the second exemplary embodiment, or implemented independently, and the present invention is not limited thereto.

Referring to FIG. 7 , in step S702 , the memory management circuit 202 (or the memory controller 104 ) configures a plurality of logical addresses to map to some of the physical erasing units.

In step S704, the memory management circuit 202 (or the memory controller 104) receives a plurality of read commands from the host system and executes the read commands. Wherein these read instructions indicate to read a plurality of first logical addresses.

In step S706, the memory management circuit 202 (or the memory controller 104) determines whether the first logical addresses are consecutive. If the result of step S706 is negative, the memory management circuit 202 (or memory controller 104) will return to step S704, receive the next read instruction and judge whether the logical address to be read by the executed n read instructions is continuous. If the result of step S706 is yes, the memory management circuit 202 (or the memory controller 104) will proceed to step S708.

In step S708, the memory management circuit 202 (or the memory controller 104) pre-reads data belonging to a logical range from the physical erase unit into a buffer memory. This cache memory can be configured inside or outside the memory controller 104 .

Each step in FIG. 7 has been described in detail above, and will not be repeated here. On the other hand, each step in FIG. 7 can be implemented as a plurality of program codes or circuits, and the present invention does not limit the implementation of the data reading method shown in FIG. 7 by means of software or hardware.

To sum up, the data reading method, memory controller and memory storage device proposed by the embodiments of the present invention can determine whether the host system reads consecutive logical addresses, thereby determining whether to pre-read data. And, according to whether the logical address to be read next by the host system (or the logical address to be read by a read command in the command array) is within a predetermined range, it is judged whether the data to be pre-read maintained in buffer memory. In this way, the speed of reading data can be increased.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (26)

1. A data reading method for a rewritable nonvolatile memory module, characterized in that, the rewritable nonvolatile memory module comprises a plurality of entity erasing units, and the data read Methods include: Configuring a plurality of logical addresses to map to some of the physical erase units; receiving a plurality of first read commands from a host system, wherein the first read commands indicate to read a plurality of first logical addresses among the logical addresses; Executing the first read instructions, and judging whether the first logical addresses are consecutive; and If the first logical addresses are continuous, pre-read data belonging to a first logical range of the logical addresses from the physical erasing units to a buffer memory. 2. The data reading method according to claim 1, further comprising: receiving a second read command from the host system, wherein the second read command indicates to read a second logical address among the logical addresses; judging whether the second logical address is within a predetermined range among the logical addresses, wherein the predetermined range includes the first logical range; if the second logical address is within the predetermined range, judging whether the second logical address is a starting logical address of the first logical range; and If the second logical address is the initial logical address, sending data belonging to the second logical address to the host system. 3. The data reading method according to claim 2, further comprising: If the second logical address is the initial logical address, pre-read data belonging to a second logical range of the logical addresses from the physical erasing units into the buffer memory, wherein the second logical range is Continuing after the first logical range. 4. The data reading method according to claim 2, further comprising: if the second logical address is not the initial logical address, maintaining data belonging to the first logical range in the buffer memory and starting a timer; and If a value recorded by the timer is greater than a critical value, clear the data belonging to the first logical range in the buffer memory. 5. The data reading method according to claim 4, wherein the critical value is proportional to a reading time of the erasable non-volatile memory module. 6. The data reading method according to claim 4, further comprising: receiving a third read command from the host system, wherein the third read command indicates to read a third logical address among the logical addresses; and If the third logical address is the initial logical address, reset the timer and transmit data belonging to the third logical address to the host system. 7. The data reading method according to claim 2, further comprising: If the second logical address is not within the predetermined range, clear the data belonging to the first logical range in the buffer memory. 8. The data reading method according to claim 1, further comprising: receiving a second read command from the host system, wherein the second read command indicates to read a second logical address among the logical addresses; judging whether the second logical address is within a predetermined range among the logical addresses, wherein the predetermined range includes the first logical range; If the second logical address is within the predetermined range, determining whether the second logical address is within the first logical range; and If the second logical address is within the first logical range, sending data belonging to the second logical address to the host system. 9. The data reading method according to claim 8, further comprising: if the second logical address is not within the first logical range, maintaining data belonging to the first logical range in the buffer memory and starting a timer; and If a value recorded by the timer is greater than a critical value, clear the data belonging to the first logical range in the buffer memory. 10. The data reading method according to claim 1, wherein a size of the first logical range is equal to a size of a memory space of the buffer memory. 11. A memory storage device, comprising: a connector for electrically connecting to a host system; A rewritable non-volatile memory module, including a plurality of physical erasing units; and A memory controller, electrically connected to the connector and the erasable non-volatile memory module, for configuring a plurality of logical addresses to be mapped to some of the physical erasing units, and receiving data from the host system a plurality of first read instructions, wherein the first read instructions indicate to read a plurality of first logical addresses among the logical addresses, Wherein, the memory controller is used to execute the first read instructions, and judge whether the first logical addresses are consecutive, If the first logical addresses are continuous, the memory controller is used to pre-read data belonging to a first logical range of the logical addresses from the physical erasing units to a buffer memory. 12. The memory storage device according to claim 11, wherein the memory controller is further configured to receive a second read command from the host system, wherein the second read command indicates to read the a second logical address of the logical addresses, The memory controller is also used to determine whether the second logical address is within a predetermined range among the logical addresses, wherein the predetermined range includes the first logical range, If the second logical address is within the predetermined range, the memory controller is also used to determine whether the second logical address is a starting logical address of the first logical range, If the second logical address is the initial logical address, the memory controller is further configured to transmit data belonging to the second logical address to the host system. 13. The memory storage device according to claim 12, wherein if the second logical address is not the initial logical address, the memory controller is also used to maintain data belonging to the first logical range in the buffer memory and starts a timer, If a value recorded by the timer is greater than a critical value, the memory controller is also used for clearing the data belonging to the first logical range in the buffer memory. 14. The memory storage device according to claim 13, wherein the memory controller is further configured to receive a third read command from the host system, wherein the third read command indicates to read the a third logical address of the logical addresses, If the third logical address is the initial logical address, the memory controller is further configured to reset the timer and transmit data belonging to the third logical address to the host system. 15. The memory storage device according to claim 11, wherein the memory controller is further configured to receive a second read command from the host system, wherein the second read command indicates to read the a second logical address of the logical addresses, The memory controller is also used to determine whether the second logical address is within a predetermined range among the logical addresses, wherein the predetermined range includes the first logical range, If the second logical address is within the predetermined range, the memory controller is further configured to determine whether the second logical address is within the first logical range, If the second logical address is within the first logical range, the memory controller is further configured to transmit data belonging to the second logical address to the host system. 16. The memory storage device according to claim 15, wherein if the second logical address is not within the first logical range, the memory controller is further configured to maintain data belonging to the first logical range in the buffer memory and starts a timer, If a value recorded by the timer is greater than a critical value, the memory controller is also used for clearing the data belonging to the first logical range in the buffer memory. 17. A memory controller, characterized in that, for controlling a rewritable non-volatile memory module, the memory controller comprises: a host interface for electrically connecting to a host system; a memory interface for electrically connecting to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erasable units; and A memory management circuit, electrically connected to the host interface and the memory interface, for configuring a plurality of logical addresses to map to some of the physical erasing units, and receiving a plurality of first read commands from the host system , wherein the first read instructions indicate to read a plurality of first logical addresses among the logical addresses, Wherein, the memory management circuit is used to execute the first read instructions, and judge whether the first logical addresses are consecutive, If the first logical addresses are consecutive, the memory management circuit is used to pre-read data belonging to a first logical range of the logical addresses from the physical erasing units to a buffer memory. 18. The memory controller according to claim 17, wherein the memory management circuit is further configured to receive a second read command from the host system, wherein the second read command indicates to read the a second logical address of the logical addresses, The memory management circuit is also used to determine whether the second logical address is within a predetermined range among the logical addresses, wherein the predetermined range includes the first logical range, If the second logical address is within the predetermined range, the memory management circuit is also used to determine whether the second logical address is a starting logical address of the first logical range, If the second logical address is the initial logical address, the memory management circuit is further configured to transmit data belonging to the second logical address to the host system. 19. The memory controller according to claim 18, wherein if the second logical address is the initial logical address, the memory management circuit is also used for pre-reading from the physical erase units belonging to the data of a second logical range in the logical addresses into the buffer memory, wherein the second logical range follows the first logical range. 20. The memory controller according to claim 18, wherein if the second logical address is not the initial logical address, the memory management circuit is further configured to maintain data belonging to the first logical range in the buffer memory and starts a timer, If a value recorded by the timer is greater than a critical value, the memory management circuit is also used for clearing the data belonging to the first logic range in the buffer memory. 21. The memory controller according to claim 20, wherein the threshold value is proportional to a read time of the erasable non-volatile memory module. 22. The memory controller according to claim 20, wherein the memory management circuit is further configured to receive a third read command from the host system, wherein the third read command indicates to read the a third logical address of the logical addresses, If the third logical address is the initial logical address, the memory management circuit is further configured to reset the timer and transmit data belonging to the third logical address to the host system. 23. The memory controller according to claim 18, wherein if the second logical address is not within the predetermined range, the memory management circuit is further configured to clear data belonging to the first logical range in the buffer memory. 24. The memory controller according to claim 17, wherein the memory management circuit is further configured to receive a second read command from the host system, wherein the second read command indicates to read the a second logical address of the logical addresses, The memory management circuit is also used to determine whether the second logical address is within a predetermined range among the logical addresses, wherein the predetermined range includes the first logical range, If the second logical address is within the predetermined range, the memory management circuit is further configured to determine whether the second logical address is within the first logical range, If the second logical address is within the first logical range, the memory management circuit is further configured to transmit data belonging to the second logical address to the host system. 25. The memory controller according to claim 24, wherein if the second logical address is not within the first logical range, the memory management circuit is further configured to maintain data belonging to the first logical range in the buffer memory and starts a timer, If a value recorded by the timer is greater than a critical value, the memory management circuit is also used for clearing the data belonging to the first logic range in the buffer memory. 26. The memory controller according to claim 25, wherein a size of the first logical range is equal to a size of a memory space of the buffer memory.