CN101977046B - Bootstrap sampling switch circuit and bootstrap circuit - Google Patents

Abstract

The invention provides a bootstrap sampling switch circuit and a bootstrap circuit. The bootstrap circuit comprises a diode D1, a charging capacitor C1, a phase inverter, a third P-channel metal oxide semiconductor (PMOS) tube M3, a fourth N-channel metal oxide semiconductor (NMOS) tube M4, a fifth NMOS tube M5, a sixth NMOS tube M6, a seventh PMOS tube M7 and an eighth NMOS tube M8, wherein the input end of the phase inverter is connected with a clock (CLK), while the output end is connected with the grid of the M3 and the grid of the M4; the source of the M3 is connected with a virtual device driver (VDD); the source of the M4 is connected with Vin; the drain of the M3 is connected with the drain of the M4; the source of the M5 is connected with the Vin; the grid of the M5 is connected with Vboot; the drain of the M5 is connected with the drain of the M6 and one plate of the capacitor; the grid of the M6 is connected with the CLK, while the source is connected with the ground (GND); the positive end of the D1 is connected with the VDD, while the negative end is connected with a second plate of the C1 and the source of the M7; the grid of the M7 is connected with the drain of the M3; the drain of the M7 and the source of the M8 are connected with the Vboot; and the grid of the M8 is connected with the VDD, while the drain is connected with the output end of the phase inverter.

Description

Bootstrapping sampling switch circuit and boostrap circuit

Technical field

The present invention relates to circuit design field, be meant a kind of bootstrapping sampling switch circuit and boostrap circuit especially.

Background technology

Along with the development of modern communications technology and signal processing technology, increasing to the demand of high speed, high-precision semiconductor integrated circuit.In the simulation process field, need be digital signal usually with analog signal conversion, further handle through digital signal processing module again.In the process of digital signal, usually need use sampling switch in analog signal conversion, to satisfy requirement to performance of analog-to-digital convertor.

Based on to the sampling switch performance demands, commonly used to the bootstrapping sampling switch.This technology is mainly used in sampling hold circuit.The structure of bootstrapped switch is as shown in Figure 1, and the bootstrapping sampling switch mainly comprises: grid voltage boostrap circuit 20 and nmos pass transistor 10 switches.The grid voltage boostrap circuit has two input CLK and Vin, an output Vout.

The grid voltage boostrap circuit of conventional art is as shown in Figure 2, promotes circuit by a charging capacitor C, ten MOS transistor M1-M10 and a clock voltage and forms.Clock CLK connects the grid of nmos pass transistor M1 and PMOS transistor M2, and the source electrode of M1 and M2 meets supply voltage VDD and GND respectively, and the drain electrode of M1 and M2 links to each other, and is designated as node 1, and in fact M1 and M2 have formed an inverter, and the output of direction device is node 1.Node 1 is as the input of clock voltage lifting circuit, and node 2 is the output that clock voltage promotes circuit.Node 2 connects the grid of nmos pass transistor M5, and the drain electrode of M5 meets supply voltage VDD, and source electrode connects the pole plate of charging capacitor C, links to each other with the source electrode of PMOS transistor M9 simultaneously.Node 1 connects the grid of nmos pass transistor M6, and the source electrode of M6 meets GND, and drain electrode connects another pole plate of charging capacitor C, links to each other with the source electrode of nmos pass transistor M4, M7 and M8 simultaneously.The grid of the grid of M4 and nmos pass transistor M3 all meets clock CLK, and the drain electrode of M4 connects the drain electrode of grid and the M8 of the drain electrode of M3, M9.The drain electrode of M9 links to each other with the grid of the grid of M8, M7 and the drain electrode of nmos pass transistor M10, as the output Vboot of grid voltage boostrap circuit.The source electrode of M10 meets GND, and grid connects node 1.The drain electrode of M7 meets the input Vin of grid voltage boostrap circuit.

When clock CLK was low level GND, node 1 made M5, M6 conducting with node 2, and C charges to charging capacitor, and making C go up the voltage that keeps is VDD, M10 conducting this moment, and output voltage V boot is GND.When clock CLK was high level VDD, node 1 broke off M5, M6, M10 with node 2, and M4 drags down the grid voltage of M9; Make M7, M8, M9 conducting; So just make Vboot equal Vin and add that C goes up the voltage that keeps, promptly Vboot=Vin+VDD has accomplished the function that grid voltage is booted.M8 surpasses VDD for fear of the gate source voltage of M9, thereby improves device reliability.

Can see that traditional grid voltage boostrap circuit needs extra clock voltage to promote circuit, this circuit increases fixing value (being generally VDD) with the voltage of input clock.This extra clock voltage promotes the complexity that circuit has increased circuit.

Summary of the invention

The technical problem that the present invention will solve provides a kind of bootstrapping sampling switch circuit and boostrap circuit that reduces circuit complexity.

For solving the problems of the technologies described above, embodiments of the invention provide technical scheme following:

A kind of bootstrapping sampling switch circuit comprises:

Boostrap circuit and the 9th nmos pass transistor;

Said boostrap circuit input clock signal CLK with treat sampled signal Vin, export the first signal Vboot; The source electrode of the 9th nmos pass transistor connects treats that sampled signal Vin, the grid of the 9th nmos pass transistor connect the said first signal Vboot, the drain electrode output secondary signal Vout of the 9th nmos pass transistor;

Said boostrap circuit comprises:

Diode, charging capacitor, inverter, the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th PMOS transistor and the 8th nmos pass transistor;

The input of said inverter connects clock signal clk, and the output of said inverter connects the grid of transistorized grid of the 3rd PMOS and the 4th nmos pass transistor respectively;

The transistorized source electrode of the 3rd PMOS connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor drain and the 4th nmos pass transistor links to each other;

The source electrode of the 5th nmos pass transistor connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor connects the drain electrode of the 6th nmos pass transistor and first pole plate of charging capacitor respectively;

The grid of the 6th nmos pass transistor connects clock signal clk, and the source electrode of the 6th nmos pass transistor connects earth signal GND;

The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate and the transistorized source electrode of the 7th PMOS of charging capacitor respectively;

The transistorized grid of the 7th PMOS links to each other with the 3rd PMOS transistor drain, and the source electrode of the 7th PMOS transistor drain and the 8th nmos pass transistor all is connected the first signal Vboot;

The grid of the 8th nmos pass transistor connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor links to each other with the output of inverter.

Said inverter comprises: a PMOS transistor and second nmos pass transistor;

The grid of the transistorized grid of the one PMOS and second nmos pass transistor all is connected clock signal clk, as the input of inverter;

The transistorized source electrode of the one PMOS connects supply voltage VDD;

The source electrode of second nmos pass transistor connects earth signal GND;

The drain electrode of the one PMOS transistor drain and second nmos pass transistor links to each other, as the output of inverter.

Said bootstrapping sampling switch circuit is a semiconductor integrated circuit.

On the other hand, a kind of boostrap circuit is provided, comprises:

Diode, charging capacitor, inverter, the 3rd PMOS transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th PMOS transistor and the 8th nmos pass transistor;

The input of said inverter connects clock signal clk, and the output of said inverter connects the grid of transistorized grid of the 3rd PMOS and the 4th nmos pass transistor respectively;

The transistorized source electrode of the 3rd PMOS connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor drain and the 4th nmos pass transistor links to each other;

The source electrode of the 5th nmos pass transistor connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor connects the drain electrode of the 6th nmos pass transistor and first pole plate of charging capacitor respectively;

The grid of the 6th nmos pass transistor connects clock signal clk, and the source electrode of the 6th nmos pass transistor connects earth signal GND;

The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate and the transistorized source electrode of the 7th PMOS of charging capacitor respectively;

The transistorized grid of the 7th PMOS links to each other with the 3rd PMOS transistor drain, and the source electrode of the 7th PMOS transistor drain and the 8th nmos pass transistor all is connected the first signal Vboot;

The grid of the 8th nmos pass transistor connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor links to each other with the output of inverter.

Said inverter comprises: a PMOS transistor and second nmos pass transistor;

The grid of the transistorized grid of the one PMOS and second nmos pass transistor all is connected clock signal clk, as the input of inverter;

The transistorized source electrode of the one PMOS connects supply voltage VDD;

The source electrode of second nmos pass transistor connects earth signal GND;

The drain electrode of the one PMOS transistor drain and second nmos pass transistor links to each other, as the output of inverter.

Said boostrap circuit is a semiconductor integrated circuit.

Embodiments of the invention have following beneficial effect:

In the such scheme, when clock signal clk was high level VDD, Vboot was low level GND.When clock signal clk is low level GND, Vboot be treat sampled signal Vin and charging capacitor voltage VDD-Vd with, Vd is the threshold voltage of diode, thereby has reached the function of grid voltage bootstrapping.Do not need extra clock voltage to promote circuit, reduced the complexity of circuit.

Description of drawings

Fig. 1 is the schematic diagram of bootstrapping sampling switch circuit in the prior art;

Fig. 2 is the schematic diagram of boostrap circuit in the prior art;

Fig. 3 is the schematic diagram of boostrap circuit of the present invention.

Embodiment

For technical problem, technical scheme and advantage that embodiments of the invention will be solved is clearer, will combine accompanying drawing and specific embodiment to be described in detail below.

The present invention provides a kind of bootstrapping sampling switch circuit, comprising:

Boostrap circuit and the 9th nmos pass transistor M0;

Said boostrap circuit input clock signal CLK with treat sampled signal Vin, export the first signal Vboot; The source electrode of the 9th nmos pass transistor M0 connects treats that sampled signal Vin, the grid of the 9th nmos pass transistor M0 connect the said first signal Vboot, the drain electrode output secondary signal Vout of the 9th nmos pass transistor M0;

As shown in Figure 3, said boostrap circuit comprises:

Diode, charging capacitor, inverter, the 3rd PMOS (P-channel metal oxide semiconductor FET; The P-channel metal-oxide-semiconductor field-effect transistor) transistor M3, the 4th NMOS (N-channel metal oxide semiconductor FET, n channel metal oxide semiconductor field effect transistor) transistor M4, the 5th nmos pass transistor M5, the 6th nmos pass transistor M6, the 7th PMOS transistor M7 and the 8th nmos pass transistor M8;

The input of said inverter connects clock signal clk, and the output of said inverter connects the grid of the 3rd PMOS transistor M3 and the grid of the 4th nmos pass transistor M4 respectively;

The source electrode of the 3rd PMOS transistor M3 connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor M4 connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor M3 links to each other with the drain electrode of the 4th nmos pass transistor M4;

The source electrode of the 5th nmos pass transistor M5 connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor M5 connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor M5 connects the drain electrode of the 6th nmos pass transistor M6 and first pole plate of charging capacitor respectively;

The grid of the 6th nmos pass transistor M6 connects clock signal clk, and the source electrode of the 6th nmos pass transistor M6 connects earth signal GND;

The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate of charging capacitor and the source electrode of the 7th PMOS transistor M7 respectively;

The grid of the 7th PMOS transistor M7 links to each other with the drain electrode of the 3rd PMOS transistor M3, and the drain electrode of the 7th PMOS transistor M7 all is connected the first signal Vboot with the source electrode of the 8th nmos pass transistor M8;

The grid of the 8th nmos pass transistor M8 connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor M8 links to each other with the output of inverter.

Said inverter comprises: the 8th PMOS transistor M1 and the second nmos pass transistor M2;

The grid of the 8th PMOS transistor M1 all is connected clock signal clk with the grid of the second nmos pass transistor M2, as the input of inverter;

The source electrode of the 8th PMOS transistor M1 connects supply voltage VDD;

The source electrode of the second nmos pass transistor M2 connects earth signal GND;

The drain electrode of the 8th PMOS transistor M1 links to each other with the drain electrode of the second nmos pass transistor M2, as the output of inverter.

Said bootstrapping sampling switch circuit is a semiconductor integrated circuit.

In the foregoing circuit, the drain electrode of the 8th PMOS transistor M1 links to each other with the drain electrode of the second nmos pass transistor M2, is designated as node 1; The drain electrode of the 3rd PMOS transistor M3 links to each other with the drain electrode of the 4th nmos pass transistor M4, is designated as node 2.

On the other hand, as shown in Figure 3, a kind of boostrap circuit is provided, comprising:

Diode, charging capacitor, inverter, the 3rd PMOS transistor M3, the 4th nmos pass transistor M4, the 5th nmos pass transistor M5, the 6th nmos pass transistor M6, the 7th PMOS transistor M7 and the 8th nmos pass transistor M8;

The input of said inverter connects clock signal clk, and the output of said inverter connects the grid of the 3rd PMOS transistor M3 and the grid of the 4th nmos pass transistor M4 respectively;

The source electrode of the 3rd PMOS transistor M3 connects supply voltage VDD, and the source electrode of the 4th nmos pass transistor M4 connects treats sampled signal Vin, and the drain electrode of the 3rd PMOS transistor M3 links to each other with the drain electrode of the 4th nmos pass transistor M4;

The source electrode of the 5th nmos pass transistor M5 connects treats that sampled signal Vin, the grid of the 5th nmos pass transistor M5 connect the first signal Vboot, and the drain electrode of the 5th nmos pass transistor M5 connects the drain electrode of the 6th nmos pass transistor M6 and first pole plate of charging capacitor respectively;

The grid of the 6th nmos pass transistor M6 connects clock signal clk, and the source electrode of the 6th nmos pass transistor M6 connects earth signal GND;

The forward end of diode connects supply voltage VDD, and the negative end of diode connects second pole plate of charging capacitor and the source electrode of the 7th PMOS transistor M7 respectively;

The grid of the 7th PMOS transistor M7 links to each other with the drain electrode of the 3rd PMOS transistor M3, and the drain electrode of the 7th PMOS transistor M7 all is connected the first signal Vboot with the source electrode of the 8th nmos pass transistor M8;

The grid of the 8th nmos pass transistor M8 connects supply voltage VDD, and the drain electrode of the 8th nmos pass transistor M8 links to each other with the output of inverter.

Said inverter comprises: the 8th PMOS transistor M1 and the second nmos pass transistor M2;

The grid of the 8th PMOS transistor M1 all is connected clock signal clk with the grid of the second nmos pass transistor M2, as the input of inverter;

The source electrode of the 8th PMOS transistor M1 connects supply voltage VDD;

The source electrode of the second nmos pass transistor M2 connects earth signal GND;

The drain electrode of the 8th PMOS transistor M1 links to each other with the drain electrode of the second nmos pass transistor M2, as the output of inverter.

The invention solves the problem of implementation of bootstrapped switch in the sampling hold circuit; Overcome the deficiency of existing bootstrapping sampling switch circuit; A kind of bootstrapping sampling switch circuit that does not need extra clock signals to promote circuit is provided; Effectively reduce the area of bootstrapping sampling switch circuit, reduced the chip manufacturing cost, effectively realized the function of high speed, high-precision bootstrapping sampling switch.

The present invention uses a diode, under the control of clock signal, periodically charges to charging capacitor, and the voltage on the charging capacitor is added on the input signal, to realize the function of gate voltage bootstrapping.

The 9th metal-oxide-semiconductor that is used as switch is operated in dark linear zone (also claiming dark triode region), and at this moment metal-oxide-semiconductor satisfies condition:

V _ds＝V _gs-V _th (1)

V wherein _DsBe the drain-source voltage of metal-oxide-semiconductor, V _GsBe the gate source voltage of metal-oxide-semiconductor, V _ThBe the threshold voltage of metal-oxide-semiconductor, V _Gs-V _ThBe the overdrive voltage of metal-oxide-semiconductor, at this moment metal-oxide-semiconductor is approximate can equivalence be a resistance, its resistance R _OnBe about:

$R_{\mathrm{on}}\≈\frac{1}{\mathrm{\μ}{C}_{\mathrm{ox}}\frac{W}{L}(V_{\mathrm{gs}}-V_{\mathrm{th}})}---\left(2\right)$

Wherein μ is the metal-oxide-semiconductor carrier mobility, C _OxBe current potential area gate oxide electric capacity,

Breadth length ratio for metal-oxide-semiconductor.

Can see that conducting resistance can be along with gate source voltage V _GsVariation and change, and the variation of conducting resistance can bring the reduction of the linearity, influences the performance of switching circuit.

In order to reach the better linearity degree, need make the gate source voltage V of metal-oxide-semiconductor _GsRemain unchanged.Generally be to give certain electric capacity charging earlier, again with voltage on the electric capacity and input signal addition, connect the grid of metal-oxide-semiconductor, input signal connects the source electrode of metal-oxide-semiconductor, and the gate source voltage of metal-oxide-semiconductor will equal the voltage on the electric capacity like this.

The present invention's sampling switch of booting comprises grid voltage boostrap circuit and the 9th nmos pass transistor M0 switch.The grid voltage boostrap circuit has CLK and two input signals of Vin, and an output of Vout signal is arranged.

The present invention uses the grid voltage boostrap circuit, makes the grid voltage of the 9th nmos pass transistor M9 when switch conduction, remain constant voltage, eliminates the nonlinear purpose of conducting resistance to reach.This circuit can use technologies such as CMOS, BiCMOS to realize.The present invention is applicable to the bootstrapped switch circuit of semiconductor integrated circuit, has solved the excessive problem of existing bootstrapped switch circuit area.

Among the present invention, the negative sense termination supply voltage of diode, forward termination charging capacitor.Under the control of clock signal, periodically charge, and the voltage on the charging capacitor is added on the input signal, to realize the function of gate voltage bootstrapping to charging capacitor.The voltage Vboot that connects the 9th nmos pass transistor M0 switch gate changes under the control of clock signal clk.When CLK was high level, Vboot was output as low-voltage GND; When CLK was low level, Vboot was output as the bootstrap voltage mode of treating sampled signal Vin.

The present invention charges to electric capacity through diode, utilizes turn-offing certainly of diode to reach the purpose of turn-offing the charging path again.When clock signal clk was high level VDD, the voltage of node 1 was moved to low level GND by the second nmos pass transistor M2, because the grid of the 8th nmos pass transistor M8 meets VDD, was low level GND so can make Vboot.Simultaneously, the CLK of high level can make the 6th nmos pass transistor M6 conducting, with supply voltage charging capacitor is charged, and is charged to VDD-Vd, and Vd is the threshold voltage of diode.

When clock signal clk was low level GND, the voltage of node 1 was mentioned high level VDD by the 8th PMOS transistor M1.At this moment low level CLK can make the 6th nmos pass transistor M6 turn-off.The voltage of node 2 is moved to level Vin by the 4th nmos pass transistor M4.The voltage of Vin can make the 7th PMOS transistor M7 conducting, thereby Vboot is uprised, and can make the 5th nmos pass transistor M5 conducting after Vboot uprises; Make Vin receive an end of charging capacitor; And Vboot receives the other end of charging capacitor, and diode D1 is oppositely ended, at this moment Vboot be treat sampled signal Vin and charging capacitor voltage VDD-Vd with; Be Vin+Vdd-Vd, thereby reached the function of grid voltage bootstrapping.

Said method embodiment is corresponding with said device embodiment; The description of relevant portion gets final product among the part comparable device embodiment that in method embodiment, does not describe in detail, and the description of relevant portion gets final product among the part reference method embodiment that in device embodiment, does not describe in detail.

One of ordinary skill in the art will appreciate that; Realize that all or part of step in the foregoing description method is to instruct relevant hardware to accomplish through program; Described program can be stored in the computer read/write memory medium, and this program comprises the step like above-mentioned method embodiment when carrying out; Described storage medium; As: magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.

In each method embodiment of the present invention; The sequence number of said each step can not be used to limit the sequencing of each step; For those of ordinary skills, under the prerequisite of not paying creative work, the priority of each step is changed also within protection scope of the present invention.

The above is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle according to the invention; Can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.

Claims (6)

1. A bootstrap sampling switch circuit, characterized in that, comprising: a bootstrap circuit and a ninth NMOS transistor; The bootstrap circuit inputs the clock signal CLK and the signal Vin to be sampled, and outputs the first signal Vboot; the source of the ninth NMOS transistor is connected to the signal Vin to be sampled, the gate of the ninth NMOS transistor is connected to the first signal Vboot, and the gate of the ninth NMOS transistor is connected to the first signal Vboot. The drains of the nine NMOS transistors output the second signal Vout; The bootstrap circuit includes: a diode, a charging capacitor, an inverter, a third PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth NMOS transistor; The input end of the inverter is connected to the clock signal CLK, and the output end of the inverter is respectively connected to the gate of the third PMOS transistor and the gate of the fourth NMOS transistor; The source of the third PMOS transistor is connected to the power supply voltage VDD, the source of the fourth NMOS transistor is connected to the signal Vin to be sampled, and the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the fifth NMOS transistor is connected to the signal Vin to be sampled, the gate of the fifth NMOS transistor is connected to the first signal Vboot, and the drain of the fifth NMOS transistor is respectively connected to the drain of the sixth NMOS transistor and the first plate of the charging capacitor ; The gate of the sixth NMOS transistor is connected to the clock signal CLK, and the source of the sixth NMOS transistor is connected to the ground signal GND; The positive end of the diode is connected to the power supply voltage VDD, and the negative end of the diode is respectively connected to the second plate of the charging capacitor and the source of the seventh PMOS transistor; The gate of the seventh PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the seventh PMOS transistor and the source of the eighth NMOS transistor are both connected to the first signal Vboot; The gate of the eighth NMOS transistor is connected to the power supply voltage VDD, and the drain of the eighth NMOS transistor is connected to the output terminal of the inverter. 2. The bootstrap sampling switch circuit according to claim 1, wherein the inverter comprises: a first PMOS transistor and a second NMOS transistor; Both the gate of the first PMOS transistor and the gate of the second NMOS transistor are connected to the clock signal CLK as the input terminal of the inverter; The source of the first PMOS transistor is connected to the power supply voltage VDD; The source of the second NMOS transistor is connected to the ground signal GND; The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor as an output terminal of the inverter. 3. The bootstrap sampling switch circuit according to claim 1, wherein the bootstrap sampling switch circuit is a semiconductor integrated circuit. 4. A bootstrap circuit, characterized in that, comprising: a diode, a charging capacitor, an inverter, a third PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and an eighth NMOS transistor; The input end of the inverter is connected to the clock signal CLK, and the output end of the inverter is respectively connected to the gate of the third PMOS transistor and the gate of the fourth NMOS transistor; The source of the third PMOS transistor is connected to the power supply voltage VDD, the source of the fourth NMOS transistor is connected to the signal Vin to be sampled, and the drain of the third PMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the fifth NMOS transistor is connected to the signal Vin to be sampled, the gate of the fifth NMOS transistor is connected to the first signal Vboot, and the drain of the fifth NMOS transistor is respectively connected to the drain of the sixth NMOS transistor and the first plate of the charging capacitor ; The gate of the sixth NMOS transistor is connected to the clock signal CLK, and the source of the sixth NMOS transistor is connected to the ground signal GND; The positive end of the diode is connected to the power supply voltage VDD, and the negative end of the diode is respectively connected to the second plate of the charging capacitor and the source of the seventh PMOS transistor; The gate of the seventh PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the seventh PMOS transistor and the source of the eighth NMOS transistor are both connected to the first signal Vboot; The gate of the eighth NMOS transistor is connected to the power supply voltage VDD, and the drain of the eighth NMOS transistor is connected to the output terminal of the inverter. 5. The bootstrap circuit according to claim 4, wherein the inverter comprises: a first PMOS transistor and a second NMOS transistor; Both the gate of the first PMOS transistor and the gate of the second NMOS transistor are connected to the clock signal CLK as the input terminal of the inverter; The source of the first PMOS transistor is connected to the power supply voltage VDD; The source of the second NMOS transistor is connected to the ground signal GND; The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor as an output terminal of the inverter. 6. The bootstrap circuit according to claim 4, wherein the bootstrap circuit is a semiconductor integrated circuit.

Images