CN106160744A - A kind of high speed dynamic latch comparator applied in low voltage environment - Google Patents

Abstract

The invention discloses a high-speed dynamic latch comparator applied in a low-voltage environment. Under the structure of the traditional high-speed dynamic latch comparator, the traditional structure + forward body bias method is adopted. Compared with the traditional structure The power supply voltage and response time are reduced, and then a NAND gate is added. The traditional structure + forward body bias + NAND gate method reduces power consumption compared with the traditional structure + forward body bias method. The forward body bias method adopted uses the CMOS substrate as another gate, provides the substrate with a substrate bias voltage opposite to the traditional structure, changes the PMOS substrate to ground, and the NMOS substrate Change the power supply. The depletion layer is narrowed, lowering the threshold voltage and thus the required gate voltage.

Description

A High-Speed Dynamic Latch Comparator Applied in Low Voltage Environment

technical field

The invention relates to the field of comparator modules in analog or digital-analog hybrid integrated circuits, in particular to a high-speed dynamic latch comparator used in low-voltage environments.

Background technique

While the reduction of semiconductor process feature size brings great advantages to digital integrated circuits, it does not bring the same advantages to analog integrated circuits as digital integrated circuits. With the continuous reduction of semiconductor process feature sizes, power supply voltage, Intrinsic gain and gate oxide thickness are decreasing, which poses great challenges to analog IC design. Reduction of power supply voltage is an effective way to reduce power consumption of CMOS ICs. As a key module of the analog-to-digital converter (ADC), the comparator's performance, especially speed, noise, offset and power consumption, greatly affects the various performance parameters of the analog-to-digital converter. It is difficult for traditional comparators to meet the speed and power consumption requirements of analog-to-digital converters in low-voltage environments.

SUMMARY OF THE INVENTION The object of the present invention is to provide a high-speed dynamic latch comparator used in a low-voltage environment. The forward body bias technology adopted can make the comparator work in a very low power supply voltage environment, and then add The NAND gate makes the comparator maintain low static power consumption, so as to solve the problem that the comparator in the prior art cannot meet the speed and power consumption requirements of the analog-to-digital converter.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A high-speed dynamic latch comparator applied in a low-voltage environment is characterized in that it includes a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), and a fourth PMOS transistor ( P4), a first inverter (I1), a second inverter (I2), a NAND gate (NAND) and a latch; wherein the latch includes a first control terminal, a second control terminal, a second an output terminal, a second output terminal and a ground terminal;

The gate of the first PMOS transistor (P1) is connected to the clock signal (CLK), the gate of the second PMOS transistor (P2) is connected to the output terminal (CLKC) of the NAND gate, and the gate of the third PMOS transistor (P3) connected to the first input signal (VIP), and the gate of the fourth PMOS transistor (P4) connected to the second input signal (VIN);

The source of the first PMOS transistor (P1) is connected to the power supply (Vdd), the source of the second PMOS transistor (P2) is connected to the drain of the first PMOS transistor (P1), and the third PMOS transistor (P3) The source electrode of the fourth PMOS transistor (P4) is connected to the drain electrode of the second PMOS transistor (P2) respectively;

The drain of the third PMOS transistor (P3) is respectively connected to the input end of the first inverter (I1) and the first output end of the latch; the drain electrode of the fourth PMOS transistor (P4) is respectively connected to the first output end of the latch. The input end of the second inverter (I2) is connected to the second output end of the latch;

The output terminal (OUTP) of the first inverter (I1) is connected to one of the input terminals of the NAND gate (NAND), and the output terminal (OUTN) of the second inverter (I2) is connected to the NAND gate (NAND). ) is connected to the other input terminal;

The substrate of the first PMOS transistor (P1), that is, the body, the body of the second PMOS transistor (P2), the body of the third PMOS transistor (P3), and the body of the fourth PMOS transistor (P4) are all grounded ; The bodies of all PMOS transistors in the first inverter (I1), the second inverter (I2) and the NAND gate (NAND) are grounded, and the bodies of all NMOS transistors are connected to the power supply (Vdd) .

The high-speed dynamic latch comparator applied in a low-voltage environment is characterized in that: the latch includes a first NMOS transistor (P5), a second NMOS transistor (P6), a third NMOS transistor ( P7), the fourth NMOS tube (P8);

The gate of the first NMOS transistor (P5) is used as the first control terminal to connect the clock signal (CLK), the gate of the second NMOS transistor (P6) is used as the second output terminal of the latch, and the gate of the third NMOS transistor (P7 ) gate is used as the first output terminal of the latch, and the gate of the fourth NMOS transistor (P8) is used as the second control terminal to connect to the clock signal (CLK);

The source of the first NMOS transistor (P5), the source of the second NMOS transistor (P6), the source of the third NMOS transistor (P7), and the source of the fourth NMOS transistor (P8) are commonly connected as the ground terminal grounding;

The drain of the first NMOS transistor (P5) and the drain of the second NMOS transistor (P6) are respectively connected to the input end of the first inverter (I1) and the first output end of the latch; The drains of the three NMOS transistors (P7) and the fourth NMOS transistor (P8) are respectively connected to the input end of the second inverter (I2) and the second output end of the latch;

The drain of the third PMOS transistor (P3) is respectively connected to the drain of the first NMOS transistor (P5), the drain of the second NMOS transistor (P6), and the gate of the third NMOS transistor (P7), and the The drain of the fourth PMOS transistor (P4) is respectively connected to the drain of the third NMOS transistor (P7), the drain of the fourth NMOS transistor (P8), and the gate of the second NMOS transistor (P6);

The body of the substrate of the first NMOS transistor (P5), the body of the second NMOS transistor (P6), the body of the third NMOS transistor (P7), and the body of the fourth NMOS transistor (P8) are all connected to power supply (Vdd).

The present invention has the following beneficial technical effects:

1. Pass the comparator output signals OUTP and OUTN through the NAND gate NAND to generate an output signal CLKC, and use the output signal as the control signal of the second PMOS transistor to solve the problem of static power consumption in the traditional structure.

2. Compared with the traditional structure, the substrates of all MOS transistors, that is, the body electrodes, are all reversed, which reduces the threshold voltage and the required gate voltage.

3. The circuit structure of the present invention is simple. Compared with the traditional structure, the sequence is not complicated, and the area is not significantly increased, but it can work effectively in a low-voltage environment, increase the speed, and reduce power consumption.

Description of drawings

Figure 1 is a schematic diagram of the structure of a traditional high-speed dynamic latch comparator;

Figure 2 is a structural schematic diagram of the traditional structure + forward body bias method;

Fig. 3 is a structural principle diagram of the traditional structure+forward body bias+NAND gate method provided by the present invention.

Figure 4 is a comparison time simulation comparison of two comparators under different power supply voltages;

Fig. 5 is a comparison curve of the change of the comparison time of the comparator of the present invention with the change of the input differential signal ΔVin under different common-mode voltages.

detailed description

Figure 1 shows a schematic diagram of a traditional high-speed dynamic latch comparator structure (referred to as the structure [1]), when the clock control signal CLK is high, the NMOS transistor P5/P8 is in the conduction state, and the PMOS transistor P1 is in the ON state. In the off state, through the inverter I1/I2, the comparator output signals OUTP and OUTN are high level, and the comparator is in the reset state; when CLK becomes low level, the PMOS transistor P1 is turned on, and the NMOS transistor P5/P8 turn off, the latch composed of NMOS transistors P6/P7 quickly amplifies the voltage difference between Dip and Din, and enters the latch state; but it should be noted that after the comparison is completed, since the PMOS transistors P1 and P2 are still on, There is still static current and static power consumption; the substrate is the traditional reverse body bias method, that is, the body of the PMOS transistor is connected to VDD, and the body of the NMOS transistor is grounded.

Figure 2 shows the structural schematic diagram of the traditional structure + forward body bias method (referred to as structure [2]), the comparator works the same as the structure [1], except that the forward body bias method is adopted, and the CMOS substrate As another gate, a substrate bias voltage opposite to the traditional structure is provided to the substrate, the substrate of the PMOS is changed to ground, and the substrate of the NMOS is changed to a power supply. The depletion layer is narrowed, the threshold voltage is reduced, and the required gate voltage is also reduced, so as to achieve the purpose of low voltage. The structure proposed by the invention has the advantage of being applied in low power supply voltage occasions.

The structural schematic diagram of the high-speed dynamic latch comparator applied in the low-voltage environment proposed by the present invention is shown in Figure 3 (referred to as the structure [3]),

The high-speed dynamic latch comparator applied in the low-voltage environment includes the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the first inverter I1, the second inverter Phase device I2, NAND gate and latch; the latch includes a first control terminal, a second control terminal, a first output terminal, a second output terminal and a ground terminal; the gate of the first PMOS transistor P1 is connected to the clock signal CLK, the gate of the second PMOS transistor P2 is connected to the output terminal CLKC of the NAND gate, the gate of the third PMOS transistor P3 is connected to the first input signal VIP, and the gate of the fourth PMOS transistor P4 is connected to the second input signal VIN; The source of the first PMOS transistor P1 is connected to the power supply, the source of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1, the source of the third PMOS transistor P3, and the source of the fourth PMOS transistor P4 are respectively connected to the first PMOS transistor P4. The drains of the two PMOS transistors P2 are connected; the drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2, and the drain of the second PMOS transistor P2 is respectively connected to the source of the third NMOS transistor P3, the fourth The source of the NMOS transistor P4 is connected, the drain of the third PMOS transistor P3 is respectively connected to the input end of the first inverter I1, and the first output end of the latch; the drain of the fourth PMOS transistor P4 is respectively connected to the second The input terminal of the inverter I2 is connected to the second output terminal of the latch; the output terminal OUTP of the first inverter I1 is connected to one of the input terminals of the NAND gate NAND, and the output terminal OUTN of the second inverter I2 It is connected with the other input terminal of the NAND gate NAND, and the output CLKC of the NAND gate is connected with the gate of the second PMOS transistor P2; the substrate of the first PMOS transistor P1 is the body, the body of the second PMOS transistor P2, The bodies of the third PMOS transistor P3 and the fourth PMOS transistor P4 are all grounded; the bodies of all the PMOS transistors in the first inverter I1, the second inverter I2, and the NAND gate NAND are grounded, and all The bodies of the NMOS tubes are all connected to the power supply Vdd.

The latch includes a first NMOS transistor P5, a second NMOS transistor P6, a third NMOS transistor P7, and a fourth NMOS transistor P8; the gate of the first NMOS transistor P5 is used as the first control terminal to connect to the clock signal CLK, and the second NMOS transistor The gate of P6 is used as the second output terminal of the latch, the gate of the third NMOS transistor P7 is used as the first output terminal of the latch, and the gate of the fourth NMOS transistor P8 is used as the second control terminal to connect to the clock signal CLK; The source of the first NMOS transistor P5, the source of the second NMOS transistor P6, the source of the third NMOS transistor P7, and the source of the fourth NMOS transistor P8 are all grounded; the drain of the first NMOS transistor P5, the second NMOS The drain of the transistor P6 is respectively connected to the input terminal of the first inverter I1 and the first output terminal of the latch; the drain of the third NMOS transistor P7 and the drain of the fourth NMOS transistor P8 are respectively connected to the second inverting The input terminal of the device I2 and the second output terminal of the latch are connected; the drain of the third PMOS transistor P3 is respectively connected to the drain of the first NMOS transistor P5, the drain of the second NMOS transistor P6, and the drain of the third NMOS transistor P7 The gates are connected, the drain of the fourth PMOS transistor P4 is respectively connected to the drain of the third NMOS transistor P7, the drain of the fourth NMOS transistor P8, and the gate of the second NMOS transistor P6; the body of the first NMOS transistor P5 , the body pole of the second NMOS transistor P6, the body pole of the third NMOS transistor P7, and the body pole of the fourth NMOS transistor P8 are all connected to the power supply;

In this embodiment, the first NMOS transistor and the fourth NMOS transistor are pull-down NMOS transistors, and the first PMOS transistor and the second PMOS transistor are pull-up PMOS transistors.

In this embodiment, the first output signal of the latch passes through the first inverter I1 to generate the output signal OUTP, and the second output signal of the latch passes through the second inverter I2 to generate the output signal sum OUTN, OUTP and OUTN The output signal CLKC is generated by the NAND gate NAND, and the signal CLKC is used as the gate input signal of the second PMOS transistor to control the turn-on and turn-off of the second PMOS transistor P2.

The comparator shown in Figure 3 has two working states, one is the reset state and the other is the latch state. When the comparator is in the reset state, the clock control signal CLK is high level, the PMOS transistor P1 is turned off, the NMOS transistors P5 and P8 are turned on, and the signal Dip generated by the third PMOS transistor P3 and the signal generated by the fourth PMOS transistor P4 are Din is pulled down to low level 0, through the inverters I1 and I2, the comparator output signals OUTP and OUTN are high level VDD, the output signal CLKC of OUTP and OUTN through the NAND gate NAND is low level, and P2 is turned on; When the clock control signal CLK becomes low level, the latch will enter the regenerative mode. At this time, P1 is turned on, P2 is still turned on, NMOS transistors P5 and P8 are turned off, and the output voltage starts to drop gradually from VDD. The differential voltage at the input terminal and the difference in the current of the two branches cause the voltage at the output terminal to drop at different speeds. Before the output terminal voltage drops to VDD-Vthn, the NMOS transistor P6/P7 is cut off, and the positive feedback process has not yet been established; when the NMOS transistor P6/P7 is turned on, the positive feedback is established, and the output differential voltage starts from the initial differential voltage value V0 by The exponential function relationship increases rapidly; when the output differential voltage increases to a certain level, the latch NMOS tube of one branch will be cut off, the positive feedback process is over, and the corresponding output voltage of the branch is charged/discharged through the branch MOS tube to level VDD/GND. At this time, one of the output signals OUTP and OUTN after the comparison of the comparator is high level, and the other is low level. After they pass through the NAND gate NAND, the output voltage CLKC is high level, and the PMOS transistor P2 is turned off, thus solving the problem. The problem of static power consumption is solved.

In order to further verify the above-mentioned advantages of the present invention, under the SMIC 0.18um 1P6M CMOS process,

The clock frequency is 0.3MHz, the input differential voltage ΔVin is 1mV, Vcm=0.1V, when |Dip-Din| = 0.5VDD, it is considered that the comparator completes the comparison. Use the Cadence simulation tool to simulate the circuit, use excel to analyze the data, and obtain the comparison curve of the comparison time as the power supply voltage VDD changes, as shown in Figure 4, the energy utilization efficiency of the comparator of the present invention is significantly improved.

The clock frequency is 7MHz, the power supply voltage is 0.5 V, when |Dp-Dn| = 0.25V, it is considered that the comparator completes the comparison. The comparison curves of the comparison time of the comparator shown in Figure 3 changing with the input differential signal ΔVin under different common-mode voltages are shown in Figure 5.

The preferred embodiments of the invention disclosed above are only to help illustrate the invention. The preferred embodiments are not exhaustive in all detail, nor are the inventions limited to specific embodiments described. Obviously, many modifications and variations can be made based on the contents of this specification. This description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (2)

1. the high speed dynamic latch comparator that a kind is applied in low voltage environment, it is characterised in that: include the first PMOS (P1), the second PMOS (P2), the 3rd PMOS (P3), the 4th PMOS (P4), the first phase inverter (I1), the second phase inverter (I2), NAND gate (NAND) and latch；Wherein said latch include the first control end, second control end, the first outfan, Second outfan and ground end；

The grid of described first PMOS (P1) connects clock signal (CLK), and the grid of the 2nd PMOS pipe (P2) connects NAND gate Outfan (CLKC), the grid of the 3rd PMOS pipe (P3) connects the first input signal (VIP), and the grid of the 4th PMOS (P4) connects Second input signal (VIN)；

The source electrode of described first PMOS (P1) connects power supply (Vdd), the source electrode of the second PMOS (P2) and the first PMOS (P1) Drain electrode be connected, the source electrode of described 3rd PMOS (P3), the 4th PMOS (P4) source electrode respectively with the second PMOS (P2) Drain electrode connect；

The drain electrode of described 3rd PMOS (P3) connects with the input of the first phase inverter (I1), the first outfan of latch respectively Connect；The drain electrode of described 4th PMOS (P4) connects with the input of the second phase inverter (I2), the second outfan of latch respectively Connect；

The outfan (OUTP) of described first phase inverter (I1) and one of them input of NAND gate (NAND) connect, and second is anti- The outfan (OUTN) of phase device (I2) and another input of NAND gate (NAND) connect；

The substrate i.e. body pole of described first PMOS (P1), the body pole of the second PMOS (P2), the body pole of the 3rd PMOS (P3), The body of the 4th PMOS (P4) extremely all ground connection；In described first phase inverter (I1), the second phase inverter (I2) and NAND gate (NAND) Body extremely all ground connection of all PMOS, the body of all NMOS tube connects power supply (Vdd) the most without exception.

A kind of high speed dynamic latch comparator applied in low voltage environment the most according to claim 1, its feature exists In: described latch includes the first NMOS tube (P5), the second NMOS tube (P6), the 3rd NMOS tube (P7), the 4th NMOS tube (P8)；

The grid of described first NMOS tube (P5) controls terminated clock signal (CLK), the grid of the second NMOS tube (P6) as first Pole is as the second outfan of latch, and the grid of the 3rd NMOS tube (P7) is as the first outfan of latch, the 4th NMOS The grid of pipe (P8) controls terminated clock signal (CLK) as second；

The source electrode of described first NMOS tube (P5), the source electrode of the second NMOS tube (P6), the source electrode of the 3rd NMOS tube (P7), the 4th The source electrode of NMOS tube (P8) connect altogether after as earth terminal ground connection；

The drain electrode of described first NMOS tube (P5), the second NMOS tube (P6) drain electrode respectively with the input of the first phase inverter (I1) End, the first outfan of latch connect；The drain electrode of described 3rd NMOS tube (P7), the 4th NMOS tube (P8) drain electrode respectively with The input of the second phase inverter (I2), the second outfan of latch connect；

The drain electrode of described 3rd PMOS (P3) respectively with the drain electrode of the first NMOS tube (P5), the drain electrode of the second NMOS tube (P6), The grid of the 3rd NMOS tube (P7) is connected, the drain electrode of described 4th PMOS (P4) respectively with the drain electrode of the 3rd NMOS tube (P7), The drain electrode of the 4th NMOS tube (P8), the grid of the second NMOS tube (P6) are connected；

The substrate i.e. body pole of described first NMOS tube (P5), the body pole of the second NMOS tube (P6), the body pole of the 3rd NMOS tube (P7), The body of the 4th NMOS tube (P8) the most all connects power supply (Vdd).