CN102270984B - Positive high voltage level conversion circuit - Google Patents

Abstract

The invention discloses a positive high-voltage level conversion circuit belonging to the technical field of integrated circuit design. The connection relationship of the present invention is as follows: the VIN input voltage is connected to the common node of the INV1 inverter and the first bootstrap circuit, the INV1 inverter is also connected to the second bootstrap circuit, and the voltage conversion circuit is connected to the first bootstrap circuit and the first bootstrap circuit respectively. Two bootstrap circuits and VOUT output voltage connections. The invention has the beneficial effects of simple circuit structure, fast switching speed and low power consumption. The two bootstrap circuits double the swing of the low-voltage control signal, which enhances the driving capability of the two high-voltage NMOS transistors in the voltage conversion circuit, thereby reducing the pull-down and pull-up of the NMOS transistor in the voltage conversion process of the voltage conversion circuit. Serious competition between PMOS transistors reduces the power consumption of high-voltage conversion, and the invention can still work normally under very low power supply voltage.

Description

A positive high voltage level conversion circuit

technical field

The invention belongs to the technical field of integrated circuit design, and in particular relates to a positive high-voltage level conversion circuit.

Background technique

At present, flash memory (Flash memory) is widely used in portable devices such as mobile phones, cameras, and handheld computers. It has the advantages of not losing data when power is turned off, high programming speed, and high integration. FIG. 1 is a cross-sectional view of a conventional flash memory unit, which is a stacked gate structure composed of a polysilicon control gate 10 and a floating gate 12 . On the p-type substrate 16, a source 14 and a drain 15 of n+ structure are formed by implantation. In addition, the floating gate 12 is isolated from the p-type substrate 16 by the second insulating layer 13 , and the polysilicon control gate 10 is isolated from the floating gate 12 by the first insulating layer 11 . This stacked gate structure makes the threshold voltage of the memory cell seen from the polysilicon control gate 10 depend on the number of electrons in the floating gate 12 .

The flash memory unit adopts Fowler-Nordheim (abbreviated as F-N) tunneling effect to perform programming and erasing operations. Table 1 shows typical voltages on the control gate, drain, and source of the flash memory cell during various operations.

operate control grid Drain region source region programming 10V -5V -5V erase -5V 10V 10V read 2.5V 0.8V 0V

Table 1

It can be seen from the above table that when the memory performs different operations, a positive high voltage needs to be applied, which requires a positive high voltage level conversion circuit that can convert the input data into a corresponding positive high voltage.

Figure 2 is a traditional positive high voltage level shifting circuit. When the IN input voltage is 0V, the INV inverter outputs a high-level voltage, so the NMOS transistor 204 is turned on, so that the PMOS transistor 201 is also turned on. Therefore, the N node voltage is pulled up to the positive high voltage of VPH, which makes the PMOS transistor 203 turned off, so the output voltage of OUT is VSS ground potential.

When the VIN input voltage is the VDD supply voltage, the NMOS transistor 202 is turned on, so that the PMOS transistor 203 is turned on. Therefore, the OUT output voltage is pulled to VPH positive high voltage. In addition, the NMOS transistor 204 is turned off, cutting off the direct current path from the positive high voltage of VPH to the ground potential of VSS, and the output voltage of OUT remains at the positive high voltage of VPH. It can be seen that the OUT output voltage can be switched between the VPH positive high voltage and the VSS ground potential, thereby completing the control and switching of the IN input voltage to the VPH positive high voltage.

However, for the conventional positive high-voltage level switching circuit shown in FIG. 2, when the VDD power supply voltage decreases, the gate drive voltages of the NMOS transistor 202 and the NMOS transistor 204 decrease, so their conduction capabilities will decrease, resulting in a level shifting process The competition between PMOS transistors and NMOS transistors intensifies, resulting in large level conversion delays and conversion power consumption. When the VDD power supply voltage drops further, there may even be a problem that the circuit cannot switch the high voltage normally. The method of simply increasing the size of the NMOS transistor will lead to a sharp increase in the area of the switching circuit, which increases the process cost. In addition, due to the large number of word lines and bit lines in the flash memory system, the performance degradation of the high-voltage switching circuit will seriously affect the performance of the entire flash memory system.

Contents of the invention

The object of the present invention is to disclose a positive high-voltage level conversion circuit for the above defects. Its connection relationship is as follows: the VIN input voltage is connected to the common node of the INV1 inverter and the first bootstrap circuit, the INV1 inverter is also connected to the second bootstrap circuit, and the voltage conversion circuit is connected to the first bootstrap circuit and the second bootstrap circuit respectively. Bootstrap circuit and VOUT output voltage connection.

The connection relationship of the first bootstrap circuit is as follows: the VIN input voltage is respectively connected to the input terminal of the first inverter, the gate of the second PMOS transistor and the gate of the first NMOS transistor, the first inverter and the first The capacitors are connected in series, the N1 node is respectively connected to the first capacitor, the drain of the first PMOS transistor, and the source of the second PMOS transistor, and the N2 node is respectively connected to the gate of the first PMOS transistor, the gate of the third NMOS transistor, and the second PMOS transistor. The drain of the transistor and the drain of the first NMOS transistor, the VDD supply voltage are respectively connected to the substrate of the second PMOS transistor and the source and substrate of the first PMOS transistor, and the source and substrate of the first NMOS transistor are connected to VSS ground potential.

The connection relationship of the second bootstrap circuit is as follows: the N0 node is respectively connected to the output terminal of the INV1 inverter, the input terminal of the second inverter, the gate of the fourth PMOS transistor and the gate of the second NMOS transistor. Two inverters are connected in series with the second capacitor, the N3 node is respectively connected to the second capacitor, the drain of the third PMOS transistor and the source of the fourth PMOS transistor, and the N4 node is respectively connected to the gate of the third PMOS transistor and the fourth NMOS transistor The gate of the gate, the drain of the fourth PMOS transistor and the drain of the second NMOS transistor, the VDD power supply voltage is respectively connected to the substrate of the fourth PMOS transistor and the source and substrate of the third PMOS transistor, the source of the second NMOS transistor Both pole and substrate are connected to VSS ground potential.

The connection relationship of the voltage conversion circuit is as follows: the VPH positive high voltage is respectively connected to the source and substrate of the fifth PMOS transistor and the source and substrate of the sixth PMOS transistor, and the VSS ground potential is respectively connected to the source and substrate of the third NMOS transistor. Substrate and the source of the sixth PMOS transistor and the substrate, the gate of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor, the drain of the fourth NMOS transistor and the common node of the VOUT output voltage, the sixth PMOS transistor The gate is connected to a common node of the drains of the fifth PMOS transistor and the drain of the third NMOS transistor.

The invention has the beneficial effects of simple circuit structure, fast switching speed and low power consumption. The two bootstrap circuits double the swing of the low-voltage control signal, which enhances the driving capability of the two high-voltage NMOS transistors in the voltage conversion circuit, thereby reducing the pull-down and pull-up of the NMOS transistor in the voltage conversion process of the voltage conversion circuit. Serious competition between PMOS transistors reduces the power consumption of high-voltage conversion, and the invention can still work normally under very low power supply voltage.

Description of drawings

FIG. 1 is a cross-sectional view of a conventional flash memory storage unit;

Figure 2, a schematic structural diagram of a traditional positive high-voltage level conversion circuit;

Fig. 3, an embodiment of the positive voltage level conversion circuit that the present invention proposes;

Fig. 4 shows another embodiment of the positive voltage level conversion circuit proposed by the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 3, the connection relationship of a positive high-voltage level conversion circuit is as follows: the VIN input voltage is connected to the common node of the INV1 inverter 40 and the first bootstrap circuit 41, and the INV1 inverter 40 is also connected to the second bootstrap circuit The circuit 42 is connected, and the voltage conversion circuit 43 is respectively connected with the first bootstrap circuit 41 , the second bootstrap circuit 42 and the VOUT output voltage.

The connection relationship of the first bootstrap circuit 41 is as follows: the VIN input voltage is respectively connected to the input terminal of the first inverter 4101, the gate of the second PMOS transistor 4104 and the gate of the first NMOS transistor 4105, and the first inverter 4101 It is connected in series with the first capacitor 4102, the N1 node is respectively connected to the first capacitor 4102, the drain of the first PMOS transistor 4103 and the source of the second PMOS transistor 4104, and the N2 node is respectively connected to the gate of the first PMOS transistor 4103 and the third NMOS The gate of the transistor 4302, the drain of the second PMOS transistor 4104 and the drain of the first NMOS transistor 4105, the VDD power supply voltage are respectively connected to the substrate of the second PMOS transistor 4104 and the source and substrate of the first PMOS transistor 4103, Both the source and the substrate of the first NMOS transistor 4105 are connected to the VSS ground potential.

The connection relationship of the second bootstrap circuit 42 is as follows: the N0 node is respectively connected to the output terminal of the INV1 inverter 40, the input terminal of the second inverter 4201, the gate of the fourth PMOS transistor 4204, and the gate of the second NMOS transistor 4205. pole, the second inverter 4201 is connected in series with the second capacitor 4202, the N3 node is respectively connected to the second capacitor 4202, the drain of the third PMOS transistor 4203 and the source of the fourth PMOS transistor 4204, and the N4 node is respectively connected to the third PMOS transistor The gate of 4203, the gate of the fourth NMOS transistor 4304, the drain of the fourth PMOS transistor 4204 and the drain of the second NMOS transistor 4205, and the VDD supply voltage are respectively connected to the substrate of the fourth PMOS transistor 4204 and the third PMOS transistor The source and substrate of 4203, and the source and substrate of the second NMOS transistor 4205 are both connected to VSS ground potential.

The connection relationship of the voltage conversion circuit 43 is as follows: VPH positive high voltage is respectively connected to the source and substrate of the fifth PMOS transistor 4301 and the source and substrate of the sixth PMOS transistor 4303, and the VSS ground potential is respectively connected to the source of the third NMOS transistor 4302. electrode and substrate and the source and substrate of the sixth PMOS transistor 4303, the fifth PMOS transistor 4301 and the sixth PMOS transistor 4303 are cross-coupled, the gate of the fifth PMOS transistor 4301 is connected to the drain of the sixth PMOS transistor 4303, The drain of the fourth NMOS transistor 4304 is the common node of the VOUT output voltage, and the gate of the sixth PMOS transistor 4303 is connected to the common node of the drain of the fifth PMOS transistor 4301 and the drain of the third NMOS transistor 4302 .

As shown in Figure 3, it is an embodiment of a positive high-voltage level conversion circuit, and its working principle is as follows:

Set the VDD power supply voltage to 1.5V, the VSS ground potential to 0V, and the VPH positive high voltage to 7.5V. The first bootstrap circuit 41 and the second bootstrap circuit 42 are important components of a positive high-voltage level shifting circuit, and both work on the same principle. Taking the first bootstrap circuit 41 as an example, the VIN input voltage is 1.5V , the voltage at the output terminal of the first inverter 4101 is 0V, the source of the first NMOS transistor 4105 is connected to the VSS ground potential, the first NMOS transistor 4105 is turned on, and the second PMOS transistor 4104 is turned off. At this time, the voltage of the N2 node is 0V, the first PMOS transistor 4103 is turned on due to the voltage feedback of the N2 node, so the voltage of the N1 node is 1.5V.

When the VIN input voltage is reversed from 1.5V to 0V, the voltage at the output terminal of the first inverter 4101 is reversed to 1.5V. Due to the charge retention characteristic of the first capacitor 4102, the voltage of the N1 node will be 3V. At this time, the second PMOS transistor 4104 is turned on, and the first NMOS transistor 4105 is turned off because the gate is connected to the VIN input voltage, so the voltage of the N2 node is 3V. In addition, the first PMOS transistor 4103 is turned off due to the voltage feedback of the N2 node, so that the voltage of the N1 node remains at 3V.

It can be seen from the above analysis that the first bootstrap circuit 41 and the second bootstrap circuit 42 utilize the charge retention characteristics of capacitors. When the input signal swing ranges from 0V to 1.5V, the output signal swing ranges from 0V to 1.5V. 3V, thus voltage bootstrap function for low voltage signals.

1) When the VIN input voltage is 1.5V, the N0 node voltage is 0V. According to the above analysis of the working principle of the bootstrap circuit, the N2 node voltage is 3V. Since the second capacitor 4202 has a charge retention characteristic, the voltage of the N3 node jumps is 3V, and the N4 node (output node) voltage is 3V. At this time, since the N2 node and the N4 node are respectively connected to the gates of the third NMOS transistor 4302 and the fourth NMOS transistor 4304, the third NMOS transistor 4302 is turned off, and the fourth NMOS transistor 4302 is turned off. The transistor 4304 is turned on, and the driving voltage is 3V, so the VOUT output voltage is 0V, the fifth PMOS transistor 4301 is turned on due to the feedback of the VOUT output voltage, the N5 node voltage is 7.5V, therefore, the sixth PMOS transistor 4303 is turned off, The VOUT output voltage thus remains at 0V.

2) When the VIN input voltage jumps from 1.5V to 0V, the N0 node voltage is 1.5V. According to the analysis of the working principle of the bootstrap circuit above, since the first capacitor 4102 has charge retention characteristics, the voltage of the N1 node jumps to 3V, and after the transmission of the second PMOS transistor 4104, the voltage of the N2 node is 3V, and the N4 node (output node) The voltage is 0V. At this time, since the N2 node and the N4 node are respectively connected to the gates of the third NMOS transistor 4302 and the fourth NMOS transistor 4304, the fourth NMOS transistor 4304 is turned off, the third NMOS transistor 4302 is turned on, the voltage of the N5 node is 0V, and the sixth The PMOS transistor 4303 is turned on due to the voltage feedback of the N5 node, so the output voltage of VOUT is 7.5V. At the same time, the fifth PMOS transistor 4301 is turned off due to the feedback of the VOUT output voltage, so that the VOUT output voltage remains at 7.5V.

From the above analysis, it can be seen that the positive high voltage level conversion circuit adopts the circuit bootstrap technology to increase the driving voltage of the NMOS transistor in the voltage conversion circuit 43 by 2 times, which reduces the competition between the NMOS transistor and the PMOS transistor during high voltage conversion, thereby improving the voltage. Level conversion speed, reducing the transient current and dynamic power consumption of level conversion. The third NMOS transistor 4302 and the fourth NMOS transistor 4304 play a selection role. When the system power supply voltage drops continuously, the positive high-voltage level conversion circuit can still work normally.

As shown in FIG. 4, it is another embodiment of the present invention. Compared with FIG. 3, a fifth NMOS transistor 4106 and a sixth NMOS transistor 4206 are added. The gate of the fifth NMOS transistor 4106 is connected to the VDD power supply voltage, and the drain is connected to the VDD power supply voltage. N2 node, the source is connected to the drain of the first NMOS transistor 4105, the substrate is connected to the VSS ground potential; the gate of the sixth NMOS transistor 4206 is connected to the VDD power supply voltage, the drain is connected to the N4 node, and the source is connected to the second NMOS transistor 4205. The drain, the substrate is connected to the VSS ground potential; the fifth NMOS transistor 4106 and the sixth NMOS transistor 4206 play the role of reducing the drain-source voltage of the first NMOS transistor 4105 and the second NMOS transistor 4205 respectively, so that the first NMOS transistor 4105 And the second NMOS transistor 4205 can be a transistor with a low withstand voltage.

Although the present invention has been described and explained in detail in conjunction with FIG. 3 and FIG. 4, it should be understood that any changes to the form and details of the present invention without departing from the spirit and scope of the present invention shall be included in the claims of the present invention. within range.

Claims (3)

1. A positive high-voltage level conversion circuit, characterized in that its connection relationship is as follows: the VIN input voltage is connected to the common node of the INV1 inverter (40) and the first bootstrap circuit (41), and the INV1 inverter ( 40) It is also connected to the second bootstrap circuit (42), and the voltage conversion circuit (43) is respectively connected to the first bootstrap circuit (41), the second bootstrap circuit (42) and the VOUT output voltage; The connection relationship of the first bootstrap circuit (41) is as follows: the VIN input voltage is respectively connected to the input terminal of the first inverter (4101), the gate of the second PMOS transistor (4104) and the first NMOS transistor (4105) The gate of the first inverter (4101) is connected in series with the first capacitor (4102), and the N1 node is respectively connected to the first capacitor (4102), the drain of the first PMOS transistor (4103) and the second PMOS transistor (4104) The source of the N2 node is respectively connected to the gate of the first PMOS transistor (4103), the gate of the third NMOS transistor (4302), the drain of the second PMOS transistor (4104) and the drain of the first NMOS transistor (4105) The VDD power supply voltage is respectively connected to the substrate of the second PMOS transistor (4104) and the source and substrate of the first PMOS transistor (4103), and the source and substrate of the first NMOS transistor (4105) are both connected to VSS ground potential . 2. A positive high-voltage level conversion circuit according to claim 1, characterized in that, the connection relationship of the second bootstrap circuit (42) is as follows: the N0 node is respectively connected to the output of the INV1 inverter (40) terminal, the input terminal of the second inverter (4201), the gate of the fourth PMOS transistor (4204) and the gate of the first NMOS transistor (4205), the second inverter (4201) and the second capacitor (4202) connected in series, the N3 node is respectively connected to the second capacitor (4202), the drain of the third PMOS transistor (4203) and the source of the fourth PMOS transistor (4204), and the N4 node is respectively connected to the gate of the third PMOS transistor (4203), The gate of the fourth NMOS transistor (4304), the drain of the fourth PMOS transistor (4204) and the drain of the second NMOS transistor (4205), and the VDD supply voltage are respectively connected to the substrate of the fourth PMOS transistor (4204) and the second The sources and substrates of the three PMOS transistors (4203), and the source and substrate of the second NMOS transistor (4205) are connected to the VSS ground potential. 3. A positive high voltage level conversion circuit according to claim 1, characterized in that the connection relationship of the voltage conversion circuit (43) is as follows: VPH positive high voltage is respectively connected to the source of the fifth PMOS transistor (4301) and the substrate, and the source and substrate of the sixth PMOS transistor (4303), the VSS ground potential is respectively connected to the source and substrate of the third NMOS transistor (4302) and the source and substrate of the fourth NMOS transistor (4304) , the gate of the fifth PMOS transistor (4301) is connected to the drain of the sixth PMOS transistor (4303), the drain of the fourth NMOS transistor (4304) and the common node of the VOUT output voltage, the gate of the sixth PMOS transistor (4303) The drains of the five PMOS transistors (4301) and the drains of the third NMOS transistors (4302) are connected to a common node. the

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