CN111277261B - Level conversion circuit - Google Patents

Abstract

The present invention provides a level shift circuit, the circuit comprising: a first pull-up transistor, a second pull-up transistor, an inverter, at least one first pull-down transistor, at least one first regulation circuit, at least one second pull-down transistor, at least one second regulation circuit; the first regulating circuit is provided with a first port, a second port and a third port, wherein the first port of the first regulating circuit is connected with a first node, the second port is grounded, and the third port is connected with a first signal end; the second regulating circuit is provided with a first port, a second port and a third port, wherein the first port of the second regulating circuit is connected with the second node, the second port is grounded, and the third port is connected with the second signal end. The circuit structure of the invention is simpler, and the output end of the level conversion circuit can successfully realize the high-low level turnover even if the input signal turnover speed is higher under the condition that the voltage change amplitude of the power end is larger.

Description

A level conversion circuit

Technical field

The present invention relates to the technical field of electronic circuits, and in particular to a level conversion circuit.

Background technique

In integrated chips, I/O circuits and core circuits are usually included. Among them, the I/O circuit is used to realize bidirectional data transmission between the core circuit and the external circuit of the integrated chip. However, the power supply voltage of the core circuit is usually different from the power supply voltage of the external circuit. Therefore, the I/O circuit needs to have voltage conversion capability (that is, the I/O circuit needs to include a level conversion circuit) to convert the core circuit into The power supply voltage is converted to a power supply voltage suitable for the external circuit and output to the external circuit. However, as the functions of integrated chip products become more and more diversified, integrated chips are usually connected to different external circuits, and the level conversion circuits in the I/O circuits should also be equipped with the power supply of the core circuits. The ability to convert voltage to many different voltages.

The level conversion circuit in the related art is shown in Figure 1. In the circuit shown in Figure 1, when the voltage input to the input terminal In is a low-level signal, the NMOS tube 4 and the PMOS tube 1 are turned on, and the PMOS tube 2 and NMOS tube 3 are turned off, and the output voltage of the output terminal Out is 0V; when the input voltage of the input terminal In is the high-level signal VDDC, NMOS tube 3 and PMOS tube 2 are turned on, NMOS tube 4 and PMOS tube 1 are turned off, and the output The output voltage at terminal Out is VDDIO. Based on this, by changing the magnitude of voltage VDDIO, the level conversion circuit can convert the input voltage VDDC into different voltage outputs.

However, in the level conversion circuit of the related art, when the voltage VDDIO is small or large, and when the input signal flips too fast, the output end cannot successfully flip between high and low levels.

Contents of the invention

The purpose of the present invention is to provide a level conversion circuit to solve the problem that the output end of the level conversion circuit in the related art cannot successfully realize high and low levels when the power supply terminal voltage VDDIO is small or large and the input signal flip speed is fast. Technical issues with flipping.

In order to solve the above technical problems, the present invention provides a level conversion circuit. The circuit includes: a first pull-up transistor, a second pull-up transistor, an inverter, at least one first pull-down transistor, at least one first pull-down transistor. a regulating circuit, at least one second pull-down transistor, and at least one second regulating circuit;

The gate of the first pull-down transistor is connected to the input terminal, the source is connected to ground, and the drain is connected to the first node; the drain of the first pull-up transistor is connected to the first node, the gate is connected to the second node, and the source is connected to the power supply terminal; conversely The input end of the phase device is connected to the gate of the first pull-down transistor, and the output end is connected to the gate of the second pull-down transistor; the source of the second pull-down transistor is connected to ground, and the drain is connected to the second node; the drain of the second pull-up transistor is The second node is connected, the gate is connected to the first node, and the source is connected to the power terminal; the second node is connected to the output terminal; the first adjustment circuit has a first port, a second port and a third port, and the third port of the first adjustment circuit One port is connected to the first node, the second port is grounded, and the third port is connected to the first signal terminal; the second adjustment circuit has a first port, a second port and a third port, and the first port of the second adjustment circuit is connected to the first signal terminal. Two nodes, the second port is grounded, and the third port is connected to the second signal terminal;

Wherein, when the voltage of the power supply terminal is greater than or equal to a predetermined voltage, the first signal terminal is used to provide a turn-on voltage to the first regulation circuit, so that the first regulation circuit is turned on, so that the output of the first node The signal can flip to a low level signal; the second signal terminal is used to provide a turn-on voltage to the second adjustment circuit to turn on the second adjustment circuit, so that the output signal of the second node can flip to a low level. level signal;

When the voltage of the power supply terminal is less than a predetermined voltage, the first signal terminal is used to provide a cut-off voltage to the first regulation circuit to turn off the first regulation circuit so that the output signal of the first node can flip to a high-level signal; the second signal terminal is used to provide a cut-off voltage to the second adjustment circuit to turn off the second adjustment circuit, so that the output signal of the second node can flip to a high-level signal.

Optionally, the first adjustment circuit includes a first switching transistor and a first adjustment transistor connected in series with each other, and the second adjustment circuit includes a second switching transistor and a second adjustment transistor connected in series with each other;

The drain of the first switching transistor serves as the first port of the first adjustment circuit and is connected to the first node, and the gate of the first switching transistor serves as the third port of the first adjustment circuit and is connected to the first node. The first signal terminal is connected, the source of the first switching transistor is connected to the drain of the first adjustment transistor, and the gate of the first adjustment transistor is connected to the gate of the first pull-down transistor, The source of the first adjustment transistor is connected to ground as the second port of the first adjustment circuit;

The drain of the second switching transistor serves as the first port of the second adjustment circuit and is connected to the second node, and the gate of the second switching transistor serves as the third port of the second adjustment circuit and is connected to the second node. The second signal terminal is connected, the source of the second switching transistor is connected to the drain of the second adjustment transistor, and the gate of the second adjustment transistor is connected to the gate of the second pull-down transistor, so The source of the second adjustment transistor is connected to ground as the second port of the second adjustment circuit;

And, when the voltage of the power supply terminal is greater than or equal to the predetermined voltage, the first signal terminal is used to input a turn-on voltage to the gate of the first switching transistor to turn on the first switching transistor; The second signal terminal is used to input a turn-on voltage to the gate of the second switching transistor to turn on the second switching transistor.

When the voltage of the power supply terminal is less than the predetermined voltage, the first signal terminal is used to output a cut-off voltage to the gate of the first switching transistor to turn off the first switching transistor; the second The signal terminal is used to output a cut-off voltage to the gate of the second switching transistor to turn off the second switching transistor.

Optionally, the first pull-down transistor and the second pull-down transistor have the same polarity, the first pull-up transistor and the second pull-up transistor have the same polarity, and the first pull-down transistor The polarity of the first pull-up transistor is opposite.

Optionally, the first adjustment transistor and the first pull-down transistor have the same polarity, and the second adjustment transistor and the second pull-down transistor have the same polarity.

Optionally, the first pull-down transistor and the second pull-down transistor are both NMOS transistors, the first pull-up transistor and the second pull-up transistor are both PMOS transistors, and the first adjustment transistor and The second adjustment transistors are all NMOS transistors.

Optionally, the first signal terminal and the second signal terminal are the same signal terminal.

Optionally, the first switching transistor and the second switching transistor have the same polarity.

Optionally, both the first switching transistor and the second switching transistor are NMOS transistors.

Optionally, both the first signal terminal and the second signal terminal include a comparison circuit, and both the first signal terminal and the second signal terminal are connected to the power supply terminal for receiving signals from the power supply terminal. voltage value and compares the voltage value with a predetermined voltage.

Optionally, the first pull-down transistor and the second pull-down transistor have the same size; the first pull-up transistor and the second pull-up transistor have the same size.

To sum up, the level conversion circuit provided by the present invention includes at least one first adjustment circuit and at least one second adjustment circuit. And, in the present invention, when the voltage at the power supply terminal is large and the pull-up capability of the level conversion circuit is strong, the first adjustment circuit and the second adjustment circuit can be turned on to correspondingly improve the level conversion. The pull-down ability of the circuit avoids the phenomenon that the pull-up ability of the level conversion circuit is much greater than the pull-down ability, so that the signal at the output end of the level conversion circuit can quickly flip to a low-level signal. And, when the voltage at the power supply terminal is small and the pull-up capability of the level conversion circuit is weak, the first adjustment circuit and the second adjustment circuit can be disconnected to correspondingly reduce the pull-down capability of the level conversion circuit to avoid The phenomenon occurs that the pull-up capability of the level conversion circuit is much smaller than the pull-down capability, so that the signal at the output end of the level conversion circuit can quickly flip to a high-level signal.

Therefore, for the level conversion circuit of the present invention, when the voltage at the power supply terminal changes greatly and the pull-up capability of the level conversion circuit is greatly reduced or increased, by controlling the first adjustment circuit and the second adjustment circuit The conduction or disconnection of the circuit can flexibly adjust the pull-down capability of the level conversion circuit to avoid the situation where the pull-up capability of the level conversion circuit is far different from the pull-down capability and ensure that the output end can operate in a short period of time. Quickly output a high level signal or a low level signal within a certain period of time. Even if the signal flip speed of the input signal is relatively fast, it can still be ensured that the output terminal can successfully flip between high and low levels, so that the level conversion circuit can adapt to the diversified needs of current chip products.

In addition, the structure of the level conversion circuit provided by the present invention is also relatively simple.

Description of the drawings

Figure 1 is a schematic structural diagram of a level conversion circuit provided by related technologies;

FIG. 2 is a schematic structural diagram of a level conversion circuit provided by an embodiment of the present invention.

Detailed ways

As mentioned in the background art, the level conversion circuit in the related art is generally shown in Figure 1. Specifically, the level conversion circuit includes two PMOS transistors 1 and 2, two NMOS transistors 3 and 4, and an inverter. Phaser 5. Among them, the sources of PMOS tubes 1 and 2 are both connected to the power terminal VDDIO; the gate of PMOS tube 2 is connected to node a, and the drain of PMOS tube 2 is connected to node b; the gate of PMOS tube 1 is connected to node b, and the PMOS tube 2 is connected to node b. 1Drain is connected to node a. The gate of NMOS tube 3 is connected to the input terminal In and the input terminal of inverter 5, the drain of NMOS tube 3 is connected to node a, and the source of NMOS tube 3 is connected to ground; the gate of NMOS tube 4 is connected to the output of inverter 5 terminal, the drain of NMOS tube 4 is connected to node b, and the source of NMOS tube 4 is connected to ground.

Wherein, when the input terminal In of the level conversion circuit inputs a low-level signal, the gate of the NMOS transistor 3 receives the low-level signal, and the NMOS transistor 3 is turned off. At the same time, the low-level signal passes through the inverter. The inverter 5 inverts a high-level signal and inputs it to the gate of the NMOS transistor 4. The NMOS transistor 4 is turned on, and the charge at point b flows to the ground through the NMOS transistor 4, so that the voltage at point b is pulled down to a low potential, thereby The output terminal Out of the level conversion circuit is caused to output a low-level signal. At the same time, based on the voltage at point b being low, the PMOS tube 1 is turned on, and the charge of the power supply terminal VDDIO flows to the node a through the PMOS tube 1, so that the point a The potential is pulled up to a high potential, and PMOS tube 2 is turned off.

And, when the input terminal In input is a high-level signal VDDC, the NMOS transistor 3 is turned on, and the charge of the node a flows to the source of the NMOS transistor 3, so that the voltage of the node a is pulled down to a low-level signal, and the PMOS transistor 2 is turned on, the charge at the power terminal VDDIO flows to the node b through the PMOS transistor 2, then the voltage of the node b is pulled up to a high-level signal VDDIO, and the output terminal Out outputs the high-level signal VDDIO. At the same time, the high-level signal VDDC input from the input terminal In is inverted into a low-level signal through the inverter 5 and input to the gate of the NMOS transistor 4, and the NMOS transistor 4 is turned off.

It can be seen from the above that in the related art, when the voltage input to the input terminal In of the level conversion circuit is a low-level signal, the NMOS tube 4 and the PMOS tube 1 are turned on, the PMOS tube 2 and the NMOS tube 3 are turned off, and the output terminal Out The output voltage is a low-level signal 0V; when the input voltage of the input terminal In is a high-level signal VDDC, NMOS tube 3 and PMOS tube 2 are turned on, NMOS tube 4 and PMOS tube 1 are turned off, and the output voltage of the output terminal Out is High level signal VDDIO. Based on this, by changing the voltage of the power terminal VDDIO, the level conversion circuit can convert the input voltage VDDC into different voltage outputs.

However, it should be noted that due to the short delay between the input signal and the output signal, when the signal at the output terminal flips from a low-level signal to a high-level signal, PMOS tube 2 and NMOS tube 4 will be turned on at the same time. The phenomenon. At this time, for the level conversion circuit in the related art, when the voltage of VDDIO is small, the drain current of the PMOS tube 2 is also correspondingly small, which will cause the charge of the power supply terminal VDDIO to flow to the node b as fast as It is greatly reduced, that is, the pull-up ability of the charge at node b is weak. At this time, when PMOS transistor 2 and NMOS transistor 4 are turned on at the same time, compared with the weak pull-up ability of the charge at node b when the power supply terminal VDDIO voltage is small, the pull-down ability of NMOS transistor 4 to pull down the charge at node b is stronger. , so that the charge pull-down ability at node b is much greater than the charge pull-up ability. Then when the PMOS transistor 2 and the NMOS transistor 4 are turned on at the same time, the speed of the charge flowing to the node b via the PMOS transistor 2 is smaller than the speed of the charge flowing out of the node b via the NMOS transistor 4, so that the node b (that is, the output It takes a long time for the charge at terminal Out) to reach the high-level signal, so it cannot quickly flip to the high-level signal. At this time, if the signal flip speed of the input signal is fast, it is very likely that the output terminal Out will not be able to output a high-level signal, which will affect the subsequent circuit function.

Similarly, due to the short delay between the input signal and the output signal, when the signal at the output terminal flips from a high-level signal to a low-level signal, the PMOS tube 2 and the NMOS tube 4 will also be turned on at the same time. . At this time, for the level conversion circuit in the related art, when the voltage of VDDIO is relatively large, the drain current of the PMOS tube 2 is also correspondingly large, which causes the charge of the power supply terminal VDDIO to flow to the node b. The speed is greatly improved, that is, the pull-up ability of the charge at node b is stronger. At this time, when the PMOS transistor 2 and the NMOS transistor 4 are turned on at the same time, the pull-down ability of the charge at node b will be much smaller than the charge pull-up ability, so that the signal at node b cannot quickly flip to a low-level signal. Based on this, if the signal flip speed of the input signal is fast, it is very likely that the output terminal Out will not be able to output a low-level signal, which will affect the circuit function of the subsequent circuit.

And, it should also be noted that when the voltage of the power supply terminal VDDIO is large, the drain current of the PMOS tube 2 is large, then when the PMOS tube 2 is turned on and the NMOS tube 4 is turned off, the charge flows from the power supply terminal VDDIO to the node. The speed of b is also faster, that is, the pull-up ability of the charge at node b is stronger, so that node b can accumulate more charges and output a high-level signal. At this time, if the output terminal Out (i.e., node b) is to be flipped from a high-level signal to a low-level signal, the PMOS transistor 2 will be turned off and the NMOS transistor 4 will be turned on, so that the NMOS transistor 4 can be used to pull down the node. The charge at b. However, compared with the strong pull-up ability of the charge at node b when the voltage of the power supply terminal VDDIO is large, the pull-down ability of the charge at node b by the NMOS transistor 4 is weak, and the pull-down ability of the charge at node b will occur. The phenomenon of being far less than the charge pull-up capability makes it take a long time for the charge signal at the node b (that is, the output terminal Out) to become a low-level signal, and cannot quickly flip to a low-level signal. At this time, if the signal flip speed of the output signal is fast, the output terminal Out will also be unable to output a low-level signal, which will affect subsequent circuit operations.

In addition, based on the symmetry of the level conversion circuit, when the voltage of VDDIO is larger or smaller, and the signal flip speed of the input signal is faster, the flip of the high and low level signals cannot be successfully achieved at node a, making it impossible to reasonably Controlling the on and off of the PMOS transistor 2 also makes it impossible to successfully output a low-level signal or a high-level signal at the node b, and the level conversion cannot be realized.

It can be seen from this that for the level conversion circuit in the related art, the pull-down capability cannot be adjusted in the level conversion circuit in the related art. In this way, when the pull-up capability of the level conversion circuit changes significantly due to a large change in VDDIO, there will definitely be a gap between the pull-up capability and the pull-down capability of the level conversion circuit, resulting in a faster switching speed of the high and low levels of the output signal. slow. At this time, when the signal flip speed of the input signal is relatively fast, the output end cannot successfully flip the high and low level signals.

The present invention mainly proposes a level conversion circuit to solve the above technical problems. The level conversion circuit proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.

Figure 2 is a schematic structural diagram of a level conversion circuit provided by an embodiment of the present invention. As shown in Figure 2, the circuit includes: a first pull-up transistor P1, a second pull-up transistor P2, an inverter O1, and at least A first pull-down transistor N1 (the present invention takes one as an example to illustrate), at least one first adjustment circuit O2 (the present invention takes one as an example to illustrate), at least one second pull-down transistor N2 (the present invention (Including one for illustration) and at least one second regulating circuit 03.

Wherein, the gate of the first pull-down transistor N1 is connected to the input terminal In, the source of the first pull-down transistor N1 is connected to ground, and the drain of the first pull-down transistor N1 is connected to the first node A. The input terminal of the inverter 01 is connected to the gate of the first pull-down transistor N1, and the output terminal of the inverter 01 is connected to the gate of the second pull-down transistor N2. The source of the second pull-down transistor N2 is connected to ground, and the drain of the second pull-down transistor N2 is connected to the second node B. The drain of the first pull-up transistor P1 is connected to the first node A, the gate of the first pull-up transistor P1 is connected to the second node B, and the source of the first pull-up transistor P1 is connected to the power terminal VDDIO. The drain of the second pull-up transistor P2 is connected to the second node B, the gate of the second pull-up transistor P2 is connected to the first node A, and the source of the second pull-up transistor P2 is connected to the power terminal VDDIO.

In this embodiment, the first pull-down transistor N1 and the second pull-down transistor N2 have the same polarity, and the first pull-up transistor P1 and the second pull-up transistor P2 have the same polarity, The first pull-down transistor N1 and the first pull-up transistor P1 have opposite polarities. For example, the first pull-down transistor and the second pull-down transistor may be NMOS transistors, and the first pull-up transistor and the second pull-up transistor may be PMOS transistors.

And, continuing to refer to Figure 2, the first port of the first adjustment circuit 02 is connected to the first node A, the second port of the first adjustment circuit 02 is grounded, and the third port of the second adjustment circuit 02 Connect the first signal terminal 04. The first port of the second adjustment circuit 03 is connected to the second node B, the second port of the first adjustment circuit 03 is grounded, and the third port of the second adjustment circuit 03 is connected to the second signal terminal. 05.

Among them, the first signal terminal 04 is mainly used to control the opening and disconnection of the first adjustment circuit 02, and the second signal terminal 05 is mainly used to control the opening or disconnection of the second adjustment circuit 03, so as to control The pull-down capability of the level shifting circuit is adjusted.

Specifically, when the voltage of the power supply terminal VDDIO is greater than or equal to a predetermined voltage, thereby improving the pull-up capability of the level conversion circuit for the charges at the first node A and the second node B, the first signal terminal 04 is used to Provide a turn-on voltage to the first adjustment circuit 02 to turn on the first adjustment circuit 02 to improve the pull-down capability of the level conversion circuit for the charge at the first node A, so that the level conversion circuit can The pull-up capability and pull-down capability of the charge at the node A match each other to avoid the situation where the pull-up capability is much greater than the pull-down capability, so that the signal at the first node A can quickly flip to a low-level signal. And, the second signal terminal 05 is used to provide a turn-on voltage to the second adjustment circuit 03 to turn on the second adjustment circuit 03 to improve the pull-down capability of the level conversion circuit for the charge at the second node B. , so that the level conversion circuit's pull-up capability and pull-down capability for the charge at the second node B match each other, avoiding the situation where the pull-up capability is much greater than the pull-down capability, so that the signal at the second node B can quickly flip to low voltage. flat signal.

When the voltage of the power supply terminal VDDIO is less than a predetermined voltage so that the level conversion circuit's pull-up capability for the charges at the first node A and the second node B is reduced, the first signal terminal 04 is used to supply the first signal to the first node A. The adjustment circuit 02 provides a cut-off voltage to turn off the first adjustment circuit 02 to reduce the pull-down ability of the level conversion circuit for the charge at the first node A, so that the level conversion circuit can pull up the charge at the first node A. The pull-up capability and the pull-down capability match each other to avoid the situation where the pull-up capability is far less than the pull-down capability, so that the signal of the first node can quickly flip to a high-level signal. And, the second signal terminal 05 is used to provide a cut-off voltage to the second adjustment circuit 03 to turn off the second adjustment circuit 03 to reduce the pull-down capability of the level conversion circuit for the charge at the second node B. , so that the pull-up ability and pull-down ability of the level conversion circuit for the charge at the second node B match each other, avoiding the situation where the pull-up ability is far less than the pull-down ability, so that the signal of the second node B can quickly flip to a high level Signal.

It should be noted that in this embodiment, when the voltage of the power supply terminal VDDIO is greater than or equal to a predetermined voltage, the first adjustment circuit and the second adjustment circuit are not always on. Specifically, when the voltage of the power supply terminal VDDIO is greater than or equal to a predetermined voltage and the first pull-down transistor N1 is turned on, the first regulating circuit 02 is turned on. Otherwise, the first regulating circuit 02 is turned off. . And, when the voltage of the power supply terminal VDDIO is greater than or equal to a predetermined voltage and the second pull-down transistor N2 is turned on, the second adjustment circuit 03 is turned on; otherwise, the second adjustment circuit 03 is turned off.

And, further, in this embodiment, the value range of the predetermined voltage should be between the operating voltage range of the integrated circuit chip, and the integrated circuit chip is specifically a chip including the level conversion circuit of the present invention. . Also, it should be recognized that different integrated circuit process nodes correspond to different operating voltages, and diversified product needs require the same integrated circuit chip to have multiple operating voltages. Based on this, the predetermined voltage is a reasonable value between the minimum operating voltage and the maximum operating voltage of the integrated circuit chip. For example, when the integrated circuit chip uses a 55nm process, the predetermined voltage may be between 2 and 3V.

Therefore, for the level conversion circuit of the present invention, no matter when the voltage at the power supply terminal is large or small, it can be ensured that the output end of the level conversion circuit can realize rapid flipping between high and low levels. At this time, even if the voltage at the input end is If the signal flip speed of the input signal is faster, it can also ensure that the level conversion circuit outputs the correct signal to ensure that the subsequent circuit can operate normally.

Further, the first adjustment circuit 02 and the second adjustment circuit 03 are introduced in detail. As shown in Figure 2, in this embodiment, the first adjustment circuit 02 may include a first switching transistor N3 and a first adjustment transistor N4 connected in series with each other, and the second adjustment circuit 03 may include a second switching transistor N3 connected in series with each other. switching transistor N5 and second regulating transistor N6.

Wherein, the drain of the first switching transistor N3 serves as the first port of the first adjustment circuit 02 and is connected to the first node A, and the gate of the first switching transistor N3 serves as the first adjustment circuit. The third port of O2 is connected to the first signal terminal O4, the source of the first switching transistor N3 is connected to the drain of the first adjustment transistor N4, and the gate of the first adjustment transistor N4 is connected to the The gate of the first pull-down transistor N1 is connected, and the source of the first adjustment transistor N4 serves as the second port of the first adjustment circuit 02 and is connected to ground.

The drain of the second switching transistor N5 serves as the first port of the second adjustment circuit 03 and is connected to the second node B, and the gate of the second switching transistor N5 serves as the first port of the second adjustment circuit 03 The third port is connected to the second signal terminal 05, the source of the second switching transistor N5 is connected to the drain of the second adjustment transistor N6, and the gate of the second adjustment transistor N5 is connected to the second adjustment transistor N6. The gates of the two pull-down transistors N2 are connected, and the source of the second adjustment transistor N5 serves as the second port of the second adjustment circuit 03 and is connected to ground.

It should be noted that in this embodiment, when the first pull-down transistor N1 is turned on, the first adjustment transistor N3 should also be turned on; when the second pull-down transistor N2 is turned on, The second regulating transistor N5 should also be turned on. Based on this, in this embodiment, the first adjustment transistor N3 and the first pull-down transistor N1 can have the same polarity, and the second adjustment transistor N5 and the second pull-down transistor N2 can have the same polarity. Similarly, for example, the first adjustment transistor and the second adjustment transistor can both be NMOS transistors.

In addition, it should be noted that in this embodiment, the first signal terminal 04 and the second signal terminal 04 may both be connected to the power terminal VDDIO. Among them, the first signal terminal 04 and the second signal terminal 05 may also include a comparison circuit, and the comparison circuit stores a value of a predetermined voltage. The predetermined voltage may be input through an external connection or by an internal circuit. The set mode is stored in the comparison circuit, and the comparison circuit in the first signal terminal and the second signal terminal can be used to receive the voltage value of the power supply terminal VDDIO and compare the voltage value with a predetermined voltage. , to control the first switching transistor N3 or the second switching transistor N5 to turn on or off.

Specifically, in this embodiment, when the first signal terminal 04 and the second signal terminal 05 determine that the voltage of the power terminal VDDIO is greater than or equal to a predetermined voltage, the first signal terminal 04 is used to provide the signal to the A turn-on voltage is input to the gate of the first switching transistor N3 to turn on the first switching transistor N3; the second signal terminal 05 is used to input a turn-on voltage to the gate of the second switching transistor N5 to turn on the first switching transistor N3. The second switching transistor N5 is turned on.

And, when the first signal terminal 04 and the second signal terminal 05 determine that the voltage of the power supply terminal VDDIO is less than the predetermined voltage, the first signal terminal 04 is used to provide a signal to the gate of the first switching transistor N3. The second signal terminal O5 is used to output a cut-off voltage to the gate of the second switching transistor N5, so that the second switching transistor N5 disconnect.

In this embodiment, the first signal terminal 04 and the second signal terminal 05 may be the same signal terminal. Moreover, the first switching transistor N3 and the second switching transistor N5 have the same polarity. For example, both of them can be NMOS transistors.

In addition, in this embodiment, the first signal terminal 04 and the second signal terminal 05 can realize their functions through external direct connection VG signals or digital circuits, which are not specifically limited in this embodiment of the present invention.

And, based on the above content, the first pull-up transistor P1 and the second pull-up transistor P2 are now PMOS transistors, the first pull-down transistor N1, the first pull-down transistor N2, the first switching transistor N3, and the first adjustment transistor N4 Taking the second switching transistor N5 and the second adjustment transistor N6 as NMOS transistors as an example, the principle of the level conversion circuit in this embodiment is introduced:

Among them, the case where the power supply terminal voltage VDDIO is relatively large will be introduced first.

Specifically, when the voltage VDDIO of the power supply terminal is larger than or equal to a predetermined voltage, and the input voltage of the input terminal In is a low-level signal, the first pull-down transistor N1 and the first adjustment transistor The gate of N4 receives a low level signal, the first pull-down transistor N1 and the first adjustment transistor N4 are turned off, and the first adjustment circuit 02 is turned off. And the low-level signal is inverted into a high-level signal through the inverter 01 and input to the gates of the second pull-down transistor N2 and the second adjustment transistor N6. The second pull-down transistor N2 and the second adjustment transistor N6 are The second regulating transistor N6 is turned on.

And, because when the voltage of the power supply terminal VDDIO is greater than or equal to the predetermined voltage, the first signal terminal 04 will output a turn-on voltage to the gate of the second switching transistor N5, then the second switching transistor N5 conducts Pass. As a result, the second adjustment transistor N6, the second switching transistor N5, and the second pull-down transistor N2 are all turned on. At this time, the second adjustment circuit 03 and the second pull-down transistor N2 are both turned on at the same time, and both of them simultaneously pull down the charge at the second node B to a low level signal. The first pull-up transistor P1 is turned on, the charge at the first node A is pulled up to a high-level signal, the second pull-up transistor P2 is turned off, and the output terminal Out outputs a low-level signal.

And, when the voltage VDDIO of the power supply terminal is large and greater than or equal to a predetermined voltage, if the input voltage of the input terminal In is the high-level signal VDDC, the gates of the first pull-down transistor N1 and the first adjustment transistor N4 Upon receiving a high level signal, the first pull-down transistor N1 and the first adjustment transistor N4 are turned on. The gates of the second pull-down transistor N2 and the second adjustment transistor N6 receive a low level signal, and the second pull-down transistor N2 and the second adjustment transistor N6 are turned off, and the second adjustment circuit 03 is turned off. Moreover, when the voltage of the power supply terminal is greater than or equal to the predetermined voltage, the first signal terminal 04 will output a turn-on voltage to the gate of the first switching transistor N3, and the first switching transistor N3 will be turned on. Therefore, the first adjustment NMOS transistor N4, the first switching transistor N3 and the first pull-down transistor N1 are all turned on, that is, the first adjustment circuit 02 and the first pull-down transistor N1 are both turned on at the same time. , both simultaneously pull down the charge at the first node A to a low level signal. Then the second pull-up transistor P2 is turned on, pulling up the charge at the second node B to a high level signal and outputting it, and the first pull-up transistor P1 is turned off.

It should be noted that before the signal at the second node B flips to a low level signal, the second pull-up transistor P2 and the second pull-down transistor N2 will be turned on at the same time due to signal delay. At this time, when the voltage at the power supply terminal is larger, the charge at the power supply terminal VDDIO flows to the second node B at a faster speed, which makes the level conversion circuit have a stronger ability to pull up the charge at the second node B. Based on this, in this embodiment, when the voltage of the power supply terminal is relatively large, the second adjustment circuit 03 will be turned on at the same time along with the second pull-down transistor N2, so that the potential at the second node B is changed from the The two pull-down transistors N2 and the second adjustment circuit 03 both pull down at the same time and have strong pull-down capabilities, so that the pull-down capabilities and the pull-up capabilities match each other. Based on this, when the second pull-up transistor P2 and the second pull-down transistor N2 are turned on at the same time, it can avoid the situation that the pull-down capability of the charge at the second node B is much smaller than the pull-up capability, thereby making the second node B The charge at the output terminal Out is quickly pulled down to a low-level signal, and the output terminal Out (that is, the second node B) can quickly flip the low-level signal at the output terminal.

And, similarly, before the signal at the first node A flips to a low level signal, the first pull-up transistor P1 and the first pull-down transistor N1 will also be turned on at the same time due to signal delay. At this time, when the voltage at the power supply terminal is large, the level conversion circuit has a strong ability to pull up the charge at the first node A. In this embodiment, when the voltage at the power supply terminal is relatively large, the first adjustment circuit 02 is turned on simultaneously with the first pull-down transistor N1 to pull down the charge at the first node A, thereby improving level conversion. The circuit's pull-down ability for the charge coming out of the first node A makes the pull-down ability and the pull-up ability match each other. In this way, when the first pull-up transistor P1 and the first pull-down transistor N1 are turned on at the same time, it can be avoided that the pull-down capability of the charge at the first node A is much smaller than the pull-up capability, so that the charge at the first node A The charge is quickly pulled down to the low-level signal, thereby allowing the second pull-up transistor P2 to turn on quickly, so that the charge at the second node B can be quickly pulled up to the high-level signal VDDIO to output to achieve rapid flipping of the high-level signal at the output end.

It can be seen from the above that in the level conversion circuit of this embodiment, when the power supply terminal VDDIO is greater than or equal to a predetermined voltage, resulting in a strong pull-up capability of the level conversion circuit, the first adjustment circuit 02 and the third When the second adjustment circuit 03 is turned on, the level conversion circuit's pull-down ability for the charges at the first node A and the second node B can be flexibly adjusted, so that the level conversion circuit can flexibly adjust the pull-down ability of the level conversion circuit for the charges at the first node A and the second node B. The pull-down ability of the charge is also correspondingly strong, avoiding the phenomenon that the pull-down ability is much smaller than the pull-up ability, so that the charges at the first node A and the second node B can successfully flip to a low-level signal in a short time. , thus enabling the output terminal Out to quickly flip between high and low levels. In this way, even if the input signal flips quickly, the output terminal Out can still successfully flip the high and low level signals, thereby outputting the correct signal and ensuring subsequent circuit operation.

Further, the following will introduce the case where the power supply terminal voltage VDDIO is small.

Specifically, when the power terminal VDDIO is small and less than a predetermined voltage, or when the voltage of VDDIO is less than (normal operating voltage - normal operating voltage × preset percentage), the preset percentage can be between Between 8% and 12%, for example, it may be 10%, and the normal working voltage may be the normal working voltage of the integrated circuit chip. If the input signal at the input terminal In is a high-level signal, the second pull-down transistor N2 and the second adjustment transistor N6 are turned off, and the second adjustment circuit 03 is turned off. The first pull-down transistor N1 and the first adjustment transistor N4 are turned on. At the same time, when the voltage of the power supply terminal is less than the predetermined voltage, the first signal terminal 04 will output a cut-off voltage to the gate of the first switching transistor N3, and the first switching transistor N3 will be cut off, so that The first regulating circuit 02 is disconnected. At this time, only the first pull-down transistor N1 pulls down the charge at the first node A to a low level signal, then the second pull-up transistor P2 is turned on, and the charge at the second node B is pulled up. The signal is pulled to a high level and output from the output terminal Out, and the first pull-up transistor P2 is turned off.

And, when the power terminal VDDIO is small and less than a predetermined voltage, or when the voltage of VDDIO is less than (normal operating voltage - normal operating voltage × preset percentage). If the input signal at the signal terminal In is a low-level signal and the first pull-down transistor N1 and the first adjustment transistor N4 are turned off, the first adjustment circuit 02 is turned off, and the second pull-down transistor N2 and the first adjustment transistor N4 are turned off. The second regulating transistor N6 is turned on. At the same time, when the voltage of the power supply terminal is less than the predetermined voltage, the second signal terminal 05 will output a cut-off voltage to the gate of the second switching transistor N5, and the second switching transistor N5 will be cut off, so that The second regulating circuit 03 is disconnected. At this time, only the second pull-down transistor N2 pulls down the charge at the second node B to a low level signal, then the first pull-up transistor P1 is turned on, and the charge at the first node A is pulled up. to a high level signal, the second pull-up transistor P2 is turned off, and the second node B outputs a low level signal.

In this embodiment, before the signal at the second node B is pulled up to a high level signal, the second pull-up transistor P2 and the second pull-down transistor N2 will be turned on at the same time due to signal delay. At this time, if the voltage of the power supply terminal is small, the speed at which the charge at the power supply terminal VDDIO flows to the second node B will be slow, thereby causing the level conversion circuit to pull up the charge at the second node B. Less capable. At this time, in this embodiment, the second adjustment circuit 03 will be turned off, and then only the second pull-down transistor N2 in the level conversion circuit will pull down the charge at the second node B, and its pull-down capability will also be correspondingly Smaller, so that the pull-down ability and the pull-up ability match each other. In this way, when the second pull-up transistor P2 and the second pull-down transistor N2 are turned on at the same time, it can avoid the phenomenon that the charge pull-down capability at the second node B is much greater than the pull-up capability, thereby making the charge at the second node B The signal can quickly flip to the high-level signal VDDIO for output, realizing the rapid flip-flop of the high-level signal at the output end.

And, similarly, before the signal at the first node A is pulled up to a high level signal, the first pull-up transistor P1 and the first pull-down transistor N1 will be turned on at the same time due to signal delay. At this time, if the voltage VDDIO of the power supply terminal is small, the level conversion circuit will have a smaller ability to pull up the charge at the first node A. At this time, in this embodiment, the first adjustment circuit 02 will be disconnected, then only the first pull-down transistor N1 in the level conversion circuit will pull down the charge at the first node A, and its pull-down capability will also be correspondingly Smaller, so that the pull-down ability and the pull-up ability match each other. In this way, when the first pull-up transistor P1 and the first pull-down transistor N1 are turned on at the same time, it can avoid the phenomenon that the charge pull-down capability at the first node A is much greater than the charge pull-up capability, so that the charge pull-down capability of the first node A is The signal can quickly flip to the high-level signal VDDIO, so that the second pull-up transistor P2 can turn off faster, so that the signal at the second node can quickly flip to the low-level signal and be output, achieving a low level at the output end. Rapid flipping of signals.

It can be seen from the above that in the level conversion circuit of the present invention, when the power terminal VDDIO is small and the pull-up capability of the level conversion circuit is weak, the first adjustment circuit and the second adjustment circuit can be The circuit is disconnected to flexibly adjust the pull-down ability of the level conversion circuit, so that the pull-down ability of the level conversion circuit is correspondingly weaker, thus avoiding the situation where the pull-up ability of the level conversion circuit is far less than the pull-down ability. situation, so that the output terminal Out can quickly flip between high and low levels. In this way, even if the input signal flips quickly, the output terminal Out can successfully flip the high and low level signals, thereby outputting the correct signal and ensuring subsequent circuit operation.

In addition, it should be noted that in this embodiment, the first adjustment circuit may only include a first switching transistor, and the second adjustment circuit may only include a second switching transistor. In this case, the third adjustment circuit may include only a first switching transistor. A signal terminal and the second signal terminal are not the same signal terminal. And, when the power supply terminal voltage VDDIO is greater than or equal to a predetermined voltage, and when the first pull-down transistor N1 is turned on, the first signal terminal is used to input a turn-on voltage to the first switch transistor to turn on the first switch transistor. , otherwise the first signal terminal is used to output a cut-off voltage to the first switching transistor to turn off the first switching transistor. When the power supply terminal voltage VDDIO is greater than or equal to the predetermined voltage, and when the second pull-down transistor N2 is turned on, the second signal terminal is used to input a turn-on voltage to the second switch transistor to turn on the second switch transistor. Otherwise, The second signal terminal is used to output a cut-off voltage to the second switching transistor to turn off the second switching transistor. And, when the power supply terminal voltage VDDIO is less than a predetermined voltage, the first signal terminal is used to input a cut-off voltage to the first switching transistor, and the second signal terminal is used to input a cut-off voltage to the second switching transistor.

Optionally, in this embodiment, the first adjustment transistor and the second adjustment transistor have the same size, and the first switching transistor and the second switching transistor have the same size; the first The pull-down transistor and the second pull-down transistor have the same size; the first pull-up transistor and the second pull-up transistor have the same size; the substrate end of the first pull-up transistor and the first pull-up transistor have the same size. The source of the pull-up transistor is connected; the substrate end of the second pull-up transistor is connected to the source of the second pull-up transistor; the substrate end of the first pull-down transistor is connected to the source of the first pull-down transistor. and grounded; the substrate terminal of the second pull-down transistor is connected to the source of the second pull-down transistor and grounded.

To sum up, the level conversion circuit provided by the present invention includes at least one first adjustment circuit and at least one second adjustment circuit. And, in the present invention, when the voltage at the power supply terminal is large and the pull-up capability of the level conversion circuit is strong, the first adjustment circuit and the second adjustment circuit can be turned on to correspondingly improve the level conversion. The pull-down ability of the circuit avoids the phenomenon that the pull-up ability of the level conversion circuit is much greater than the pull-down ability, so that the signal at the output end of the level conversion circuit can quickly flip to a low-level signal. And, when the voltage at the power supply terminal is small and the pull-up capability of the level conversion circuit is weak, the first adjustment circuit and the second adjustment circuit can be disconnected to correspondingly reduce the pull-down capability of the level conversion circuit to avoid The phenomenon occurs that the pull-up capability of the level conversion circuit is much smaller than the pull-down capability, so that the signal at the output end of the level conversion circuit can quickly flip to a high-level signal.

Therefore, for the level conversion circuit of the present invention, when the voltage at the power supply terminal changes greatly and the pull-up capability of the level conversion circuit is greatly reduced or increased, by controlling the first adjustment circuit and the second adjustment circuit When the circuit is turned on or off, the pull-down capability of the level conversion circuit can be flexibly adjusted accordingly to avoid the situation where the pull-up capability of the level conversion circuit is far different from the pull-down capability and ensure that the output end can Quickly output high-level signals or low-level signals in a short period of time. Even if the signal flip speed of the input signal is relatively fast, it can still be ensured that the output terminal can successfully flip between high and low levels, so that the level conversion circuit can adapt to the diversified needs of current chip products.

In addition, the structure of the level conversion circuit provided by the present invention is also relatively simple.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For relevant details, please refer to the description in the method section.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes or modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of the claims.

Claims (10)

1. A level shifter circuit, the circuit comprising: a first pull-up transistor, a second pull-up transistor, an inverter, at least one first pull-down transistor, at least one first regulation circuit, at least one second pull-down transistor, at least one second regulation circuit;

the grid electrode of the first pull-down transistor is connected with the input end, the source electrode is grounded, and the drain electrode is connected with the first node; the drain electrode of the first pull-up transistor is connected with the first node, the grid electrode of the first pull-up transistor is connected with the second node, and the source electrode of the first pull-up transistor is connected with the power supply end; the input end of the inverter is connected with the grid electrode of the first pull-down transistor, and the output end of the inverter is connected with the grid electrode of the second pull-down transistor; the source electrode of the second pull-down transistor is grounded, and the drain electrode of the second pull-down transistor is connected with the second node; the drain electrode of the second pull-up transistor is connected with the second node, the grid electrode of the second pull-up transistor is connected with the first node, and the source electrode of the second pull-up transistor is connected with the power supply end; the second node is connected with the output end; the first regulating circuit is provided with a first port, a second port and a third port, wherein the first port of the first regulating circuit is connected with a first node, the second port is grounded, and the third port is connected with a first signal end; the second regulating circuit is provided with a first port, a second port and a third port, the first port of the second regulating circuit is connected with the second node, the second port is grounded, and the third port is connected with the second signal end;

When the voltage of the power supply end is larger than or equal to a preset voltage and the input voltage of the input end is a high-level signal, the second regulating circuit is disconnected, and the first signal end is used for providing an opening voltage for the first regulating circuit so as to enable the first regulating circuit to be conducted, so that the output signal of the first node can be turned to a low-level signal; when the voltage of the power supply end is larger than or equal to a preset voltage and the input voltage of the input end is a low-level signal, the first regulating circuit is disconnected, and the second signal end is used for providing an opening voltage for the second regulating circuit so as to enable the second regulating circuit to be conducted, so that the output signal of the second node can be turned to the low-level signal;

when the voltage of the power supply end is smaller than a preset voltage, the first signal end is used for providing cut-off voltage for the first regulating circuit so that the first regulating circuit is disconnected, and the output signal of the first node can be turned to a high-level signal; the second signal terminal is used for providing cut-off voltage for the second regulating circuit so as to disconnect the second regulating circuit, and the output signal of the second node can be inverted to a high-level signal.

2. The level shifter circuit of claim 1, wherein the first regulator circuit includes a first switching transistor and a first regulator transistor in series with each other, and the second regulator circuit includes a second switching transistor and a second regulator transistor in series with each other;

the drain electrode of the first switch transistor is used as a first port of the first regulating circuit to be connected with the first node, the grid electrode of the first switch transistor is used as a third port of the first regulating circuit to be connected with the first signal end, the source electrode of the first switch transistor is connected with the drain electrode of the first regulating transistor, the grid electrode of the first regulating transistor is connected with the grid electrode of the first pull-down transistor, and the source electrode of the first regulating transistor is used as a second port of the first regulating circuit to be grounded;

the drain electrode of the second switch transistor is used as a first port of the second regulating circuit to be connected with the second node, the grid electrode of the second switch transistor is used as a third port of the second regulating circuit to be connected with the second signal end, the source electrode of the second switch transistor is connected with the drain electrode of the second regulating transistor, the grid electrode of the second regulating transistor is connected with the grid electrode of the second pull-down transistor, and the source electrode of the second regulating transistor is used as a second port of the second regulating circuit to be grounded;

When the voltage of the power supply end is larger than or equal to the preset voltage, the first signal end is used for inputting an opening voltage to the grid electrode of the first switching transistor so as to enable the first switching transistor to be opened; the second signal end is used for inputting an opening voltage to the grid electrode of the second switching transistor so as to enable the second switching transistor to be opened;

when the voltage of the power supply terminal is smaller than the preset voltage, the first signal terminal is used for outputting an off voltage to the grid electrode of the first switching transistor so as to enable the first switching transistor to be disconnected; the second signal terminal is used for outputting a cut-off voltage to the grid electrode of the second switching transistor so as to disconnect the second switching transistor.

3. The level shifting circuit of claim 2, wherein the first pull-down transistor is of the same polarity as the second pull-down transistor, the first pull-up transistor is of the same polarity as the second pull-up transistor, and the first pull-down transistor and the first pull-up transistor are of opposite polarity.

4. The level shifter circuit of claim 3, wherein the first adjustment transistor and the first pull-down transistor are of the same polarity and the second adjustment transistor and the second pull-down transistor are of the same polarity.

5. The level shifter circuit of claim 4, wherein the first pull-down transistor and the second pull-down transistor are NMOS transistors, wherein the first pull-up transistor and the second pull-up transistor are PMOS transistors, and wherein the first adjustment transistor and the second adjustment transistor are NMOS transistors.

6. The level shifter circuit of claim 2, wherein the first signal terminal and the second signal terminal are the same signal terminal.

7. The level shifter circuit of claim 2, wherein the first switching transistor and the second switching transistor are of the same polarity.

8. The level shifter circuit of claim 7, wherein the first switching transistor and the second switching transistor are NMOS transistors.

9. The level shifter circuit of claim 2, wherein the first signal terminal and the second signal terminal each include a comparison circuit, and wherein the first signal terminal and the second signal terminal are each connected to the power terminal for receiving a voltage value of the power terminal and comparing the voltage value with a predetermined voltage.

10. The level shifter circuit of claim 1, wherein the first pull-down transistor and the second pull-down transistor are the same size; the first pull-up transistor and the second pull-up transistor are the same size.