CN101964335A - Package and method of manufacturing the same - Google Patents
Package and method of manufacturing the same Download PDFInfo
- Publication number
- CN101964335A CN101964335A CN2009101651761A CN200910165176A CN101964335A CN 101964335 A CN101964335 A CN 101964335A CN 2009101651761 A CN2009101651761 A CN 2009101651761A CN 200910165176 A CN200910165176 A CN 200910165176A CN 101964335 A CN101964335 A CN 101964335A
- Authority
- CN
- China
- Prior art keywords
- lead frame
- notched
- connecting portion
- notch
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000565 sealant Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000004806 packaging method and process Methods 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 4
- 210000002683 foot Anatomy 0.000 claims 24
- 239000003963 antioxidant agent Substances 0.000 claims 1
- 230000003078 antioxidant effect Effects 0.000 claims 1
- 235000006708 antioxidants Nutrition 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 36
- 238000005538 encapsulation Methods 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 22
- 238000010586 diagram Methods 0.000 description 12
- 239000008393 encapsulating agent Substances 0.000 description 5
- 230000003064 anti-oxidating effect Effects 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
技术领域technical field
本发明涉及一种封装件及其制造方法,且特别是涉及一种具有凹口的封装件及其制造方法。The present invention relates to a package and its manufacturing method, and in particular to a package with a notch and its manufacturing method.
背景技术Background technique
随着电子产业的蓬勃发展,半导体封装技术不断地进步。一般而言,半导体封装技术是利用导线架承载芯片,并以封胶密封导线架及基板,以避免芯片受潮或因碰撞而损坏。其中,芯片更通过导线架的接垫与外界电性连接,以便于与印刷电路板电性连接。With the vigorous development of the electronics industry, semiconductor packaging technology is constantly improving. Generally speaking, semiconductor packaging technology utilizes a lead frame to carry a chip, and seals the lead frame and the substrate with an encapsulant to prevent the chip from being damaged by moisture or impact. Wherein, the chip is further electrically connected to the outside through the pads of the lead frame, so as to be electrically connected to the printed circuit board.
然而,在电子产品追求“轻、薄、短、小”的潮流下,业界不断地致力于缩小封装结构的体积以符合潮流。However, under the trend of pursuing "light, thin, short, and small" in electronic products, the industry is constantly working on reducing the volume of the packaging structure to meet the trend.
发明内容Contents of the invention
本发明有关于一种封装件及其制造方法,其利用导线架的设计使得封装件更符合“轻、薄、短、小”的目标。The invention relates to a package and its manufacturing method, which uses the design of the lead frame to make the package more in line with the goal of "light, thin, short and small".
根据本发明的一方面,提出一种封装件。封装件包括导线架(LeadFrame)、芯片、数个导电凸块及封胶。导线架具有凹口。导线架包括数个第一凹口侧导线脚、数个第一凹口侧焊垫、数个第二凹口侧导线脚及数个第二凹口侧焊垫。第一凹口侧导线脚延伸至凹口的一侧,第一凹口侧焊垫对应地设置于第一凹口侧导线脚上。第二凹口侧导线脚延伸至凹口的另一侧,第二凹口侧焊垫对应地设置于第二凹口侧导线脚上。芯片设置于导线架,芯片具有数个接垫。导电凸块电性连接接垫与第一凹口侧焊垫及第二凹口侧焊垫。封胶包覆芯片、导电凸块及导线架,并裸露导线架的下表面。其中,凹口裸露出部分的封胶。According to an aspect of the present invention, a package is proposed. The package includes a lead frame (LeadFrame), a chip, several conductive bumps and sealant. The lead frame has notches. The lead frame includes several first notch-side lead pins, several first notch-side welding pads, several second notch-side lead pins and several second notch-side welding pads. The first notch-side wire feet extend to one side of the notch, and the first notch-side welding pads are correspondingly arranged on the first notch-side wire feet. The second notch-side lead pins extend to the other side of the notch, and the second notch-side welding pads are correspondingly arranged on the second notch-side lead pins. The chip is arranged on the lead frame, and the chip has several pads. The conductive bump is electrically connected to the pad and the first notch-side welding pad and the second notch-side welding pad. The sealing glue covers the chip, the conductive bump and the lead frame, and exposes the lower surface of the lead frame. Wherein, the notch exposes part of the sealant.
根据本发明的另一方面,提出一种封装件的制造方法。制造方法包括以下步骤。提供导线架,导线架具有第一连接部。导线架包括数个第一凹口侧导线脚、数个第一凹口侧焊垫、数个第二凹口侧导线脚及数个第二凹口侧焊垫。第一凹口侧导线脚延伸至第一连接部的一侧,第一凹口侧焊垫对应地设置于第一凹口侧导线脚上。第二凹口侧导线脚延伸至第一连接部的另一侧,第二凹口侧焊垫对应地设置于第二凹口侧导线脚上。其中每个第一凹口侧导线脚及每个第二凹口侧导线脚的上表面与第一连接部的上表面相距距离;提供芯片,芯片具有数个接垫;设置数个导电凸块于接垫上;以导电凸块电性连接接垫与第一凹口侧焊垫及第二凹口侧焊垫;以封胶包覆芯片、导电凸块及导线架,并裸露导线架的下表面;沿着第一连接部的延伸方向切割导线架,以去除第一连接部,使第一凹口侧导线脚与第二凹口侧导线脚电性分离,并形成凹口,凹口裸露出部分的该封胶。According to another aspect of the present invention, a method for manufacturing a package is provided. The manufacturing method includes the following steps. A lead frame is provided, the lead frame has a first connection portion. The lead frame includes several first notch-side lead pins, several first notch-side welding pads, several second notch-side lead pins and several second notch-side welding pads. The first notch-side lead pins extend to one side of the first connection portion, and the first notch-side welding pads are correspondingly arranged on the first notch-side lead pins. The second notch-side lead pins extend to the other side of the first connection portion, and the second notch-side welding pads are correspondingly arranged on the second notch-side lead pins. Wherein the upper surface of each first notch-side wire foot and each second notch-side wire foot is at a distance from the upper surface of the first connection part; a chip is provided, and the chip has several pads; several conductive bumps are provided On the pad; electrically connect the pad with the first notch side pad and the second notch side pad with the conductive bump; cover the chip, the conductive bump and the lead frame with the sealant, and expose the bottom of the lead frame Surface: cut the lead frame along the extension direction of the first connection part to remove the first connection part, electrically separate the first notch side lead pin from the second notch side lead leg, and form a notch, the notch is exposed Out of the part of the sealant.
为让本发明的上述内容能更明显易懂,下文特举优选实施例,并配合附图,作详细说明如下:In order to make the above content of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:
附图说明Description of drawings
图1绘示依照本发明优选实施例的封装件的制造方法的流程图。FIG. 1 is a flowchart of a manufacturing method of a package according to a preferred embodiment of the present invention.
图2绘示本实施例的封装件的导线架的俯视图。FIG. 2 is a top view of the lead frame of the package of the present embodiment.
图3绘示图2的导线架的前视图。FIG. 3 is a front view of the lead frame of FIG. 2 .
图4绘示本实施例的芯片的示意图。FIG. 4 is a schematic diagram of the chip of this embodiment.
图5绘示本实施例设置有导电凸块的芯片的示意图。FIG. 5 is a schematic diagram of a chip provided with conductive bumps in this embodiment.
图6绘示本实施例设置有芯片的导线架的示意图。FIG. 6 is a schematic diagram of a leadframe provided with chips in this embodiment.
图7其绘示本实施例的导线架的另一种实施方式的示意图。FIG. 7 is a schematic diagram illustrating another implementation manner of the lead frame of this embodiment.
图8绘示图7中局部A的放大立体图。FIG. 8 is an enlarged perspective view of part A in FIG. 7 .
图9绘示图7的导线架的俯视图。FIG. 9 is a top view of the lead frame of FIG. 7 .
图10绘示以封胶包覆图6的导线架、芯片及导电凸块的示意图。FIG. 10 is a schematic diagram of encapsulating the lead frame, chip and conductive bump in FIG. 6 with encapsulant.
图11绘示依照本发明优选实施例的封装件的示意图。FIG. 11 is a schematic diagram of a package according to a preferred embodiment of the present invention.
附图标记说明Explanation of reference signs
200、256:导线架200, 256: lead frame
202:第一连接部202: The first connecting part
204:第二连接部204: Second connection part
206:第三连接部206: The third connecting part
212:第一凹口侧导线脚212: First notch side wire foot
214、246:第一凹口侧焊垫214, 246: first notch side pads
216:第二凹口侧导线脚216: Second notch side guide pin
218、248:第二凹口侧焊垫218, 248: Second notch side solder pads
220:第一边缘侧导线脚220: first edge side wire foot
222、250:第一边缘侧焊垫222, 250: first edge side pads
224:第二边缘侧导线脚224: second edge side conductor foot
226、252:第二边缘侧焊垫226, 252: second edge side pads
228:芯片228: chip
230:接垫230: Pad
232:导电凸块232: Conductive bump
234:封胶234: Sealant
236:导线架的下表面236: Lower surface of lead frame
238:凹口238: Notch
240:导线架的上表面240: Top surface of lead frame
242:中间位置242: middle position
244:凹陷空间244: Recessed Space
248:抗氧化金属层248: anti-oxidation metal layer
260:侧表面260: side surface
262:封装件262: package
264:第一凹口侧导线脚的上表面264: Upper surface of the lead pin on the first notch side
266:第二凹口侧导线脚的上表面266: Upper surface of the lead pin on the second notch side
268:第一连接部的上表面268: the upper surface of the first connecting part
270:封胶的一部分270: Part of the sealant
272:第一侧面272: First Side
274:第二侧面274: Second Side
S102-S114:步骤S102-S114: Steps
具体实施方式Detailed ways
请参照图1,其绘示依照本发明优选实施例的封装件的制造方法流程图。制造方法包括以下步骤。Please refer to FIG. 1 , which shows a flowchart of a manufacturing method of a package according to a preferred embodiment of the present invention. The manufacturing method includes the following steps.
首先,请同时参照图2,其绘示本实施例的封装件的导线架的俯视图。在步骤S102中,提供导线架200。导线架200具有第一连接部202及相对应的第二连接部204及第三连接部206。第一连接部202实质上平行于第二连接部204及第三连接部206。且第一连接部202实质上位于第二连接部204与第三连接部206的中间位置242。First, please refer to FIG. 2 , which shows a top view of the lead frame of the package of this embodiment. In step S102, a
导线架200包括数个第一凹口侧导线脚212、数个第一凹口侧焊垫214、数个第二凹口侧导线脚216及数个第二凹口侧焊垫218。第一凹口侧导线脚212延伸至第一连接部202,第一凹口侧焊垫214对应地设置于第一凹口侧导线脚212上。第二凹口侧导线脚216延伸至第一连接部202,第二凹口侧焊垫218对应地设置于第二凹口侧导线脚216上。其中,第一凹口侧导线脚212及第二凹口侧导线脚216分别位于第一连接部202中相对应的两侧。The
此外,导线架200还包括数个第一边缘侧导线脚220、数个第一边缘侧焊垫222、数个第二边缘侧导线脚224及数个第二边缘侧焊垫226。第一边缘侧导线脚220延伸至第二连接部204。第一边缘侧焊垫222对应地设置于第一边缘侧导线脚220上。第二边缘侧导线脚224延伸至第三连接部206。第二边缘侧焊垫226对应地设置于第二边缘侧导线脚224上。In addition, the
第一凹口侧导线脚212的上表面264、第二凹口侧导线脚216的上表面266与第一连接部202的上表面268相距一距离,使第一凹口侧导线脚212、第二凹口侧导线脚216及第一连接部202形成凹陷外型,而第一连接部202的厚度相对较薄。The
此外,如图2所示,第一凹口侧焊垫214与第一边缘侧焊垫222为交错排列,且第二凹口侧焊垫218与第二边缘侧焊垫226为交错排列。通过该些焊垫的交错排列,充分运用了该些焊垫之间的空间,增加了导线架200可容纳的焊垫数目。优选但非限定地,每一第一凹口侧焊垫214及每一第二凹口侧焊垫218分别由第二连接部204及第三连接部206向内延伸第一距离D1。每一第一边缘侧焊垫222及每一第二边缘侧焊垫226分别由第二连接部204及第三连接部206向内延伸第二距离D2,其中,第一距离D1大于第二距离D2。亦即,将第一凹口侧焊垫214、第二凹口侧焊垫218、第一边缘侧焊垫222及第二边缘侧焊垫226规则地排列,可使导线架200可容纳的焊垫数目增加得更多。In addition, as shown in FIG. 2 , the first notch-
此外,本实施例的导线架200为预电镀导线架(Pre-Plating Lead Frame,PPF)。如图3所示,其绘示图2的导线架的前视图,此种导线架已预先电镀了抗氧化金属层248,例如是镍钯金(Ni-Pd-Au)合金。In addition, the
接着,请同时参照图4,其绘示本实施例的芯片的示意图。在步骤S104中,提供芯片228,芯片228具有数个接垫230。Next, please refer to FIG. 4 , which shows a schematic diagram of the chip of this embodiment. In step S104 , a
再来,请同时参照图5,其绘示本实施例设置有导电凸块的芯片的示意图。在步骤S106中,设置数个导电凸块232于接垫230上。Next, please refer to FIG. 5 , which shows a schematic diagram of a chip provided with conductive bumps in this embodiment. In step S106 , a plurality of
再来,请同时参照图6,其绘示本实施例设置有芯片的导线架的示意图。在步骤S108中,以导电凸块232电性连接接垫230与第一凹口侧焊垫214、第二凹口侧焊垫218、第一边缘侧焊垫222及第二边缘侧焊垫226。Next, please refer to FIG. 6 , which shows a schematic diagram of a leadframe provided with chips in this embodiment. In step S108, electrically connect the
虽然第一凹口侧焊垫214、第二凹口侧焊垫218、第一边缘侧焊垫222及第二边缘侧焊垫226以图6的形式形成于导线架200上。然于其它实施方式中,第一凹口侧焊垫214、第二凹口侧焊垫218、第一边缘侧焊垫222及第二边缘侧焊垫226也可以其它形式形成于导线架200上。例如,请参照图7,其绘示第一实施例的导线架的另一种实施方式的示意图。导线架256的第一凹口侧焊垫246、第二凹口侧焊垫248、第一边缘侧焊垫250及第二边缘侧焊垫252的外型为柱体且突出于导线架200的上表面240。Although the first notch-
请参照图8,其绘示图7中局部A的放大立体图。第一边缘侧焊垫250以柱体的形式设置于导线架200上,柱体的周围具有凹陷空间244,此凹陷空间244露出柱体的侧表面260。当导电凸块232(导电凸块232绘示于图6)设置在第一边缘侧焊垫250上后,在后续的回焊工艺(reflow)中,熔化的导电凸块232与第一边缘侧焊垫250接触的面积会增加。接触面积增加,表面张力亦增加,可增强导电凸块232与第一边缘侧焊垫250的结合性。如此,导电凸块232较不会错位,因而提升了导电凸块232与第一边缘侧焊垫250的对位性。相似地,当呈柱体的第一凹口侧焊垫246、第二凹口侧焊垫248及第二边缘侧焊垫252与导电凸块232结合时,也会产生第一边缘侧焊垫250与导电凸块232结合性增强的效果。Please refer to FIG. 8 , which shows an enlarged perspective view of part A in FIG. 7 . The
此外,请参照图9,其绘示图7的导线架的俯视图。第一凹口侧焊垫246、第二凹口侧焊垫248、第一边缘侧焊垫250及第二边缘侧焊垫252的截面形状为圆形。虽然本实例的柱体的截面以圆形为例作说明,然在其它实施方式中,柱体的截面形状也可以是三角形、四角形或其它形状,其形状并不受图9所限制。In addition, please refer to FIG. 9 , which shows a top view of the lead frame in FIG. 7 . Cross-sectional shapes of the first notch-
然后,请同时参照图10,其绘示以封胶包覆图6的导线架、芯片及导电凸块的示意图。在步骤S110中,以封胶234包覆芯片228、导电凸块232及导线架200并裸露导线架200的下表面236。Then, please refer to FIG. 10 , which shows a schematic diagram of encapsulating the lead frame, chip and conductive bump in FIG. 6 with encapsulant. In step S110 , the
此外,虽然本实施例的导线架200为预电镀导线架。然而,图2的导线架200也可以不为预电镀导线架。举例来说,若导线架200不是预电镀导线架,则在步骤S110之后,形成抗氧化金属层(例如是锡(Sn)或锡-铅(Sn-Pb))合金于导线架200的底面。形成抗氧化金属层的方式例如是电镀。In addition, although the
然后,请同时参照图11,其绘示依照本发明优选实施例的封装件的示意图。在步骤S112中,沿着第一连接部202的延伸方向切割被封胶234包覆的导线架200,以去除第一连接部202,使第一凹口侧导线脚212与第二凹口侧导线脚216电性分离,并形成凹口238,凹口238裸露出封胶234的一部分270。Then, please also refer to FIG. 11 , which shows a schematic diagram of a package according to a preferred embodiment of the present invention. In step S112, the
由于第一连接部202的厚度相对较薄,所以非常轻易地就能切割出凹口238。其中,去除第一连接部202的动作可采用刀具或激光,以切削的方式完成。Since the thickness of the first connecting
由于第一连接部202实质上位于第二连接部204与第三连接部206的中间位置,所以凹口238的位置实质上位于相同位置。Since the first connecting
然后,在步骤S114中,沿着第二连接部204的延伸方向及第三连接部206的延伸方向切割被封胶234包覆的导线架200,以去除第二连接部204及第三连接部206,并使第一边缘侧导线脚220与第二边缘侧导线脚224电性分离第二连接部204及第三连接部206被切除后,裸露出封装件262中相对应的第一侧面272及第二侧面274。至此,完成了本发明优选实施例的封装件262,如图11所示。Then, in step S114, the
本发明上述实施例所披露的封装件及其制造方法,具有多项优点,以下仅列举部分优点说明如下:The package and its manufacturing method disclosed in the above embodiments of the present invention have many advantages, and only some of the advantages are listed below:
(1)第一凹口侧焊垫、第一边缘侧焊垫、第二凹口侧焊垫及第二边缘侧焊垫呈阵列式排列,增加了导线架可容纳的焊垫数量。(1) The first notch-side welding pad, the first edge-side welding pad, the second notch-side welding pad and the second edge-side welding pad are arranged in an array, which increases the number of welding pads that the lead frame can accommodate.
(2)第一凹口侧焊垫与第一边缘侧焊垫为交错排列且第二凹口侧焊垫与第二边缘侧焊垫亦交错排列。在充分利用了焊垫之间的空间下,更增加了导线架可容纳的焊垫数量。(2) The first notch-side welding pads and the first edge-side welding pads are arranged in a staggered manner, and the second notch-side welding pads and the second edge-side welding pads are also arranged in a staggered manner. Under the condition that the space between the welding pads is fully utilized, the number of welding pads that the lead frame can accommodate is increased.
(3)第一凹口侧焊垫、第二凹口侧焊垫、第一边缘侧焊垫及第二边缘侧焊垫以柱体形式形成于导线架上。如此,在回焊工艺中,增加了导电凸块与焊垫的接触面积。接触面积增加,表面张力亦增加。使得导电凸块在回焊工艺中较不会错位。(3) The first notch-side solder pad, the second notch-side solder pad, the first edge-side solder pad and the second edge-side solder pad are formed on the lead frame in the form of pillars. In this way, in the reflow process, the contact area between the conductive bump and the pad is increased. As the contact area increases, the surface tension also increases. Therefore, the conductive bumps are less likely to be dislocated during the reflow process.
综上所述,虽然本发明已以优选实施例披露如上,然其并非用以限定本发明。本发明所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视所附的权利要求所界定为准。In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910165176 CN101964335B (en) | 2009-07-23 | 2009-07-23 | Package and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910165176 CN101964335B (en) | 2009-07-23 | 2009-07-23 | Package and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101964335A true CN101964335A (en) | 2011-02-02 |
CN101964335B CN101964335B (en) | 2013-04-24 |
Family
ID=43517163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 200910165176 Active CN101964335B (en) | 2009-07-23 | 2009-07-23 | Package and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101964335B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104167368A (en) * | 2013-05-17 | 2014-11-26 | 新科金朋有限公司 | Integrated circuit packaging system with plated leads and method of manufacture thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6597059B1 (en) * | 2001-04-04 | 2003-07-22 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package |
US6815833B2 (en) * | 2002-11-13 | 2004-11-09 | Advanced Semiconductor Engineering, Inc. | Flip chip package |
CN1639864A (en) * | 2002-03-06 | 2005-07-13 | 飞思卡尔半导体公司 | Multi-row leadframe |
US20060022316A1 (en) * | 2004-06-24 | 2006-02-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with flip chip on leadless leadframe |
CN101055860A (en) * | 2006-04-11 | 2007-10-17 | 日月光半导体制造股份有限公司 | Lead frame package structure with high density pin arrangement |
CN101151727A (en) * | 2005-02-03 | 2008-03-26 | 德州仪器公司 | Integrated circuit chip package and method |
CN101308830A (en) * | 2007-05-18 | 2008-11-19 | 飞思卡尔半导体(中国)有限公司 | Lead frame for semiconductor encapsulation |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101091896B1 (en) * | 2004-09-04 | 2011-12-08 | 삼성테크윈 주식회사 | Flip chip semiconductor package and manufacturing methode thereof |
US7495325B2 (en) * | 2005-05-05 | 2009-02-24 | Stats Chippac, Ltd. | Optical die-down quad flat non-leaded package |
CN100395888C (en) * | 2005-09-30 | 2008-06-18 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
CN100524722C (en) * | 2006-12-28 | 2009-08-05 | 日月光半导体制造股份有限公司 | Packaging structure of lead frame without external pin |
US20080241991A1 (en) * | 2007-03-26 | 2008-10-02 | National Semiconductor Corporation | Gang flipping for flip-chip packaging |
-
2009
- 2009-07-23 CN CN 200910165176 patent/CN101964335B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6597059B1 (en) * | 2001-04-04 | 2003-07-22 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package |
CN1639864A (en) * | 2002-03-06 | 2005-07-13 | 飞思卡尔半导体公司 | Multi-row leadframe |
US6815833B2 (en) * | 2002-11-13 | 2004-11-09 | Advanced Semiconductor Engineering, Inc. | Flip chip package |
US20060022316A1 (en) * | 2004-06-24 | 2006-02-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with flip chip on leadless leadframe |
CN101151727A (en) * | 2005-02-03 | 2008-03-26 | 德州仪器公司 | Integrated circuit chip package and method |
CN101055860A (en) * | 2006-04-11 | 2007-10-17 | 日月光半导体制造股份有限公司 | Lead frame package structure with high density pin arrangement |
CN101308830A (en) * | 2007-05-18 | 2008-11-19 | 飞思卡尔半导体(中国)有限公司 | Lead frame for semiconductor encapsulation |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104167368A (en) * | 2013-05-17 | 2014-11-26 | 新科金朋有限公司 | Integrated circuit packaging system with plated leads and method of manufacture thereof |
CN104167368B (en) * | 2013-05-17 | 2018-07-13 | 新科金朋有限公司 | The integrated circuit package system and its manufacturing method of lead with plating |
Also Published As
Publication number | Publication date |
---|---|
CN101964335B (en) | 2013-04-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7608930B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US9418940B2 (en) | Structures and methods for stack type semiconductor packaging | |
CN101540310B (en) | Semiconductor package and method of manufacturing the same | |
US8405212B2 (en) | Semiconductor package | |
JP5122835B2 (en) | Semiconductor device, lead frame, and manufacturing method of semiconductor device | |
US8133759B2 (en) | Leadframe | |
US8008784B2 (en) | Package including a lead frame, a chip and a sealant | |
WO2006109566A1 (en) | Semiconductor device | |
US20040238923A1 (en) | Surface-mount-enhanced lead frame and method for fabricating semiconductor package with the same | |
CN102569242B (en) | Semiconductor package integrating shielding film and manufacturing method thereof | |
CN101740539B (en) | Four-square plane non-guide pin package unit and its manufacturing method and its lead frame | |
US20090206459A1 (en) | Quad flat non-leaded package structure | |
US20020146863A1 (en) | Method of mounting an exposed-pad type of semiconductor device over a printed circuit board | |
JP4635471B2 (en) | Semiconductor device and manufacturing method thereof, mounting structure of semiconductor device, and lead frame | |
CN203118928U (en) | Packaging structure | |
US20080185698A1 (en) | Semiconductor package structure and carrier structure | |
KR20100050976A (en) | Semiconductor package and method for fabricating the same | |
CN103021879B (en) | Leadless semiconductor package, method for manufacturing the same, and lead frame strip | |
CN101964335A (en) | Package and method of manufacturing the same | |
CN101685809B (en) | Semiconductor package and its lead frame | |
US20140284803A1 (en) | Semiconductor package and fabrication method thereof | |
US11227820B2 (en) | Through hole side wettable flank | |
TWI429351B (en) | Memory card package having a small substrate | |
KR100772103B1 (en) | Laminated package and its manufacturing method | |
TWI761116B (en) | Semiconductor package structure and leadframe |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |