CN100395888C - Semiconductor package and fabrication method thereof - Google Patents

Abstract

A semiconductor package and its preparation method is to equip a chip and a lead frame with many pins, define at least a central area and a peripheral area in the active surface center of the chip, and plant the first conductive lug and the second conductive lug in the peripheral area corresponding to the pin in the central area, set the chip on the lead frame, then form a encapsulation colloid used for coating the chip, the first, the second conductive lug and the lead frame, make the pin and the second conductive lug bottom expose outside the encapsulation colloid, as the direct external electrical connection end point of the package; the semiconductor package of the present invention not only has a plurality of pins as electrical connection terminals, but also can directly use the second conductive bumps as additional electrical connection terminals such as input/output terminals, so as to increase the number of electrical connection terminals of the package.

Description

Semiconductor package and its manufacturing method

technical field

The invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package using flip-chip technology on a lead frame and its manufacturing method.

Background technique

The traditional semiconductor package with lead frame as the chip carrier is to set the non-active surface of the semiconductor chip on the die pad of the lead frame, and then connect the active surface of the semiconductor chip through multiple bonding wires. It is electrically connected to a plurality of pins (Lead) of the lead frame, and then the semiconductor chip, the bonding wire and part of the lead frame are covered by encapsulation glue. This kind of semiconductor package often weakens the transmission signal due to the bonding wire, and in the molding process of the encapsulant, the arc of the bonding wire is also easily shifted or toppled by the impact of the mold flow, and even causes adjacent bonding wires to touch each other. short circuit. Furthermore, the overall height of the semiconductor package is also limited by the arc height of the bonding wires and cannot be effectively reduced.

In this context, someone has developed a semiconductor package using flip-chip technology on a lead frame, which is to place the active surface of the semiconductor chip downward through a plurality of conductive bumps implanted on the active surface. The semiconductor chip is electrically connected and fixed to the corresponding pin of the lead frame. In this way, since the electrical connection does not need to be performed through the wire bonding, the problem of the electrical connection quality of the wire bonding technology can be solved, and the height of the semiconductor package can also be effectively reduced.

However, due to the application of flip-chip technology in the semiconductor package of the lead frame, the multiple pins of the lead frame are only arranged on the peripheral part, and no electrical connection terminals can be formed at the central part, so there is The problem of insufficient number of electrical connection terminals available for flip-chip electrical connection.

To solve this problem, US Pat. No. 6,815,833 proposes a semiconductor package in which electrical connection terminals are formed at the central portion of the lead frame. As shown in FIGS. 1A and 1B, the semiconductor package 5 includes: a lead frame 57 with a plurality of pins 54 and a chip base 55; a semiconductor chip 51 with an active surface 512, the semiconductor chip 51 is formed by A plurality of conductive bumps 52 formed on the active surface are arranged and electrically connected to the chip base 55 and pins 54 of the lead frame 57; 51 encapsulation colloid 56 . Wherein, the lower surfaces of the pins 54 and the die holder 55 are exposed to the lower surface of the encapsulant 56 . Therefore, in addition to using the plurality of pins 54 as signal input/output (I/O) electrical connection terminals of the semiconductor package 5 , the chip base 55 can also be used to provide additional power or ground terminals.

In addition, US Patent No. 6,597,059 also proposes a semiconductor package that can increase electrical connection terminals. 2A and 2B, the semiconductor package 6 includes a lead frame 67 with multiple pins 64 and two chip bases 65; a semiconductor chip 61 with an active surface 612, the semiconductor chip 61 is formed by multiple A conductive bump 62 formed on the active surface 612 is electrically connected to the corresponding pin 64 and the two chip holders 65; 61 encapsulation colloid 66. Wherein, the lower surfaces of the pins 64 and the die holder 65 expose the lower surface of the encapsulant 66 . Therefore, in addition to using the plurality of pins 64 as electrical connection terminals of the semiconductor package 6 , the chip base 65 can also be used as two additional electrical connection terminals, such as power and/or ground terminals.

However, in the above-mentioned prior art, although the chip base can be used as the electrical connection terminal of the semiconductor package except the pins, at most one or two electrical connection terminals are added. In addition, the electrical connection increased by the chip base Because it requires multiple conductive bumps to be set on it, it can only be used as a power supply or ground terminal, and cannot be an input/output terminal, that is, it cannot meet the needs of high-electricity, multi-functional devices with multiple contacts. demand for semiconductor chips. Therefore, how to increase the number of electrical connection terminals such as input/output terminals in the semiconductor package and improve the electrical function of the package has indeed become an urgent problem to be solved in related fields.

Contents of the invention

To overcome the above-mentioned problems in the prior art, the main purpose of the present invention is to provide a semiconductor package capable of increasing the number of input/output electrical connection terminals and its manufacturing method.

Another object of the present invention is to provide a semiconductor package that can simultaneously improve heat dissipation, increase electrical performance, and additionally increase electrical connection terminals and its manufacturing method.

To achieve the above and other objects, the semiconductor package of the present invention includes: a lead frame with a plurality of pins; a chip with an active surface, which is arranged on the lead frame with its active surface, and the active surface defines There is a central area and a peripheral area; the first conductive bump is placed on the peripheral area of the active surface of the chip, for the chip to be disposed and electrically connected to the pin of the lead frame; the second conductive bump, Placed in the central area of the active surface of the chip, as the external electrical connection terminal of the package; and encapsulant, used to cover the chip, the first and second conductive bumps and the lead frame, wherein the The lower surface of the pin and the lower surface of the second conductive bump expose the encapsulation compound. The lower surface of the encapsulant, the lower surface of the pin is flush with the lower surface of the second conductive bump. In addition, the present invention mainly exposes the second conductive bump part by grinding the encapsulant and the lower surface of the pin, so that the semiconductor package can use the exposed second conductive bump part to provide additional electrical connection endpoint.

In this way, not only the chip can be electrically connected to the outside through the first conductive bump and the pins of the lead frame, but also the second conductive bump can be used to provide the chip with an electrical connection directly to the outside, increasing the electrical conductivity of the semiconductor package. The number of electrical connection terminals, and the additional electrical connection terminals added by the second conductive bump implanted in the central area of the active surface of the chip can not only be used as grounding or power supply, but also can be directly used as signal input/ The output terminal achieves the purpose of increasing the number of input/output electrical connection terminals, and solves the problem that in the past, only the grounding and power supply electrical connection terminals could be added, but the input/output electrical connection terminals could not be increased.

In addition, in the semiconductor package of the present invention, the chip uses a redistribution layer, and the central area and the peripheral area of the chip redistribute the electrical contacts on the active surface of the chip, so that the electrical contacts of the chip can be redistributed. In a suitable position, the first conductive bump is planted on the peripheral area of the active surface of the chip, and the second conductive bump is planted on the central area of the active surface of the chip, so as to increase the package such as input/ The output is electrically connected to the terminal purpose.

Furthermore, in addition to having a plurality of pins, the lead frame in the semiconductor package of the present invention may also include a conductive sheet (chip holder) placed in the center portion surrounded by these pins, for partly implanted on the chip The second conductive bump in the central area can be installed and electrically connected to the conductive sheet as a ground or power terminal, and the remaining second conductive bumps not arranged on the conductive sheet can expose the encapsulant in subsequent operations as input/ output endpoint.

The present invention also provides the above method for manufacturing a semiconductor package, the steps of which include: preparing a lead frame and a chip, the lead frame has a plurality of pins, and the chip has an active surface, and on the active surface A central area is defined at the center of the source surface and a peripheral area is defined around the active surface; the first conductive bump is implanted on the peripheral area of the chip, and the second conductive bump is implanted on the chip On the central area; the first conductive bump planted on the chip is bonded to the upper surface of the corresponding pin of the lead frame; an encapsulation compound is formed for covering the chip, the first and second conductive bumps and the lead frame; and grinding the packaging colloid and the lower surface of the pin to expose the lower surface of the second conductive bump.

The manufacturing method of the semiconductor package of the present invention also includes forming a redistribution layer on the active surface of the chip for redistributing the electrical contacts of the chip in the central area and the peripheral area of the chip. Wherein if the original electrical contact of the chip is not arranged in the required position, the appropriate position can be redistributed, and the first conductive bump can be planted on the circumferential area corresponding to the position of the pin, and the The second conductive bump is implanted on the central area for subsequent grinding to expose the second conductive bump part, so as to increase the package such as the purpose of the input/output electrical connection terminal.

As can be seen from the above, the semiconductor package and its manufacturing method of the present invention make the semiconductor package not only have a plurality of pins as electrical connection terminals, but also use the second conductive bump directly as an additional input/output The electrical connection terminals achieve the purpose of increasing the number of electrical connection terminals of the package. At the same time, the semiconductor package and its manufacturing method of the present invention can also improve heat dissipation, increase electrical performance and additionally increase electrical connection terminals.

Description of drawings

1A is a schematic plan view of a semiconductor package with a lead frame disclosed in US Patent No. 6,815,833;

1B is a schematic cross-sectional view of a semiconductor package with a lead frame disclosed in US Patent No. 6,815,833;

2A is a schematic plan view of a semiconductor package with a lead frame disclosed in US Patent No. 6,597,059;

2B is a schematic cross-sectional view of a semiconductor package with a lead frame disclosed in US Patent No. 6,597,059;

3A is a schematic plan view of Embodiment 1 of the semiconductor package of the present invention;

3B is a schematic cross-sectional view of Embodiment 1 of the semiconductor package of the present invention;

4A to 4F are schematic diagrams of Embodiment 1 of the semiconductor package manufacturing method of the present invention;

5A is a schematic plan view of Embodiment 2 of the semiconductor package of the present invention; and

5B is a schematic cross-sectional view of Embodiment 2 of the semiconductor package of the present invention.

Detailed ways

The following embodiments are illustrated by taking the Flip-Chip Quad FlatNon-Leads (FC-QFN for short) semiconductor package and its manufacturing method as an example. In order to simplify the accompanying drawings, the features of the present invention and The structure is clearer and easier to understand. In the drawings, only the parts directly related to the present invention are shown, and the rest are omitted.

Example 1

Please refer to FIG. 3A and FIG. 3B , which are schematic plan and cross-sectional views of Embodiment 1 of the semiconductor package of the present invention. As shown in FIG. 3A and FIG. 3B, the semiconductor package 1 according to Embodiment 1 of the present invention includes: a lead frame 17 having a plurality of pins 14, wherein the pins 14 have an upper surface 141 and an opposite lower surface 142; A chip 11 disposed on the lead frame 17 has an active surface 112, and the active surface 112 defines a peripheral region 113 and a central region 114; a plurality of first conductive bumps 12 are arranged on the peripheral region On the area 113, and the first conductive bump 12 is corresponding to the position of the pin 14, for the chip to be arranged and electrically connected to the upper surface 141 of the pin 14; a plurality of second conductive bumps 13 are arranged on the pin 14. On the central area 114, wherein the size of the second conductive bump 13 is larger than the size of the first conductive bump 12; and an encapsulant 16 for covering the chip 11, the first conductive bump 12, the The second conductive bump 13 and the lead frame 17 , wherein, the bottom surface 142 of the pin 14 and the second conductive bump 13 partially expose the encapsulant 16 .

On the active surface 112 of the semiconductor chip 11, a redistribution layer (Redistribution Layer, RDL) (not shown) can be formed, so that the electrical contacts of the semiconductor chip 11 (such as input/ Output contacts, power contacts, ground contacts) are reconfigured to appropriate positions, the first conductive bump 12 is implanted on the peripheral area 113, and the second conductive bump 13 is implanted on the central area 114 superior.

In the semiconductor package 1, the first conductive bump 12 is mainly used to connect to the input/output contact of the chip 11, and the second conductive bump 13 is optionally used to connect to the power contact of the chip 11. , grounding contacts or input/output contacts, etc. In addition, the semiconductor package 1 also includes a solder layer 18 formed on the lower surface 142 of each pin 14, so that the semiconductor package 1 can be electrically connected to the second conductive bump 13 through the solder layer 18 on the pin. to an external device such as a printed circuit board.

In addition, in the semiconductor package 1 , a stepped structure 143 can be formed on the second surface of the pin 14 to increase the adhesion between the encapsulant 16 and the pin 14 .

The manufacturing method of the semiconductor package of the present invention will be described in detail below with reference to FIGS. 4A to 4F .

As shown in FIGS. 4A and 4B , a semiconductor chip 11 having an active surface 112 is prepared. Wherein, on the active surface 112, a plurality of electrical contacts 110, such as input/output contacts, power contacts, ground contacts, etc., have been formed by existing semiconductor processes. A central region 114 and a peripheral region 113 are defined on the active surface 112 . Wherein, the original electrical contacts on the active surface of the chip can be reconfigured by a redistribution layer to form the electrical contacts 110 on the peripheral area 113 and the central area 114 defined on the active surface 112 .

As shown in FIG. 4C, a plurality of first conductive bumps 12 are implanted in the peripheral area 113 of the active surface of the chip 11, such as input/output electrical contacts 110, and a plurality of second conductive bumps 13 Implanted in the central area 114 of the active surface of the chip 11 , such as power, ground or input/output electrical contacts 110 .

As shown in FIG. 4D, prepare a lead frame 17 such as being made of conductive metal such as copper, aluminum or alloys thereof, the lead frame 17 at least includes a plurality of pins 14 arranged around the lead frame 17 for the active surface 112 The chip 11 implanted with the first and second conductive bumps 12, 13 is disposed thereon. It is to respectively arrange and electrically connect the first conductive bumps 12 implanted on the peripheral area 113 of the chip 11 to the pins 14 .

As shown in FIG. 4E , an encapsulant 16 is formed to cover the semiconductor chip 11 , the plurality of first conductive bumps 12 , the plurality of second conductive bumps 13 and the lead frame 17 .

As shown in FIG. 4F , the lower surface of the encapsulant 16 near the lead frame 17 is ground by means of a grinding wheel G or the like. At this time, the pins 14 and the encapsulant 16 are ground at the same time until they are ground to an appropriate depth, so that the second conductive bump 13 has an appropriate area exposed from the encapsulant 16 . Thereby, the lower surfaces of the plurality of second conductive bumps 13, the lower surfaces of the plurality of pins 14 are substantially flush with the lower surface of the encapsulant 16, thereby completing the semiconductor package as shown in FIG. 3A and FIG. 3B piece 1.

The steps of the above semiconductor package manufacturing method may also include: after the grinding process is completed, plating a solder layer 18 (as shown in FIG. 3B ) on the lower surface of the plurality of pins 14, so that the semiconductor package can be passed through The pin solder layer 18 and the second conductive bump 13 exposing the encapsulant are electrically connected to an external device such as a printed circuit board.

In addition, the size of the second conductive bump 13 is preferably larger than the size of the first conductive bump 12, so that when the part of the second conductive bump 13 that exposes the encapsulant is formed by grinding, there is no need to The lower portion of pin 14 is excessively ground.

Therefore, through the semiconductor package and its manufacturing method of the present invention, it is possible to provide a flip-chip semiconductor package with a lead frame, in addition to having a plurality of pins for electrically connecting the terminals, the second conductive bump can also be used As an additional input/output electrical connection terminal, the purpose of increasing the input/output terminal of the package is achieved. Of course, the second conductive bump can also be selected as a power supply or ground terminal in addition to the package input/output terminal. , and even heat dissipation terminals, which can improve the heat dissipation of the package, increase the electrical performance, and add additional electrical connection terminals.

Example 2

Please refer to FIG. 5A and FIG. 5B , which are cross-sectional and plan views of Embodiment 2 of the semiconductor package of the present invention. The semiconductor package of Embodiment 2 of the present invention is substantially the same as the semiconductor package of Embodiment 1. The main difference is that the lead frame in the semiconductor package includes at least one pin formed in the surrounding part in addition to a plurality of pins formed in the surrounding part. On the conductive sheet (chip holder) at the central portion, the second conductive bumps partially formed on the active surface of the chip can be disposed and electrically connected to the conductive sheet.

As shown in the figure, the semiconductor package 2 according to Embodiment 2 of the present invention includes: a lead frame 27 having a plurality of pins 24 disposed on the periphery of the semiconductor package 2, and a conductive sheet ( Chip holder) 29, wherein, the plurality of pins 24 have opposite upper surfaces 241 and lower surfaces 242, and the conductive sheet 29 also has opposite upper surfaces 291 and lower surfaces 292; the chip arranged on the lead frame 27 21, having at least an active surface 212 defining a peripheral area 213 and a central area 214; a plurality of first conductive bumps 22 arranged on the peripheral area 213, the positions of the plurality of first conductive bumps 22 are respectively Corresponding to the positions of the plurality of pins 24, the chip 21 is provided and electrically connected to the upper surface 241 of the pins 24; the plurality of second conductive bumps 23 arranged on the central area 214, some of which Two conductive bumps 23' are provided and electrically connected to the upper surface 291 of the conductive sheet 29; and the encapsulant 26 is used to cover the chip 21, the first and second conductive bumps 22, 23 (23') And the lead frame 17, wherein, the lower surface of the plurality of pins 24 of the lead frame 27, the lower surface of the conductive sheet 29, and the lower surface of the second conductive bump 23 that is not partly arranged on the conductive sheet are external The encapsulant 26 is exposed.

Since some of the second conductive bumps 23' are commonly connected to the conductive sheet 29, that is, the second conductive bumps 23' form a single electrical connection terminal, so it is better to connect the second conductive bumps 23' To the power or ground contact of the chip 21 , or the heat dissipation contact, and connect the other second conductive bumps 23 not disposed on the conductive sheet 29 to the input/output contacts of the chip 21 . At the same time, it meets the needs of multi-function, high electrical performance and even heat dissipation of the chip.

The lead frame 27 of the semiconductor package 2 may also include a solder layer 28 formed on the lower surface of each pin 24 and the lower surface of the conductive sheet 29, so that the semiconductor package 2 can pass through the solder layer 28 and be exposed to the outside. Part of the second conductive bump 23 of the encapsulant is directly electrically connected to an external device such as a printed circuit board.

The present invention is not limited to the above-mentioned embodiments. In the semiconductor package manufacturing method of the present invention, a lead frame module having a plurality of lead frame units can also be formed to form a plurality of semiconductor packages at the same time. The semiconductor package is separated.

Claims (20)

1. A semiconductor package, characterized in that the semiconductor package comprises: Leadframes with multiple pins; a chip having an active surface, with its active surface disposed on the lead frame, and the active surface defines a central area and a peripheral area; A plurality of first conductive bumps are placed on the peripheral area of the active surface of the chip for the chip to be disposed and electrically connected to the pins of the lead frame; A plurality of second conductive bumps, placed in the central area of the active surface of the chip, as the external electrical connection terminals of the package; and The encapsulant is used to cover the chip, the first and second conductive bumps and the lead frame, wherein the lower surface of the pin and the lower surface of the second conductive bump are exposed from the encapsulant. 2. The semiconductor package as claimed in claim 1, wherein the active surface of the chip further comprises a redistribution layer for distributing the electrical contacts of the chip in the central area and the peripheral area of the chip. 3. The semiconductor package as claimed in claim 1, wherein the first conductive bump is connected to an input/output contact on the active surface of the chip. 4. The semiconductor package of claim 1, wherein the second conductive bumps are selectively connected to power, ground and I/O contacts on the active surface of the chip. 5. The semiconductor package as claimed in claim 1, wherein the size of the second conductive bump is larger than the size of the first conductive bump. 6. The semiconductor package as claimed in claim 1, further comprising a solder layer formed on the bottom surface of the pin. 7 . The semiconductor package as claimed in claim 1 , wherein the encapsulant and the lower surface of the pin are polished to expose the lower surface of the second conductive bump. 8. The semiconductor package according to claim 1, wherein the lead frame further comprises a conductive sheet and pins arranged around the conductive sheet, and part of the second conductive bumps are arranged and electrically connected to the conductive sheet. 9. The semiconductor package as claimed in claim 8, wherein the conductive sheet, the pins and the lower surface of the encapsulant are ground to expose the lower surface of the second conductive bump that is not disposed on the conductive sheet . 10. The semiconductor package as claimed in claim 8, further comprising a solder layer formed on the conductive sheet and the bottom surface of the pin. 11. A method for manufacturing a semiconductor package, characterized in that the steps of the method for manufacturing a semiconductor package include: preparing a lead frame and a chip, the lead frame has a plurality of pins, and the chip has an active surface, and defines a central region at the center of the active surface and a circumferential region around the active surface; implanting a plurality of first conductive bumps on the peripheral area of the chip, and implanting a plurality of second conductive bumps on the central area of the chip; bonding the first conductive bump implanted on the chip to the upper surface of the corresponding pin of the lead frame; forming an encapsulant for covering the chip, the first and second conductive bumps and the lead frame; and Grinding the encapsulation colloid and the lower surface of the pin to expose the lower surface of the second conductive bump. 12 . The method of manufacturing a semiconductor package as claimed in claim 11 , wherein a redistribution layer is formed on the active surface of the chip to distribute the electrical contacts of the chip in a central area and a peripheral area of the chip. 13 . 13 . The method for manufacturing a semiconductor package as claimed in claim 11 , further comprising plating a solder layer on the lower surface of the pin. 14 . 14. The manufacturing method of a semiconductor package as claimed in claim 11, wherein the chip is electrically connected to the lead frame in a flip-chip manner. 15. The method of manufacturing a semiconductor package as claimed in claim 11, wherein the first conductive bump is an input/output contact connected to the active surface of the chip. 16. The semiconductor package manufacturing method of claim 11, wherein the second conductive bumps are selectively connected to power, ground and I/O contacts on the active surface of the chip. 17. The method of manufacturing a semiconductor package as claimed in claim 11, wherein the size of the second conductive bump is larger than the size of the first conductive bump. 18. The method for manufacturing a semiconductor package according to claim 11, wherein the lead frame further comprises a conductive sheet and pins arranged around the conductive sheet, and part of the second conductive bump is provided and electrically connected connected to the conductive strip. 19. The method for manufacturing a semiconductor package according to claim 18, wherein the conductive sheet, the pins, and the bottom surface of the encapsulant are ground to expose the second conductive bumps not arranged on the conductive sheet lower surface. 20. The manufacturing method of a semiconductor package as claimed in claim 18, wherein a solder layer is formed on the conductive sheet and the lower surface of the pin.

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